CN215773085U

CN215773085U - Gray code counter circuit

Info

Publication number: CN215773085U
Application number: CN202121509890.0U
Authority: CN
Inventors: 赵照
Original assignee: Hefei Xinfoo Sensor Technology Co ltd
Current assignee: Hefei Xinfoo Sensor Technology Co ltd
Priority date: 2021-07-05
Filing date: 2021-07-05
Publication date: 2022-02-08
Anticipated expiration: 2031-07-05

Abstract

The application discloses gray code counter circuit builds gray code output unit through logic circuit or trigger, and a plurality of gray code output unit constitute gray code counter circuit. Compared with the traditional Gray code counter circuit, the Gray code counter circuit provided by the application does not need to build a binary counter firstly and then convert the binary counter into a Gray code format through a logic circuit, the power consumption of the circuit is low, elements contained in the circuit are few, and the circuit structure is simple.

Description

Gray code counter circuit

Technical Field

The application relates to the technical field of circuits, in particular to a Gray code counter circuit.

Background

Gray code is a cyclic binary code or called as a reflective binary code, when the Gray code is changed from a number to an adjacent number, only one data bit jumps, and based on the characteristics, the possibility of error caused by simultaneous overturning of multiple bits of a binary coding counting combination circuit can be avoided when counting results are acquired through an asynchronous clock, the metastable state appearing in the circuit can be avoided, the circuit can work at a higher speed with fewer errors, and the anti-interference capability of the system is improved.

The gray code counter circuit is one of the common basic circuits in a digital circuit, the gray code is commonly used in a communication, FIFO or RAM address addressing counter, the traditional gray counter method is that a binary counter is built firstly, and then the binary counter is coded into a gray code format through an exclusive-OR gate, and as burrs are generated in the coding process, the gray code after being coded is finally output and also needs to be sampled through a D trigger. Each D flip-flop unit operates at the highest input frequency, and the circuit needs to consume large power consumption.

SUMMERY OF THE UTILITY MODEL

In view of this, the present application provides a gray code counter circuit, which directly performs gray code counting, does not need to convert binary codes through a logic circuit, and has low circuit power consumption.

In order to solve the technical problem, the following technical scheme is adopted in the application:

the application provides a gray code counter circuit, gray code counter circuit includes:

the N output units are used for outputting N-bit Gray codes, wherein N is a positive integer;

the N output units comprise a first output unit to an Nth output unit;

a first output unit comprising:

the clock end of the first trigger is connected with a clock signal, and the clock end of the second trigger is connected with the inverted output end of the first trigger;

a second output unit comprising:

a first input end of the first AND gate is connected with a positive phase output end of the first trigger, and a second input end of the first AND gate is connected with a positive phase output end of the second trigger;

a clock end of the third trigger is connected with the output end of the first AND gate;

a third output unit including:

the input end of the first inverter is connected with the non-inverting output end of the second trigger;

a first input end of the second AND gate is connected with the positive phase output end of the first trigger, a second input end of the second AND gate is connected with the positive phase output end of the third trigger, and a third input end of the second AND gate is connected with the output end of the first phase inverter;

a clock end of the fourth trigger is connected with the output end of the second AND gate;

an Mth output unit, wherein M is greater than or equal to 4 and less than or equal to N, and M is a positive integer, comprising:

the input end of the M-3 clock control unit is connected with the output end of the trigger;

the first input end of the M-1 AND gate is connected with the positive phase output end of the first trigger, the second input end of the M-1 AND gate is connected with the positive phase output end of the Mth trigger, and the third input end of the M-1 AND gate is connected with the output end of the M-3 clock control unit;

the clock end of the M +1 th trigger is connected with the output end of the M-1 th AND gate;

and the inverted output end of each trigger is connected with the data end of the trigger.

Preferably, the mth output unit includes an M-3 clock control unit, an input end of the M-3 clock control unit is connected to an output end of the flip-flop, a third input end of the M-1 and gate is connected to an output end of the M-3 clock control unit, and the method includes: the M-th output unit comprises an M-3 NOR gate, the input end of the M-3 NOR gate is connected with the non-inverting output end of the second flip-flop to the M-1 flip-flop, and the third input end of the M-1 AND gate is connected with the output end of the M-3 NOR gate.

Preferably, the mth output unit includes an M-3 clock control unit, an input end of the M-3 clock control unit is connected to an output end of the flip-flop, a third input end of the M-1 and gate is connected to an output end of the M-3 clock control unit, and the method includes: the Mth output unit comprises an M-3 NOR gate and at least one NAND gate, the input end of the at least one NAND gate is connected with the inverted output ends of the second flip-flop and the M-1 flip-flop, the input end of the M-3 NOR gate is connected with the output end of the at least one NAND gate, and the third input end of the M-1 AND gate is connected with the output end of the M-3 NOR gate.

Preferably, the flip-flop is a D flip-flop.

Compared with the prior art, the method has the following beneficial effects:

according to the technical scheme, the gray code counter circuit provided by the application is characterized in that the gray code counter circuit is directly built through the logic circuit and the trigger, and compared with the traditional gray code counter circuit, the gray code counter circuit provided by the application does not need to build a binary counter firstly and then converts the binary counter into a gray code format through the logic circuit, the power consumption of the circuit provided by the application is low, elements contained in the circuit are few, and the circuit structure is simple.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1 is a logic circuit diagram of a first output unit according to an embodiment of the present disclosure.

Fig. 2 is a second output unit logic circuit diagram provided in an embodiment of the present application.

Fig. 3 is a logic circuit diagram of a third output unit according to an embodiment of the present application.

Fig. 4 is a logic circuit diagram of an mth output unit according to an embodiment of the present application.

Fig. 5 is a logic circuit diagram of another output unit according to an embodiment of the present disclosure.

Fig. 6 is a logic circuit diagram of an N-bit gray code counter according to an embodiment of the present disclosure.

Fig. 7 is a waveform diagram of an output signal of a logic circuit of a gray code counter according to an embodiment of the present application.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described and will be readily apparent to those of ordinary skill in the art without departing from the spirit of the present invention, and therefore the present invention is not limited to the specific embodiments disclosed below.

Before introducing the gray code counter circuit, the encoding rule of the gray code is first introduced, referring to the following table.

Decimal system	Binary system	Gray code	Decimal system	Binary system	Gray code
						0	0000	0000	8	1000	1100
1	0001	0001	9	1001	1101
						2	0010	0011	10	1010	1111
3	0011	0010	11	1011	1110
						4	0100	0110	12	1100	1010
5	0101	0111	13	1101	1011
						6	0110	0101	14	1110	1001
7	0111	0100	15	1111	1000

Defining the highest bit of the N-bit Gray code as the Nth bit and the lowest bit as the 1 st bit. From the above table, the following rule is easily known for the gray code flip change in the counting period:

rule 1: if the reset state of the 4-bit gray code counter is 0000, the 1 st bit of the gray code in the counting process is subjected to a 0110 state cycle, for example, corresponding to decimal digits 0 to 3, the lowest bits of the gray code are 0, 1 and 0 respectively, corresponding to decimal digits 4 to 7, and the lowest bits of the gray code are 0, 1 and 0 respectively.

Referring to fig. 1, in terms of circuit implementation, an output unit formed by cascading two stages of flip-flops in a divide-by-2 manner may be used to implement state inversion of the 1 st bit of the gray code.

Specifically, the output unit for outputting the 1 st bit of the gray code is a first output unit, the first output unit includes a first flip-flop and a second flip-flop, a clock end of the first flip-flop is connected to the clock signal ckin, a clock end of the second flip-flop is connected to an inverted output end of the first flip-flop, inverted output ends of the first flip-flop and the second flip-flop are respectively connected to data ends of the first flip-flop and the second flip-flop, reset ends of the first flip-flop and the second flip-flop are connected to a reset signal, and a normal phase output end of the second flip-flop is used for outputting the 1 st bit of gray code Q <1>, i.e., the lowest bit gray code. The frequency of the non-inverting output signal ckn of the first flip-flop is one-half of the input clock signal ckin, and the clock terminal of the second flip-flop is connected to the non-inverting output signal ckn of the first flip-flop, so that the frequency of the non-inverting output signal Q <1> of the second flip-flop is one-half of the frequency of the non-inverting output signal ckn of the first flip-flop, and therefore, the frequency of the non-inverting output signal Q <1> of the second flip-flop is one-quarter of the frequency of the input clock signal ckin.

Rule 2: if and only if the 1 st bit toggles from 0 to 1 in the current count cycle, then the 2 nd bit toggles in the next count cycle. For example, for 4-bit gray codes 0001, 0111, 1101, and 1011, it is satisfied that the 1 st bit is flipped from 0 to 1 in the current counting period, then the 2 nd bit is flipped in the next counting period, and the next counting period corresponds to 0011, 0101, 1111, and 1001, respectively.

Referring to fig. 2, in circuit implementation, an output unit composed of an and gate and a flip-flop may be used to implement the state inversion of the 2 nd bit of the gray code.

Specifically, the output unit for outputting the 2 nd bit of the gray code is a second output unit, the second output unit includes a first and gate, a first input end of the first and gate is connected to a positive phase output end of the first flip-flop, a second input end of the first and gate is connected to a positive phase output end Q <1> of the second flip-flop, that is, the 1 st bit of the gray code, the second output unit further includes a third flip-flop, a clock end of the third flip-flop is connected to the first nand gate output end, an inverted output end of the third flip-flop is connected to a data end of the third flip-flop, a reset end of the third flip-flop is connected to a reset signal, and the positive phase output end Q <2> of the third flip-flop is used for outputting the 2 nd bit of the gray code. When Q <1> is inverted from 0 to 1, the AND gate output is inverted from 0 to 1 at ckn signal next clock cycle, generating rising edge to trigger the third flip-flop, and realizing Q <2> inversion.

Rule 3: and if and only if the M-1 bit is 1, the M-2 bits and the subsequent low bits are all 0, and the 1 st bit is turned from 1 to 0 in the current counting period, turning the M bit in the next counting period, wherein M is more than or equal to 3 and less than or equal to N, and M is a positive integer.

For example, when M is 3, it is satisfied that the 2 nd bit is 1, the 1 st bit is 0, and the two 4-bit gray codes of the 1 st bit that are flipped from 1 to 0 in the current counting period are 0010 and 1110, then the 3 rd bit is flipped in the next counting period, and the gray codes of the next counting period corresponding to the two gray codes are 0110 and 1010, respectively.

For another example, when M is 4, it is satisfied that the 3 rd bit is 1, the 1 st bit and the 0 th bit are both 0, and the gray code of the 1 st bit that is flipped from 1 to 0 in the current counting period is 0100, then the 4 th bit is flipped in the next counting period, and the gray code of the next counting period corresponding to the gray code is 1100.

When M =3, referring to fig. 3, in terms of circuit implementation, an output unit composed of an inverter, an and gate, and a flip-flop may be used to implement state inversion of the 3 rd bit of the gray code.

Specifically, the output unit for outputting the 3 rd bit of the gray code is a third output unit, and the third output unit includes: the input end of the first inverter is connected with the positive phase output end Q <1> of the second trigger; the first input end of the second AND gate is connected with the positive phase output end of the first trigger, the second input end of the second AND gate is connected with the positive phase output end of the third trigger, and the third input end of the second AND gate is connected with the output end of the first phase inverter; and a clock end of the fourth trigger is connected with the output end of the second AND gate, an inverted output end of the fourth trigger is connected with a data end of the fourth trigger, a reset end of the fourth trigger is connected with a reset signal, and a normal phase output end of the fourth trigger is used for outputting a 3 rd-bit Gray code. When Q <1> is inverted from 1 to 0 and Q <2> is equal to 1, in ckn signal next counting period, AND gate output is inverted from 0 to 1, generating rising edge to trigger the fourth flip-flop, and realizing Q <3> inversion.

When M is greater than or equal to 4 and less than or equal to N, referring to fig. 4, in terms of circuit implementation, an output unit composed of a clock control unit, an and gate and a flip-flop may be used to implement the state inversion of the mth bit of the gray code, where the clock control unit may be an M-3 nor gate.

Specifically, an output unit for outputting the mth bit of the gray code is an mth output unit, the mth output unit includes an M-3 nor gate, and an input terminal of the M-3 nor gate is connected to the second flip-flop to a non-inverting output terminal of the M-1 flip-flop, that is, the 1 st bit to the M-2 nd bit of the gray code; the first input end of the M-1 AND gate is connected with the positive phase output end of the first trigger, the second input end of the M-1 AND gate is connected with the positive phase output end of the Mth trigger, and the third input end of the M-1 AND gate is connected with the output end of the M-3 NOR gate; the clock end of the M +1 th trigger is connected with the output end of the M-1 th AND gate, the inverted output end of the M +1 th trigger is connected with the data end of the M +1 th trigger, the reset end of the M +1 th trigger is connected with a reset signal, and the positive phase output end of the M +1 th trigger is used for outputting an M-th gray code. When Q <1> is turned from 1 to 0, Q <2> to Q < M-2> are both 0, and Q < M-1> is 1, in the next counting period of the ckn signal, the output of the AND gate is turned from 0 to 1, a rising edge is generated to trigger the fourth trigger, and the turning of Q < M > is realized.

It should be noted that when M is greater than the number of input ports of the nor gates, the clock control unit in the mth output unit may be an M-3 th nor gate and at least one nand gate.

Specifically, the inverting output terminals of the second to M-1 th flip-flops may be connected to a nand gate, and the output terminal of the nand gate is connected to the input terminal of the nor gate, where the number of the nand gates may be multiple, and the input signal of each nand gate is the inverting output signal of the flip-flop.

For example, when M is 13, three nand gates are added to the 13 th output unit for outputting the 13 th bit of the gray code, and referring to fig. 5, the input terminals of the nand gates are respectively connected to the 1 st to 4 th bit inverted outputs, the 5 th to 8 th bit inverted outputs, and the 9 th to 11 th bit inverted outputs of the gray code. The purpose of adding the nand gate at the preceding stage of the nor gate is to ensure that the condition that M-2 bits and the following low bits are all 0 is met, in order to trigger the condition that the mth bit is inverted, the output of the nor gate needs to be 1, the output of the nand gate at the preceding stage of the nor gate needs to be 0, and the inputs of the nand gate need to be 1, so the input end of the nand gate is connected with the inverted output of the low-bit gray code.

It should be noted that, the input signal of the combinational logic gate may also be partially output in reverse phase of the low level gray code and partially output in positive phase of the low level gray code, if the input signal is output in reverse phase of the low level gray code, the signal needs to be connected to the input terminal of the preceding nand gate in the combinational logic gate, if the input signal is output in positive phase of the low level gray code, the signal needs to be connected to the input terminal of the succeeding nor gate in the combinational logic gate, and it is only necessary to satisfy that all the low levels of the M-2 th bit and the following low levels are 0 as the logic of the triggering signal for the M-th bit flipping, and the application does not limit the input position of the input signal.

Fig. 6 is a schematic diagram of an N-bit gray code counter circuit structure provided by the application, including N output units in the N-bit gray code counter circuit, each output unit is used for outputting one-bit gray code, the N-bit gray code counting function is realized, the gray code counter circuit provided by the application does not need to build a binary counter and transcodes into a gray code format again, the circuit power consumption provided by the application is smaller, the elements contained in the circuit are fewer, and the circuit structure is simpler.

Fig. 7 is a waveform diagram of an output signal of a 4-bit gray code counter circuit provided in the present application, in which a gray code composed of the least significant bit Q <1> to the most significant bit Q <4> continuously changes in a counting period according to a gray code counting rule.

The foregoing is only a preferred embodiment of the present invention, and although the present invention has been disclosed in the preferred embodiments, it is not intended to limit the present invention. Those skilled in the art can make numerous possible variations and modifications to the present teachings, or modify equivalent embodiments to equivalent variations, without departing from the scope of the present teachings, using the methods and techniques disclosed above. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.

Claims

1. A gray code counter circuit, comprising:

the N output units comprise a first output unit to an Nth output unit;

a first output unit comprising:

a second output unit comprising:

a third output unit including:

the inverted output end of each trigger is connected with the data end of the trigger;

and the reset end of each trigger is connected with a reset signal.

2. The gray code counter circuit of claim 1, wherein the mth output unit comprises an M-3 clock control unit, an input terminal of the M-3 clock control unit is connected to an output terminal of the flip-flop, a third input terminal of the M-1 and gate is connected to an output terminal of the M-3 clock control unit, and the gray code counter circuit comprises:

the M-th output unit comprises an M-3 NOR gate, the input end of the M-3 NOR gate is connected with the non-inverting output end of the second flip-flop to the M-1 flip-flop, and the third input end of the M-1 AND gate is connected with the output end of the M-3 NOR gate.

3. The gray code counter circuit of claim 1, wherein the mth output unit comprises an M-3 clock control unit, an input terminal of the M-3 clock control unit is connected to an output terminal of the flip-flop, a third input terminal of the M-1 and gate is connected to an output terminal of the M-3 clock control unit, and the gray code counter circuit comprises:

the Mth output unit comprises an M-3 NOR gate and at least one NAND gate, the input end of the at least one NAND gate is connected with the inverted output ends of the second flip-flop and the M-1 flip-flop, the input end of the M-3 NOR gate is connected with the output end of the at least one NAND gate, and the third input end of the M-1 AND gate is connected with the output end of the M-3 NOR gate.

4. A gray code counter circuit according to any of claims 1 to 3, wherein the flip-flop is a D flip-flop.