CN115914870A - Low-power-consumption reading circuit based on self-adaptive counting mode - Google Patents
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Abstract
The invention relates to the technical field of integrated circuits, in order to obviously reduce the power consumption of SS ADC on the premise of ensuring the low noise and high linearity of the SS ADC, the invention provides a low-power-consumption reading circuit based on a self-adaptive counting mode, which comprises: the device comprises a ramp generator, a global counter, a low-power consumption comparator, an M-bit latch, a logic unit and an N-bit U/D DDR counter; the ramp generator is connected to the inverting input end of the low-power-consumption comparator, the non-inverting input end of the low-power-consumption comparator inputs a pixel photosensitive signal, the output end of the low-power-consumption comparator is connected to the logic unit and the global counter, the global counter outputs the pixel photosensitive signal to the M-bit latch and the logic unit, and the logic unit sends a control signal to the N-bit U/D DDR counter. The invention is mainly applied to the integrated circuit design and manufacture occasions.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a low-power-consumption reading circuit structure based on a self-adaptive counting mode.
Background
A column-parallel Single-Slope Analog-to-digital Converter (SS ADC) is widely applied to a CMOS Image Sensor (CIS) due to its advantages of simple structure, high linearity, and the like. However, as the integration level and the operating frequency are continuously increased, the power consumption of the conventional column-parallel SS ADC is more difficult to control and reduce, and becomes one of the main factors limiting the speed and stability of the column-parallel SS ADC.
The power consumption of the SS ADC is mainly derived from two aspects, namely static power consumption from the comparator on the one hand and dynamic power consumption from the counter on the other hand. In the aspect of static power consumption, because the static power consumption is not influenced by frequency, the extremely low power consumption can be realized by reducing the current of the comparator; in terms of dynamic power consumption, a DDR (Double Data Rate) counter is mainly used at present, and an operating clock can be reduced by one time. However, the operating mode of the SS ADC is limited, and with the increase of the operating frequency of the CIS chip, how to realize ultra-low power consumption of counting is still a key issue of the development of the SS ADC.
Disclosure of Invention
Aiming at overcoming the defects of the prior art and aiming at the problem of overhigh dynamic power consumption of the SS ADC, the invention aims to provide a low-power-consumption counting mode with a self-adaptive function and a corresponding circuit structure based on the principle that the optical signal received by the traditional 4T pixel does not generate mutation. On the premise of ensuring low noise and high linearity of the SS ADC, only the counting mode is changed, and the power consumption of the SS ADC is obviously reduced. Therefore, the invention adopts the technical scheme that the low-power-consumption reading circuit based on the self-adaptive counting mode comprises two parts of global circuits: a ramp generator and an M-bit global counter; 4 parts of column stage circuits: the device comprises a low-power consumption comparator, an M-bit latch, a logic unit and an N-bit U/D DDR counter; the ramp generator is connected to the inverting input end of the low-power comparator, the non-inverting input end of the low-power comparator inputs a pixel photosensitive signal, the output end of the low-power comparator is connected to the logic unit and the M-bit global counter, and the M-bit global counter outputs an M-bit counting result Q global <1:M>To the M-bit latch and the logic unit, each column of M-bit latch will store the Q in the next row period global <1:M>High M-bit count result Q as per column local <N-M+1:N>And the output is transmitted to a logic unit, and the logic unit sends a control signal to the N-bit U/D DDR counter.
The N-bit U/D DDR counter comprises a DDR counting structure, a built-in control unit and an (N-1) -bit U/D counter, wherein the (N-1) -bit DDR counting structure needs to guarantee that the initial input state of a clock is known, and the start and stop of counting are controlled through a count _ en and a count _ enb, wherein the count _ enb is the inverse of the count _ en; the output clock of the NOR gate starts with the rising edge and ends with the falling edge, so when even number of trigger edges are input, the quantity difference of the rising edges output by the NOR gate and the NAND gate is 1, when odd number of trigger edges are input, the quantity difference of the rising edges output by the NOR gate and the NAND gate is 0, the NAND gate and the NOR gate are respectively connected with the clock control end of a D trigger to store the difference, the output of the two D triggers is judged to be odd or even through the rear XOR gate, and the rear end of the XOR gate is connected with the input end of the internal connection control unit, so that the lowest order output is determined; in the control unit, the input end of the built-in control unit is connected with the input end of a NOR gate, and the input end of the NOR gate and the carry signal are processed by a D trigger to finish lowest bit quantization; the positive and negative output ends of the D trigger are connected with two input multiplexers, and the carry signal and the UD signal jointly control the gating of the multiplexers so as to control the carry from the lowest bit to the next lowest bit of the counter; the built-in control unit is connected with the clock input end of the (N-1) -bit U/D counter and controls the following counter to finish counting.
In the logical unit: q global <1:M>The quantization result Q of the last cycle stored in the AND latch local <N-M+1:N>And comparing by a digital comparator, wherein the comparator is formed by alternately connecting an exclusive-nor gate and a nand gate in series, and the comparison result of the digital comparator is a signal lp _ sig. lp _ sig is a control signal for starting and stopping counting and the counting direction, the signal is transmitted to a NOR gate and used as a clock to drive a D trigger, the D trigger can identify the rising edge of the lp _ sig and transmit the rising edge to an output end, counter _ UD is a control signal for the counting direction of the counter, the signal and one end of the D trigger are output to control the counting direction of the counter through an XOR gate, the output of the XOR gate is connected with a transmission gate, and the control signal for the transmission gate is comparisonThe output of the device and the output of the transmission gate of the dynamic counting direction control signal UD are realized as follows: if the actual comparison result is greater than the predicted result, the output of the exclusive-or gate changes before the comparator jumps, so that the counting direction is changed; if the actual comparison result is smaller than the prediction result, the comparator jumps first, then the switch is closed, and the counting direction is unchanged; thus, the dynamic adjustment of the counting direction can be realized, and the correctness of the counting direction is ensured; the output of the other end of the D flip-flop and the output comp of the comparator are used as two input ends of the exclusive-OR gate, and the initial state of the output end of the exclusive-OR gate is low level. The output of the exclusive or gate changes to a high level when one of the two inputs of the exclusive or gate changes and changes back to a low level when the other signal also changes. The output of the exclusive-OR gate is high level, the counter _ en is an enable signal for controlling the counter to work, and the output of the exclusive-OR gate and the counter _ en signal generate a counting start-stop control signal count _ en through an AND gate; in addition, the input clock signal is connected with the D flip-flop, the counter _ HD is a counter holding signal, and a dynamic holding signal HD is output and controls the D flip-flop to be in a latch state, so that counting can not be carried out any more.
The invention has the characteristics and beneficial effects that:
the invention provides a low-power-consumption SS ADC with a self-adaptive counting mode, which predicts a counting result through a previous line period, completes high-frequency counting only when residual errors are quantized, greatly saves power consumption, and is particularly suitable for a scene with a low dynamic range. Meanwhile, by improving the structure of the DDR counter, the counter is driven to work only when counting is needed, power consumption from a high-frequency clock can be further saved, and finally quantization is completed with extremely low dynamic power consumption.
Description of the drawings:
fig. 1 is a schematic diagram of a low power ADC with adaptive functional counting.
Fig. 2 is a schematic diagram of a low power consumption ADC with adaptive counting.
FIG. 3 is a schematic diagram of an N-bit U/D DDR counter.
Fig. 4 is a schematic diagram of a logic cell.
Fig. 5 is a timing diagram of the operation of the counter portion of the low power ADC with adaptive counting.
Detailed Description
The basic operation principle of the low-power-consumption reading circuit based on the self-adaptive counting mode is shown in fig. 1. Compared with the traditional SS ADC, the core idea of the design is to quantize the residual error between the previous line period and the current line period. As shown in fig. 1, in the nth line period, the quantization is completed by a global counter with a slower operation frequency, simultaneously with the completion of the quantization by the column counter. In the (n + 1) th line period, the initial value of the column counter is the quantization result of the n-th line period global counter, and the quantization of the (n + 1) th line period can be completed only by quantizing the difference between the initial value and the (n + 1) th line period on the basis.
The circuit structure of the low-power-consumption reading circuit based on the self-adaptive counting mode is shown in fig. 2. The whole circuit structure consists of 6 main parts, including a ramp generator, an M-bit global counter, a low-power consumption comparator, an M-bit latch, a logic unit and an N-bit U/D DDR counter 4 part column stage circuit.
The detailed schematic diagram of the N-bit U/D DDR counter in the core circuit structure of the invention is shown in FIG. 3. The counter consists of an improved DDR counting structure, a built-in control unit and a traditional (N-1) -bit U/D counter. The conventional DDR counting structure needs to ensure that the initial input state of the clock is known, that is, when counting is started, the input clock of the counter must be fixed from '0' (or '1'), otherwise, counting error occurs, which obviously makes it difficult to satisfy the requirement of the counting method of the present invention. The counter of the invention improves the lowest order circuit structure based on the traditional DDR counter, and is mainly characterized in that a clock can be randomly intercepted to finish double data rate counting. In this counter, the start and stop of counting is controlled by count _ en, and the signal and clock pass through a nand gate and nor gate, respectively. The clock output by the NAND gate starts with a falling edge and ends with a rising edge; the nor gate output must start clocked with a rising edge and end with a falling edge. Therefore, when an even number of trigger edges are input, the rising edge numbers of the output of the NOR gate and the NAND gate are different by 1, and when an odd number of trigger edges are input, the rising edge numbers of the output of the NOR gate and the NAND gate are different by 0. The NAND gate and the NOR gate are respectively connected with the clock control end of a D flip-flop to store the difference. The output of the two D flip-flops can judge whether the edge of the input is an odd number or an even number through an exclusive-OR gate at the rear part. The XOR gate is connected with the input end of the built-in control unit, so that the lowest bit output is determined. Inside the control unit, the signal is connected to the input end of the NOR gate and is quantized with the carry signal by the D flip-flop to the lowest bit. The positive and negative output ends of the D flip-flop are connected with two input multiplexers, and the carry signal and the UD signal jointly control the gating of the multiplexers, so that the lowest bit to the next lowest bit of the counter is controlled to carry. The built-in control unit is connected with the clock input end of the (N-1) -bit U/D counter and controls the following asynchronous counter to finish counting.
A detailed schematic diagram of the logic unit in the core circuit structure of the present invention for generating the dynamic count direction control signal UD, the dynamic hold signal HD, and the count start-stop signal count _ en is shown in fig. 4. Q global <1:M>And the quantization result Q of the last cycle stored in the latch local <N-M+1:N>The comparison is completed through a digital comparator which is formed by alternately connecting an exclusive-OR gate and a NAND gate in series, a control signal lp _ sig is output and transmitted to a NOR gate to serve as a clock to drive a D trigger, and the D trigger can identify the rising edge of the lp _ sig and transmit the rising edge to the output end. One end output of the D flip-flop and the counter _ UD control the counting direction of the counter together through an exclusive-OR gate. The output of the exclusive-or gate is connected with the transmission gate, and the control signal of the transmission gate is output by the comparator, so that the functions of: if the actual comparison result is larger than the prediction result, the output of the exclusive-or gate changes before the jump of the comparator, so that the counting direction can be changed; if the actual comparison result is larger than the predicted result, the comparator jumps first, the switch is closed, and the counting direction is unchanged. Therefore, the dynamic adjustment of the counting direction can be realized, and the correctness of the counting direction is ensured. The output of the other end of the D flip-flop and the output of the comparator comp pass through an XOR gate, and one of the two inputs is changedThe output of the time-varying exclusive-OR gate changes to high level, and the output of the exclusive-OR gate changes to low level when the other signal also changes, so that a counting interval is formed. The output of the exclusive-or gate and the counter _ en signal generate a count valid signal count _ en through the and gate. In addition, the clock synchronization count is improved, as in the lower right circuit of fig. 4. The clock is connected to the D flip-flop and output as a dynamic hold signal HD. The improved circuit has two advantages, on one hand, before HD does not become high level, the counter is in a latch state, only when the rising edge of the clock comes, the counter can count, and the clock synchronization can be ensured. On the other hand, the counter is still in a latch state when UD is changed, and the counter is not carried due to the switching of the counting direction.
Fig. 5 shows waveforms of control signals input from the outside of the column stage circuit according to the present invention, and the signal waveforms correspond to the same-name signals in fig. 2, 3, and 4 one by one.
The invention provides a counting mode with a self-adaptive function and a circuit structure by utilizing the characteristic that optical signals received by pixels cannot generate mutation and a method for predicting a next line period through a previous line period. Compared with the existing counting mode, the method has the advantages that the overturning number of the counter is greatly reduced in a prediction mode, so that the power consumption is reduced, and the method is particularly suitable for the imaging condition with a low dynamic range. On the basis of the traditional DDR counter, the invention improves the lowest order counting structure, so that the clock does not need to work all the time, a certain section of unknown initial state clock can be intercepted at will to finish correct counting, the power consumption is further reduced, and the low-power SS ADC applied to the CIS is realized.
From the above technical solutions, the overall circuit structure of the low power consumption SS ADC is shown in fig. 2, and with reference to fig. 1, the working process of the low power consumption SS ADC provided by the present invention is as follows:
(1) Firstly, in the nth line period, when the pixel signal pixel (n) is equal to the ramp signal ramp, the output comp of the comparator is inverted, the M-bit latch is controlled to enter a latch state from a transparent state, and the global counting result is stored as Q local <N-M+1:N>；
(2) In the (n + 1) th line period, the reset phase will be fullThe local counter is reset to 0 and the column counter high M-bit is reset to Q local <N-M+1:N>The low (N-M) -bit is reset to 0.
(3) When the ramp starts to fall, the global counter starts to operate, and the counting process of the column counter can be divided into two cases. If comp first turns over, as at time t1 in fig. 1, the counter starts counting down until time t 2. Wherein the time t2 is the output and Q of the global counter local <N-M+1:N>At the same time, the time logic unit sends a counting cut-off signal to the column counter; if the inversion occurs after comp, as shown at time t3 in fig. 1, the counter starts counting up from time t2 and stops at time t 3.
Through the steps, the counting accuracy can be ensured, and the reduction of dynamic power consumption is realized.
The N-bit U/D DDR counter is shown in figure 3, and the working process is as follows: at the starting stage of the line period, the logic unit sets the counter by controlling a Reset signal and a Set signal of the D trigger to enable the counter to be equal to the output result of the global counter in the upper period; in the quantization starting stage, count _ en is low level, the clock CLK does not drive any circuit, the power consumption is extremely low at this time, the output of the NOR gate is determined to be '0', and the output of the NAND gate is determined to be '1'; in the counting stage, count _ en becomes high, and the clock starts to drive the following D flip-flop to start counting. When count _ en becomes low, the nor gate output becomes '0' and the nand gate output becomes '1'. By utilizing the characteristics, when the high level duration of count _ en corresponds to an even number of clock edges, the difference between the rising edges output by the NAND gate and the NOR gate is 1; when the high level duration of count _ en corresponds to an odd number of clock edges, the difference between the rising edges output by the NAND gate and the NOR gate is 0. The difference between the two can be distinguished by an exclusive-or gate, so that the lowest bit of the DDR counter can be counted. The remaining bit counter counts normally. After the counting is finished, the carry controls the lowest bit to finish counting and carrying, and the whole counting process is finished.
The logic unit of the present invention is shown in fig. 4, and the part provides control signals for the counter, and the working process is as follows: a reset phase ofQ local <N-M+2:N>To a comparison unit, Q local <N-M+ 1>Constant '1', which ensures that the delays of comparison are the same and shortest in all cases. When Q is global <1:M>And Q local <N-M+1:N>When the same is true, lp _ sig goes high, controlling the subsequent register output Q to go from low to high. And performing exclusive or on the register output signal and the comparator output signal to obtain a working interval count _ en required by the column counter and the counting direction UD of the counter.
According to the invention, under the working conditions of an 11-bit SS ADC, a 6-bit global counter and 250MHz, when the counting result falls into a prediction interval, the highest dynamic power consumption of each column can be reduced to be less than 10% of that of the traditional SS ADC.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.
Claims (3)
1. A low-power consumption reading circuit based on a self-adaptive counting mode is characterized by comprising two parts of global circuits: a ramp generator and an M-bit global counter; 4 parts of column stage circuits: the device comprises a low-power consumption comparator, an M-bit latch, a logic unit and an N-bit U/D DDR counter; the ramp generator is connected to the inverting input end of the low-power comparator, the non-inverting input end of the low-power comparator inputs a pixel photosensitive signal, the output end of the low-power comparator is connected to the logic unit and the M-bit global counter, and the M-bit global counter outputs an M-bit counting result Q global <1:M>To the M-bit latches and logic cells, each column of M-bit latches will store the Q in the next row cycle global <1:M>As a high M-bit count result Q of each column local <N-M+1:N>And the output is transmitted to a logic unit, and the logic unit sends a control signal to the N-bit U/D DDR counter.
2. The self-adaptive counting mode-based low-power-consumption readout circuit according to claim 1, wherein the N-bit U/D DDR counter comprises a DDR counting structure, a built-in control unit and an (N-1) -bit U/D counter, the (N-1) -bit DDR counting structure needs to ensure that the initial input state of a clock is known, and the start and stop of counting are controlled by count _ en and count _ enb, wherein the count _ enb is the negation of the count _ en, in the DDR counting structure, the count _ en and the clock respectively pass through a nand gate and an nor gate, the clock output by the nand gate must start with a falling edge and end with a rising edge; the output clock of the NOR gate starts with the rising edge and ends with the falling edge, so when even number of trigger edges are input, the quantity difference of the rising edges output by the NOR gate and the NAND gate is 1, when odd number of trigger edges are input, the quantity difference of the rising edges output by the NOR gate and the NAND gate is 0, the NAND gate and the NOR gate are respectively connected with the clock control end of a D trigger to store the difference, the output of the two D triggers is judged to be odd or even through the rear XOR gate, and the rear end of the XOR gate is connected with the input end of the internal connection control unit, so that the lowest order output is determined; in the control unit, the input end of the built-in control unit is connected with the input end of a NOR gate, and the input end of the NOR gate and the carry signal are processed by a D trigger to finish lowest bit quantization; the positive and negative output ends of the D trigger are connected with two input multiplexers, and the carry signal and the UD signal jointly control the gating of the multiplexers so as to control the carry from the lowest bit to the next lowest bit of the counter; the built-in control unit is connected with the clock input end of the (N-1) -bit U/D counter and controls the following counter to finish counting.
3. A low power consumption sensing circuit based on an adaptive counting scheme according to claim 1, wherein in the logic unit: q global <1:M>And the quantization result Q of the last cycle stored in the latch local <N-M+1:N>And comparing by a digital comparator, wherein the comparator is formed by alternately connecting an exclusive-nor gate and a nand gate in series, and the comparison result of the digital comparator is a signal lp _ sig. lp _ sig is a counting start/stop and counting direction control signal which is transmitted to a NOR gate as a clock to drive a D flip-flop which can recognize and transmit the rising edge of lp _ sig to an output terminal, and counter _ UD is a counterThe digital direction control signal and one end of the D trigger output through an exclusive-or gate to control the counting direction of the counter together, the output of the exclusive-or gate is connected with a transmission gate, the transmission gate control signal is output by a comparator, and the transmission gate outputs a dynamic counting direction control signal UD, thus realizing that: if the actual comparison result is greater than the predicted result, the output of the exclusive-or gate changes before the comparator jumps, so that the counting direction is changed; if the actual comparison result is smaller than the prediction result, the comparator jumps first, the switch is closed, and the counting direction is unchanged; thus, the dynamic adjustment of the counting direction can be realized, and the correctness of the counting direction is ensured; the output of the other end of the D flip-flop and the output comp of the comparator are used as two input ends of the exclusive-OR gate, and the initial state of the output end of the exclusive-OR gate is low level. The output of the exclusive or gate changes to a high level when one of the two inputs of the exclusive or gate changes and changes back to a low level when the other signal also changes. The output of the exclusive-OR gate is high level, the counter _ en is an enable signal for controlling the counter to work, and the output of the exclusive-OR gate and the counter _ en signal generate a counting start-stop control signal count _ en through an AND gate; in addition, the input clock signal is connected with the D flip-flop, the counter _ HD is a counter holding signal, and a dynamic holding signal HD is output and controls the D flip-flop to be in a latch state, so that counting can not be carried out any more.
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