CN115914870B - Low-power consumption reading circuit based on adaptive counting mode - Google Patents
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Abstract
The invention relates to the technical field of integrated circuits, in order to obviously reduce the power consumption of an SS ADC on the premise of ensuring the low noise and high linearity of the SS ADC, the invention provides a low-power consumption reading circuit based on an adaptive counting mode, which comprises: the system comprises a slope generator, a global counter, a low-power comparator, an M-bit latch, a logic unit and an N-bit U/D DDR counter; the ramp generator is connected to the inverting input end of the low-power consumption comparator, the non-inverting input end of the low-power consumption comparator inputs pixel photosensitive signals, the output end of the low-power consumption comparator is connected to the logic unit and the global counter, the global counter outputs to the M-bit latch and the logic unit, and the logic unit sends control signals to the N-bit U/D DDR counter. The invention is mainly applied to the design and manufacturing occasions of integrated circuits.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a low-power consumption reading circuit structure based on an adaptive counting mode.
Background
The column parallel monoclinic analog-to-digital converter (Single Slope Analog-to-digital Converter, SS ADC) is widely applied to the CMOS image sensor (CMOS Image Sensor, CIS) due to the advantages of simple structure, high linearity and the like. However, as the integration level and the operating frequency are continuously improved, the power consumption of the conventional column-parallel SS ADC is more and more difficult to control and reduce, and becomes one of the main factors limiting the speed and stability of the column-parallel SS ADC.
The power consumption of SS ADCs is mainly derived from two aspects, on the one hand, static power consumption from the comparator and on the other hand, dynamic power consumption from the counter. The static power consumption is not affected by frequency, so that extremely low power consumption can be realized by reducing the current of the comparator; in terms of dynamic power consumption, a DDR (Double Data Rate) counter is currently mainly used, and the working clock can be reduced by one time. However, due to the operation mode of the SS ADC, as the operating frequency of the CIS chip increases, how to realize ultra-low power consumption of counting is still a key issue for the development of the SS ADC.
Disclosure of Invention
Aiming at the problem of overhigh dynamic power consumption of an SS ADC, the invention aims to provide a low-power consumption counting mode with a self-adaptive function and a corresponding circuit structure based on the principle that an optical signal received by a traditional 4T pixel cannot be suddenly changed. On the premise of ensuring low noise and high linearity of the SS ADC, only the counting mode is changed, so that the power consumption of the SS ADC is obviously reduced. Therefore, the technical scheme adopted by the invention is that the low-power-consumption reading circuit based on the self-adaptive counting mode comprises two parts of global circuits: a ramp generator and an M-bit global counter; 4 part column level circuit: the device comprises a low-power consumption comparator, an M-bit latch, a logic unit and an N-bit U/D DDR counter; the ramp generator is connected to the inverting input end of the low-power consumption comparator, the non-inverting input end of the low-power consumption comparator inputs pixel photosensitive signals, the output end of the low-power consumption comparator is connected to the logic unit and the M-bit global counter, the M-bit global counter outputs M-bit counting results Q global <1:M > to the M-bit latch and the logic unit, each column of M-bit latch can output stored Q global <1:M > to the logic unit in the next row period as high M-bit counting results Q local < N-M+1:N > of each column, and the logic unit sends control signals to the N-bit U/D DDR counter.
The N-bit U/D DDR counter comprises a DDR counting structure, a built-in control unit and an (N-1) -bit U/D counter, wherein the (N-1) -bit DDR counting structure needs to ensure that the initial input state of a clock is known, the start and stop of counting are controlled through a count_en and a count_enb, wherein the count_enb is the counter_en, in the DDR counting structure, the count_enb and the count_en respectively pass through a NAND gate and a NOR gate with the clock, the clock output by the NAND gate is certainly started with the falling edge, and the rising edge is ended; the clock output by the NOR gate is started with a certain rising edge, and the falling edge is ended, so that when an even number of trigger edges are input, the quantity of the rising edges of the NOR gate and the NAND gate output differs by 1, when an odd number of trigger edges are input, the quantity of the rising edges of the NOR gate and the NAND gate output differs by 0, the NAND gate and the NOR gate are respectively connected with a clock control end of a D trigger to store the difference, the output of the two D triggers judges whether the input edge is odd or even through an exclusive-OR gate at the rear, and the exclusive-OR gate is connected with the input end of a built-in control unit in sequence, so that the lowest-order output is determined; inside the control unit, the input end of the built-in control unit is connected with the input end of the NOR gate, and the input end of the built-in control unit and the carry signal together complete the least significant quantization through the D trigger; the positive and negative output ends of the D trigger are connected with two-input multiplexer, and the carry signal and the UD signal jointly control the gating of the multiplexer so as to control the carry from the lowest bit to the next lowest bit of the counter; the built-in control unit is connected with the clock input end of the (N-1) -bit U/D counter and controls the latter counter to finish counting.
In the logic unit: q global <1:M > and the quantized result Q local < N-M+1:N > of the last period stored in the latch are compared by a digital comparator, the comparator is formed by alternately connecting an exclusive OR gate and a NAND gate in series, and the comparison result of the digital comparator becomes a signal lp_sig. The lp_sig is a counting start-stop and counting direction control signal, the signal is transmitted to a NOR gate and used as a clock to drive a D trigger, the D trigger can identify and transmit the rising edge of the lp_sig to an output end, the counter_UD is a counter counting direction control signal, the signal and one end of the D trigger are output through an exclusive OR gate to jointly control the counting direction of the counter, the output of the exclusive OR gate is connected with a transmission gate, the transmission gate control signal is output by a comparator, and the transmission gate outputs a dynamic counting direction control signal UD, so that the following effects are achieved: if the actual comparison result is larger than the predicted result, the output of the exclusive-OR gate changes before the comparator jumps, so that the counting direction is changed; if the actual comparison result is smaller than the predicted result, the comparator jumps first, the switch is closed, and the counting direction is unchanged; thus, the dynamic adjustment of the counting direction can be realized, and the accuracy of the counting direction is ensured; the other end output of the D trigger and the comparator output comp are used as two input ends of the exclusive-OR gate, and the initial state of the output end of the exclusive-OR gate is low level. When one of the two inputs of the exclusive or gate changes, the exclusive or gate output goes high, and when the other signal also changes, the exclusive or gate output goes back low. The output of the exclusive-OR gate works as a counter in a high level, the counter_en is an enabling signal for controlling the counter to work, and the output of the exclusive-OR gate and the counter_en signal generate a counter start-stop control signal counter_en through an AND gate; in addition, the input clock signal is connected to the D flip-flop, counter_hd is a counter hold signal, and a dynamic hold signal HD is output, which controls the D flip-flop to be in a latch state and unable to count any more.
The invention has the characteristics and beneficial effects that:
The invention provides the low-power consumption SS ADC with the self-adaptive counting mode, the counting result is predicted through the last row period, and the high-frequency counting is completed only when residual errors are quantized, so that the power consumption is greatly saved, and the low-power consumption SS ADC is particularly suitable for a scene with a lower dynamic range. Meanwhile, by improving the DDR counter structure, only the counter is driven to work when counting is needed, the power consumption from a high-frequency clock can be further saved, and finally the quantification is completed with extremely low dynamic power consumption.
Description of the drawings:
fig. 1 is a schematic diagram of low power ADC operation with adaptive function counting.
Fig. 2 is a schematic diagram of a low power ADC with adaptive counting function.
FIG. 3N-bit U/D DDR counter schematic diagram.
Fig. 4 is a schematic diagram of a logic cell.
Fig. 5 is a timing diagram of the operation of the counter portion of a low power ADC with adaptive counting.
Detailed Description
The basic working principle of the low-power consumption reading circuit based on the adaptive counting mode is shown in figure 1. Compared with the traditional SS ADC, the core idea of the design is to quantize the residual error between the last line period and the current line period. As shown in fig. 1, in the nth row period, quantization is completed simultaneously with the completion of the column counter, by a global counter having a slower operating frequency. In the n+1th row period, the initial value of the column counter is the quantization result of the global counter of the n-th row period, and the n+1th row period can be quantized only by quantizing the difference value between the initial value and the n+1th row period on the basis.
The circuit structure of the low-power-consumption reading circuit based on the adaptive counting mode is shown in fig. 2. The whole circuit structure is composed of 6 main parts, including a slope generator, an M-bit global counter, a low-power comparator, an M-bit latch, a logic unit and an N-bit U/D DDR counter, and a 4-part column stage circuit.
A detailed schematic diagram of the N-bit U/D DDR counter in the core circuit structure of the present invention is shown in FIG. 3. The counter consists of an improved DDR counting structure, a built-in control unit and a traditional (N-1) -bit U/D counter. The conventional DDR counting structure needs to ensure that the initial clock input state is known, i.e. the counter input clock must be fixed from '0' (or '1'), otherwise counting errors, which obviously makes it difficult to meet the requirements of the counting mode of the present invention. The counter in the invention improves the circuit structure of the least significant bit based on the traditional DDR counter, and is mainly characterized in that a section of clock can be randomly intercepted to complete double data rate counting. In the counter, the start and stop of counting are controlled by count_en, and the signal and the clock pass through a nand gate and a nor gate, respectively. The clock output by the NAND gate is started by a falling edge and the rising edge is ended; the clock output by the nor gate must start with a rising edge and end with a falling edge. Therefore, the nor gate and nand gate output rising edge numbers differ by 1 when an even number of trigger edges are input, and by 0 when an odd number of trigger edges are input. The NAND gate and the NOR gate are respectively connected with a clock control end of a D trigger to save the difference. The output of the two D flip-flops can judge whether the input edge is odd or even through the exclusive OR gate at the rear. The exclusive-or gate is connected with the input end of the built-in control unit, thereby determining the lowest bit output. Inside the control unit, the signal is connected to the NOR gate input terminal, and the lowest bit quantization is completed together with the carry signal through the D trigger. The positive and negative output terminals of the D trigger are connected with the two-input multiplexer, and the carry signal and the UD signal jointly control the gating of the multiplexer so as to control the carry from the lowest bit to the next lowest bit of the counter. The built-in control unit is connected with the clock input end of the (N-1) -bit U/D counter and controls the following asynchronous counter to finish counting.
A detailed schematic diagram of the logic unit in the core circuit structure of the present invention is shown in fig. 4, and is used for generating the dynamic counting direction control signal UD, the dynamic hold signal HD, and the counting start-stop signal count_en. Q global <1:M > and the quantized result Q local < N-M+1:N > of the last period stored in the latch are compared by a digital comparator, wherein the digital comparator is formed by alternately connecting an exclusive OR gate and a NAND gate in series, and a control signal lp_sig is output, and is transmitted to a NOR gate as a clock to drive a D trigger, and the D trigger can recognize the rising edge of the lp_sig and transmit the rising edge to an output end. One end of the D trigger outputs and the counter_UD pass through an exclusive OR gate to jointly control the counting direction of the counter. The output of the exclusive-OR gate is connected with a transmission gate, and a transmission gate control signal is output by a comparator, so that the following functions can be realized: if the actual comparison result is larger than the predicted result, the output of the exclusive-OR gate changes before the comparator jumps, so that the counting direction can be changed; if the actual comparison result is larger than the predicted result, the comparator jumps first, the switch is closed, and the counting direction is unchanged. Therefore, the dynamic adjustment of the counting direction can be realized, and the accuracy of the counting direction is ensured. The other end output of the D trigger and the comparator output comp pass through an exclusive or gate, when one signal in the two inputs changes, the output of the exclusive or gate changes to a high level, and when the other signal also changes, the output of the exclusive or gate changes to a low level, so that a counting interval is formed. The exclusive or gate output and counter en signal generate a count valid signal count en via an and gate. In addition, the clock synchronization count is improved, as in the lower right part of the circuit of fig. 4. The fed clock is connected to the D flip-flop and outputted as a dynamic hold signal HD. The improved circuit has two advantages, on one hand, the counter is in a latch state before the HD is not changed into the high level, and the counter can count only when the rising edge of the clock arrives, so that the clock synchronization can be ensured. On the other hand, when the UD is ensured to be changed, the counter is still in a latch state, and the counter cannot carry due to the switching of the counting direction.
The waveform of the external input control signal of the column-level circuit is shown in fig. 5, and the waveform of the signal corresponds to the same-name signals in fig. 2,3 and 4 one by one.
The invention provides a counting mode and a circuit structure with self-adaptive function by utilizing the characteristic that the optical signals received by pixels can not generate abrupt change and by a method for predicting the period of the next line by the period of the previous line. Compared with the existing counting mode, the invention greatly reduces the turnover number of the counter in a predictive mode, thereby reducing the power consumption and being particularly suitable for imaging conditions with lower dynamic range. The invention improves the lowest bit counting structure on the basis of the traditional DDR counter, so that the clock does not need to work all the time, a certain section of unknown initial state clock can be intercepted at will to finish correct counting, the power consumption is further reduced, and the low-power consumption SS ADC applied to the CIS is realized.
As can be seen from the above technical solution, the overall circuit structure of the low-power SS ADC is shown in fig. 2, and the working process of the low-power SS ADC provided by the invention is as follows in combination with fig. 1:
(1) Firstly, in the nth row period, when the pixel signal pixel (N) is equal to the ramp signal ramp, the comparator output comp is turned over, the M-bit latch is controlled to enter a latch state from a transparent state, and the global counting result is saved as Q local < N-M+1:N >;
(2) In the n+1th row period, the reset phase resets the global counter to 0, while the column counter high M-bit is reset to Q local < N-M+1:N >, and the low (N-M) -bit is reset to 0.
(3) When the ramp starts to fall, the global counter starts to operate, and the counting process of the column counter can be divided into two cases. If comp is flipped first, as at time t1 in fig. 1, the counter starts counting down until time t 2. The time t2 is the time when the output of the global counter is the same as Q local < N-M+1:N >, and the logic unit sends a count cut-off signal to the column counter; if the flip occurs after comp, as at time t3 in fig. 1, the counter starts counting up from time t2 to stop at time t 3.
Through the steps, the counting accuracy can be ensured, and the dynamic power consumption is reduced.
The N-bit U/D DDR counter in the invention is shown in figure 3, and the working process is as follows: the logic unit sets the counter by controlling Reset signals and Set signals of the D trigger to enable the Reset signals and the Set signals to be equal to the output result of the upper period global counter; in the quantization starting stage, count_en is low level, the clock CLK does not drive any circuit, the power consumption is extremely low, the NOR gate output is necessarily 0', and the NAND gate output is necessarily 1'; in the counting stage, count_en becomes high level, and the clock starts to drive the following D flip-flops to start counting. When count_en becomes low, the nor gate output becomes '0', and the nand gate output becomes '1'. By utilizing the characteristics, when the count_en high level duration corresponds to an even number of clock edges, the difference between the rising edge numbers of the NAND gate and the NOR gate output is 1; when the count_en high duration corresponds to an odd number of clock edges, the rising edges of the nand gate and nor gate outputs differ by 0. The difference between the two can be distinguished by an exclusive or gate, so that the counting of the lowest bit of the DDR counter can be completed. The remaining bit counters count normally. After counting is completed, the lowest bit is controlled by carry to complete counting and carry, and the whole counting process is finished.
The logic unit in the invention is shown in fig. 4, and the part provides control signals for the counter, and the working process is as follows: in the reset stage, Q local < N-M+2:N > is transmitted to the comparison unit, and Q local < N-M+1> is constant to be '1', which can ensure that the delay of comparison is the same and the shortest in all cases. When Q global <1:M > is the same as Q local < N-M+1:N >, lp_sig goes high, controlling the subsequent register output Q to go high from low. The register output signal and the comparator output signal are exclusive-ored to obtain the working interval count_en required by the column counter and the counter counting direction UD.
Under the working conditions of an 11-bit SS ADC, a 6-bit global counter and 250MHz, when the counting result falls into a prediction interval, the dynamic power consumption of each column can be reduced to below 10% of the traditional SS ADC at maximum.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the scope of the present invention.
Claims (1)
1. A low-power consumption reading circuit based on an adaptive counting mode is characterized by comprising two parts of global circuits: a ramp generator and an M-bit global counter; 4 part column level circuit: the device comprises a low-power consumption comparator, an M-bit latch, a logic unit and an N-bitU/D DDR counter; the ramp generator is connected to the inverting input end of the low-power consumption comparator, the non-inverting input end of the low-power consumption comparator inputs pixel photosensitive signals, the output end of the low-power consumption comparator is connected to the logic unit and the M-bit global counter, the M-bit global counter outputs M-bit counting results Q global <1:M > to the M-bit latch and the logic unit, each column of M-bit latch can output the stored Q global <1:M > to the logic unit in the next row period as high M-bit counting results Q local < N-M+1:N > of each column, and the logic unit sends control signals to the N-bit U/D DDR counter; the N-bitU/D DDR counter comprises a DDR counting structure, a built-in control unit and an (N-1) -bit U/D counter,
The (N-1) -bit DDR counter needs to ensure that the initial input state of a clock is known, the start and stop of counting are controlled through a count_en and a count_enb, wherein the count_enb is the counter_en, in the DDR counting structure, the count_enb and the clock pass through a NAND gate, the count_en and the clock pass through the NOR gate, the clock output by the NAND gate is certainly started by a falling edge, and the rising edge is ended; the clock output by the NOR gate is started with a certain rising edge, and the falling edge is ended, so that when an even number of trigger edges are input, the quantity of the rising edges of the NOR gate and the NAND gate output differs by 1, when an odd number of trigger edges are input, the quantity of the rising edges of the NOR gate and the NAND gate output differs by 0, the NAND gate and the NOR gate are respectively connected with a clock control end of a D trigger to store the difference, the output of the two D triggers judges whether the input edge is odd or even through an exclusive-OR gate at the rear, and the exclusive-OR gate is connected with the input end of a built-in control unit, so that the lowest-order output is determined; the input end of the built-in control unit is connected with the NOR gate input end, and the NOR gate input end and the carry signal together complete the least bit quantization through the D trigger; the positive and negative output ends of the D trigger are connected with two input multiplexers, and the carry signal and the dynamic counting direction control signal UD jointly control gating of the multiplexers so as to control the carry from the lowest bit to the next lowest bit of the (N-1) -bit U/D counter; the built-in control unit is connected with the clock input end of the (N-1) -bit U/D counter and controls the following (N-1) -bit U/D counter to finish counting;
In the logic unit: q global <1:M > and the quantization result Q local < N-M+1:N > of the last period stored in the latch are compared by a digital comparator, the comparator is formed by alternately connecting an exclusive OR gate and a NAND gate in series, the comparison result of the digital comparator becomes a signal lp_sig, the lp_sig is a counting start-stop and counting direction control signal, the signal is transmitted to a NOR gate and used as a clock to drive a D trigger, the D trigger can recognize and transmit the rising edge of the lp_sig to an output end, the counter_UD is a counter counting direction control signal, the signal and one end output of the D trigger are connected in series, the output of the exclusive OR gate is connected with a transmission gate, the transmission gate control signal is the output of the comparator, and the transmission gate outputs a dynamic counting direction control signal UD, so that the following implementation is realized: if the actual comparison result is larger than the predicted result, the output of the exclusive-OR gate changes before the comparator jumps, so that the counting direction is changed; if the actual comparison result is smaller than the predicted result, the comparator jumps first, the switch is closed, and the counting direction is unchanged; thus, the dynamic adjustment of the counting direction can be realized, and the accuracy of the counting direction is ensured; the other end output and comparator output comp of the D trigger are used as two input ends of an exclusive-OR gate, the initial state of the output end of the exclusive-OR gate is low level, when one signal in the two inputs of the exclusive-OR gate is changed, the output of the exclusive-OR gate is changed to be high level, when the other signal is also changed, the output of the exclusive-OR gate is changed to be low level, the counter works, counter_en is an enabling signal for controlling the counter to work, and the output of the exclusive-OR gate and the counter_en signal generate a counter start and stop control signal counter_en through an AND gate; the input clock signal is connected to the D flip-flop, and the counter_hd is a counter hold signal, and the D flip-flop outputs a dynamic hold signal HD that controls the D flip-flop to be in a latch state and unable to count any more.
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