CN111813179A - Control method and control chip of analog-to-digital converter - Google Patents
Control method and control chip of analog-to-digital converter Download PDFInfo
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- CN111813179A CN111813179A CN202010723215.1A CN202010723215A CN111813179A CN 111813179 A CN111813179 A CN 111813179A CN 202010723215 A CN202010723215 A CN 202010723215A CN 111813179 A CN111813179 A CN 111813179A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/10—Distribution of clock signals, e.g. skew
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
- G06F1/3215—Monitoring of peripheral devices
- G06F1/3225—Monitoring of peripheral devices of memory devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
Abstract
The application provides a control method and a control chip of an analog-to-digital converter. The control method comprises the following steps: receiving an event trigger signal, wherein the event trigger signal comprises an external trigger signal or a trigger signal which is not output by the CPU and is inside the control chip; responding the event trigger signal and waking up the analog-digital converter to work. According to the method, the analog-to-digital converter is awakened to work, the whole process does not need participation of a CPU, and complete automatic processing is achieved, so that the power consumption of the CPU is reduced, the working performance of the CPU is improved, and the overall performance of a chip is finally improved.
Description
Technical Field
The present application relates to the field of integrated circuit technologies, and in particular, to a control method and a control chip for an analog-to-digital converter.
Background
With the gradual expansion of the scale of integrated circuits, more and more ips (intelligent property) are integrated on a single chip, and the implemented functions are more complex. The CPU (central Processing unit) is used as a core Processing unit of the IP and is responsible for the operation of the whole chip, so the Processing efficiency of the CPU greatly affects the performance of the chip.
Many chips on the market today have analog-to-digital conversion capability, and an analog-to-digital converter (ADC) is a circuit system that converts an analog signal to a digital signal. The continuous signal in analog form can be converted to a discrete signal in digital form by the ADC. For example: temperature signals, pressure signals, sound signals, etc., need to be converted into digital signals that are easier to store, process and transmit. Today, ADCs are widely used in a variety of electronic devices. Due to the wide application of ADCs, the chip is also particularly important for the control and data processing of the ADC.
At present, the ADC in most chips is directly controlled by a CPU. The starting and closing of the ADC, the processing of data (including reading and writing, transmission and the like) in the ADC sampling conversion process, the processing of interruption after the sampling is finished and the like all need to be directly controlled by the CPU. Although the control mode has clear logic and does not need extra controller overhead, all control and processing are completed by the CPU, so that the power consumption of the CPU is greatly increased, and the working performance of the CPU is severely restricted.
Disclosure of Invention
Therefore, it is necessary to provide a control method and a control chip for an analog-to-digital converter, aiming at the problems that the ADC in the existing chip is directly controlled by the CPU, the power consumption of the CPU is greatly increased, and the working performance of the CPU is severely restricted.
A control method of an analog-to-digital converter is applied to a control chip, the control chip comprises a CPU and the analog-to-digital converter electrically connected with the CPU, and the method comprises the following steps:
receiving an event trigger signal, wherein the event trigger signal comprises an external trigger signal or a trigger signal which is not output by the CPU and is inside the control chip;
responding the event trigger signal and waking up the analog-digital converter to work.
In one embodiment, after the step of responding to the event trigger signal and controlling the operation of the analog-to-digital converter, the method further comprises:
receiving the data converted by the analog-to-digital converter and storing the converted data into a first memory;
and if the data amount stored in the first memory is larger than or equal to a set threshold value, outputting a request signal to a DMA module, wherein the request signal is used for instructing the DMA module to move the data stored in the first memory to a second memory.
In one embodiment, the step of receiving the data converted by the analog-to-digital converter and storing the converted data in the first memory comprises:
receiving the data converted by the analog-to-digital converter and storing the converted data into a register;
and if the number of the data stored in the register reaches a preset average value number, averaging a plurality of data corresponding to the preset average value number to obtain average value data, and storing the average value data to the first memory.
In one embodiment, after the step of receiving the data converted by the analog-to-digital converter and storing the converted data in a register, the method further comprises:
judging whether the analog-to-digital converter is in a power-down mode;
and if the analog-to-digital converter is in a power-down mode, outputting an idle signal to a clock generation device so that the clock generation device controls the analog-to-digital converter to stop working.
In one embodiment, before the step of receiving the event trigger signal, the method further comprises:
and configuring the working mode of the analog-to-digital converter, wherein the working mode of the analog-to-digital converter comprises single-channel single sampling, single-channel set time sampling, single-channel continuous sampling, multi-channel single sampling, multi-channel set time sampling and multi-channel continuous sampling.
In one embodiment, the method further comprises:
and receiving a wake-up instruction output by the CPU, responding to the wake-up instruction and waking up the analog-to-digital converter to work.
A control chip, comprising: the CPU is electrically connected with the analog-to-digital converter through the analog-to-digital converter controller;
the analog-to-digital converter controller is used for receiving an event trigger signal and responding to the event trigger signal to wake up the analog-to-digital converter to work, wherein the event trigger signal comprises an external trigger signal or a trigger signal which is not output by the CPU and is inside the control chip.
In one embodiment, the control chip further includes: the first memory is arranged in the analog-to-digital converter controller, the second memory is electrically connected with the DMA device, and the DMA device is electrically connected with the analog-to-digital converter controller;
the analog-to-digital converter controller is used for receiving the data converted by the analog-to-digital converter and storing the converted data into the first memory, and if the data amount stored in the first memory is larger than or equal to a set threshold value, a request signal is output to the DMA device, and the request signal is used for instructing the DMA module to move the data stored in the first memory to a second memory.
In one embodiment, the analog-to-digital converter controller includes: the data processing device is electrically connected with the DMA device, the register and the first memory respectively;
the data processing device is used for receiving the data converted by the analog-to-digital converter, storing the converted data into the register, averaging a plurality of data corresponding to the preset average number to obtain average data if the number of the data stored in the register reaches the preset average number, and storing the average data into the first memory.
In one embodiment, the control chip further includes: a clock generation device electrically connected to the analog-to-digital converter controller;
the analog-to-digital converter controller is further configured to determine whether the analog-to-digital converter is in a power-down mode, and if the analog-to-digital converter is in the power-down mode, output an idle signal to the clock generation device so that the clock generation device controls the analog-to-digital converter to stop working.
Compared with the prior art, the control method and the control chip of the analog-to-digital converter firstly receive the event trigger signal, wherein the event trigger signal comprises an external trigger signal or a trigger signal which is not output by the CPU and is inside the control chip. Responding the event trigger signal and waking up the analog-digital converter to work. According to the method, the analog-to-digital converter is awakened to work, the whole process does not need participation of a CPU, and complete automatic processing is achieved, so that the power consumption of the CPU is reduced, the working performance of the CPU is improved, and the overall performance of a chip is finally improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the descriptions of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following descriptions are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a flowchart of a control method of an analog-to-digital converter according to an embodiment of the present application;
fig. 2 is a schematic block diagram of a control chip according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of a control chip according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of a control chip according to another embodiment of the present application;
fig. 5 is a block diagram of an analog-to-digital converter controller according to an embodiment of the present disclosure.
Description of reference numerals:
10. a control chip; 100. an analog-to-digital converter controller; 101. an analog-to-digital converter; 110. a register; 120. a data processing device; 200. a first memory; 300. a DMA device; 400. a second memory; 500. a clock generation device.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, embodiments accompanying the present application are described in detail below with reference to the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. This application is capable of embodiments in many different forms than those described herein and those skilled in the art will be able to make similar modifications without departing from the spirit of the application and it is therefore not intended to be limited to the embodiments disclosed below.
The numbering of the components as such, e.g., "first", "second", etc., is used herein for the purpose of describing the objects only, and does not have any sequential or technical meaning. The term "connected" and "coupled" when used in this application, unless otherwise indicated, includes both direct and indirect connections (couplings). In the description of the present application, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations or positional relationships based on those shown in the drawings, and are used only for convenience in describing the present application and for simplicity in description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, are not to be considered as limiting the present application.
In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through intervening media. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
Referring to fig. 1, an embodiment of the present application provides a control method for an analog-to-digital converter, which is applied to a control chip, where the control chip includes a CPU and an analog-to-digital converter electrically connected to the CPU. The method comprises the following steps:
s102: receiving an event trigger signal, wherein the event trigger signal comprises an external trigger signal or a trigger signal which is not output by the CPU in the control chip.
In one embodiment, the event trigger signal may be received by a corresponding controller of the analog-to-digital converter (i.e., an analog-to-digital converter controller). In an embodiment, the event trigger signal may be an interrupt trigger signal inside the control chip, or may be a timing trigger signal inside the control chip. In one embodiment, the event trigger signal may also be an external trigger signal of the control chip. For example, the timing trigger signal may be generated by a timing generator and sent to the analog-to-digital converter controller via a bus. In one embodiment, the interrupt trigger signal may be generated by a front-end working device electrically connected to the analog-to-digital converter controller. For example, when the front-end working device is turned off, the interrupt trigger signal may be automatically generated and sent to the analog-to-digital converter controller.
In one embodiment, the external trigger signal may be provided directly to the analog-to-digital converter controller within the control chip through a device external to the control chip. By adopting the triggering modes, the analog-digital converter can be awakened to work through the analog-digital converter controller, meanwhile, the power consumption of the CPU can be reduced, and the working performance of the CPU is improved. In one embodiment, the interrupt trigger signal, the timing trigger signal, and the external trigger signal each comprise an edge trigger signal (e.g., a rising edge trigger signal). I.e. the analog-to-digital converter controller may be triggered by a rising edge trigger signal. In one embodiment, the event trigger signal may also include other rising edge trigger signals. For example, a pulse signal with a rising edge may be input to the analog-to-digital converter controller, which may also be caused to trigger the analog-to-digital converter to operate. It should be noted that the trigger signal inside the control chip is not output by the CPU because the CPU outputs bit data.
S104: responding the event trigger signal and waking up the analog-digital converter to work.
In one embodiment, the analog-to-digital converter controller may respond to the event trigger signal and wake up the analog-to-digital converter to operate after receiving the event trigger signal. Specifically, after the analog-to-digital converter controller receives the event trigger signal, the analog-to-digital converter can be controlled to perform analog-to-digital conversion according to the event trigger signal, so that the analog-to-digital converter can be awakened.
In one embodiment, the analog-to-digital converter is in a sleep mode before being awakened. I.e. when the analog-to-digital converter is switched off, in a low power consumption operating state. Similarly, the adc controller is in a sleep state until the event trigger signal is not received. When the event trigger signal is input to the analog-to-digital converter controller, the analog-to-digital converter controller starts to work. Namely, the analog-to-digital converter controller wakes up the analog-to-digital converter to work, so that the analog-to-digital converter starts to perform analog-to-digital conversion, quantization and encoding. Therefore, the analog-to-digital converter is awakened without the participation of a CPU, and the analog-to-digital converter is automatically triggered to work through the event trigger signal. Therefore, the CPU is prevented from waking up the analog-to-digital converter to work, so that the power consumption of the CPU is greatly reduced, and the working performance of the CPU is improved.
In this embodiment, the analog-to-digital converter is awakened to work in the above manner, and the whole process does not require the participation of a CPU, so that complete automatic processing is realized, the power consumption of the CPU is reduced, the working performance of the CPU is improved, and finally the overall performance of the chip is improved.
In one embodiment, after the step of responding to the event trigger signal and controlling the operation of the analog-to-digital converter, the method further comprises: and receiving the data converted by the analog-to-digital converter and storing the converted data into a first memory. If the data amount stored in the first memory is larger than or equal to a set threshold value, outputting a request signal to a DMA module, wherein the request signal is used for instructing the DMA module to move the data stored in the first memory to a second memory. And returning to the step of receiving the data converted by the analog-to-digital converter and storing the converted data into the first memory if the data stored in the first memory is smaller than the set threshold.
In one embodiment, the analog-to-digital converter controller may receive data after analog-to-digital conversion by the analog-to-digital converter after triggering the analog-to-digital converter to operate, and store the data in a first memory in the analog-to-digital converter controller. In one embodiment, the first memory may be a memory integrated within the analog-to-digital converter controller. In particular, the memory may be a FIFO memory. After the analog-to-digital converter controller stores the data after analog-to-digital conversion into the first memory, the analog-to-digital converter controller can count the number of the stored data and judge whether the data amount stored in the first memory is larger than or equal to a set threshold value. If the analog-to-digital converter controller determines that the data amount stored in the first memory is greater than or equal to the set threshold, the analog-to-digital converter controller may send the request signal to the DMA module at this time. And the DMA module automatically moves the data stored in the first memory in the analog-to-digital converter controller to a second memory for storage after receiving the request signal.
In an embodiment, after the analog-to-digital converter controller stores the data after the analog-to-digital conversion in the first memory, a corresponding trigger mechanism may also be configured in the first memory by the analog-to-digital converter controller according to the set threshold. For example, when the amount of data stored in the first memory reaches the trigger mechanism corresponding to the set threshold, the first memory may output a signal to the adc controller, and the adc controller may determine that the amount of data stored in the first memory has reached the set threshold through the signal. That is, the adc controller may confirm that the amount of data stored in the first memory is greater than or equal to the set threshold through the signal, and at this time, the adc controller may send the request signal to the DMA module. And the DMA module automatically moves the data stored in the first memory in the analog-to-digital converter controller to a second memory for storage after receiving the request signal.
Thereby, the DMA module can move the data from the first memory to the second memory with larger capacity for storage. By adopting the mode, the processing efficiency can be effectively improved. Meanwhile, the CPU does not need to monitor the analog-to-digital converter in real time and read the first memory after the data conversion of the analog-to-digital converter is finished each time. The CPU can obtain the conversion data of the analog-to-digital converter from the second memory in an idle period to perform data processing, so that the power consumption of the CPU can be further reduced, and the working performance of the CPU is improved.
In one embodiment, if the amount of data stored in the first memory is less than the set threshold, the analog-to-digital converter controller may continue to receive the data converted by the analog-to-digital converter and store the converted data in the first memory. The analog-to-digital converter controller requests the DMA module to move the data stored in the first memory to the second memory for storage only when the amount of the data stored in the first memory is greater than or equal to the set threshold. In one embodiment, the set threshold may be set according to actual requirements, for example, the set threshold may be set to 10. In one embodiment, the second memory may be an SRAM memory.
In one embodiment, the step of receiving the data converted by the analog-to-digital converter and storing the converted data in the first memory comprises: and receiving the data converted by the analog-to-digital converter and storing the converted data to a register. And if the number of the data stored in the register reaches a preset average value number, averaging a plurality of data corresponding to the preset average value number to obtain average value data, and storing the average value data to the first memory. And returning to receive the data converted by the analog-to-digital converter and storing the converted data into a register if the number of the data does not reach the preset average value number.
In one embodiment, when the analog-to-digital converter continuously performs data conversion, the analog-to-digital converter controller may first store the received data converted by the analog-to-digital converter to the register. In particular, the register may be a register integrated in the analog-to-digital converter controller. After the analog-to-digital converter controller stores the data after analog-to-digital conversion into the register, the number of the data stored in the register can be counted by the analog-to-digital converter controller, and whether the number of the data reaches the preset average value number or not is determined. And if the number of the data stored in the register reaches the preset average value number, averaging a plurality of data corresponding to the preset average value number through the analog-to-digital converter controller to obtain average value data. And simultaneously storing the mean value data into the first memory, wherein the number of the data stored in the first memory is added up by one. That is, the first memory stores the mean value data once, and the number of the data stored in the first memory is cumulatively increased by one.
In an embodiment, after the adc controller stores the data after the adc into the register, a corresponding trigger mechanism may be configured in the register according to the preset average number by the adc controller. For example, when the number of the data stored in the first memory reaches the trigger mechanism corresponding to the preset average number, the register may output a signal to the adc controller, and the adc controller may determine that the number of the data stored in the register has reached the preset average number through the signal. That is, the analog-to-digital converter controller can confirm that the number of the data stored in the register has reached the preset average number through the signal, and at this time, the analog-to-digital converter controller can average a plurality of data corresponding to the preset average number and obtain average data. And simultaneously storing the mean value data into the first memory, wherein the number of the data stored in the first memory is added up by one.
And if the number of the data stored in the register does not reach the preset average value number, the analog-to-digital converter controller continuously stores the data converted by the analog-to-digital converter into the register. And the analog-to-digital converter controller can calculate the average value of a plurality of data corresponding to the preset average value quantity only if the number of the data stored in the register reaches the preset average value quantity. In one embodiment, the preset average number may be set according to actual requirements, for example, the preset average number may be set to 3.
In this embodiment, by using the above manner of averaging a plurality of data converted by the analog-to-digital converter, the sampling value deviation caused by voltage fluctuation and other factors can be effectively reduced, so that the stability of the data converted by the analog-to-digital converter is improved, and the subsequent data processing is more accurate.
In one embodiment, after the step of receiving the data converted by the analog-to-digital converter and storing the converted data in a register, the method further comprises: and judging whether the analog-to-digital converter is in a power-down mode or not. And if the analog-to-digital converter is in a power-down mode, outputting an idle signal to a clock generation device so that the clock generation device controls the analog-to-digital converter to stop working.
In one embodiment, the analog-to-digital converter controller determines whether the analog-to-digital converter is in the power-down mode while receiving output data of the analog-to-digital converter. Specifically, when the analog-to-digital converter controller does not receive the output data of the analog-to-digital converter, the analog-to-digital converter controller may determine that the analog-to-digital converter is in the power-down mode at this time. When the analog-to-digital converter controller determines that the analog-to-digital converter is in the power-down mode, the analog-to-digital converter controller can output an idle signal to a clock generation device. And the clock generation device is enabled to turn off the working clock of the analog-to-digital converter, namely the clock generation device controls the analog-to-digital converter to stop working, so that the power consumption of the whole chip is reduced.
In one embodiment, before the step of receiving the event trigger signal, the method further comprises: and configuring the working mode of the analog-to-digital converter. The working modes of the analog-to-digital converter comprise single-channel single-time sampling, single-channel set time sampling, single-channel continuous sampling, multi-channel single-time sampling, multi-channel set time sampling and multi-channel continuous sampling.
In one embodiment, the analog-to-digital converter may select an analog-to-digital converter with a resolution of 12 bits and 10 sampling channels. To increase the sampling flexibility of the analog-to-digital converter, the mode of operation of the analog-to-digital converter may be configured by the analog-to-digital converter controller. For example, different operation modes of the analog-to-digital converter can be selected, and specific operation modes of the analog-to-digital converter include single-channel single sampling, single-channel set-number sampling, single-channel continuous sampling, multi-channel single sampling, multi-channel set-number sampling and multi-channel continuous sampling.
The set times are sampling times of channels of the analog-to-digital converter configured by the analog-to-digital converter controller, and when the sampling times of the channels reach, the channels corresponding to the analog-to-digital converter stop sampling. Similarly, the number of channels for multi-channel sampling can be configured, and any number of channels from a single channel to a full channel of the analog-to-digital converter can be selected for sampling. Namely, the sampling times and the sampling channels of the analog-to-digital converter can be configured according to application requirements so as to adapt to different application occasions, thereby greatly increasing the application flexibility of the analog-to-digital converter.
In one embodiment, the method further comprises: and receiving a wake-up instruction output by the CPU, responding to the wake-up instruction and waking up the analog-to-digital converter to work. Namely, the analog-to-digital converter can also be woken up through a wake-up instruction output by the CPU.
Referring to fig. 2, another embodiment of the present application provides a control chip 10. The control chip 10 includes: a CPU, an analog-to-digital converter controller 100, and an analog-to-digital converter 101. The CPU is electrically connected to the analog-to-digital converter 101 through the analog-to-digital converter controller 100. The adc controller 100 is configured to receive an event trigger signal, and wake up the adc 101 to operate in response to the event trigger signal. The event trigger signal comprises an external trigger signal or a trigger signal which is not output by the CPU and is inside the control chip. In an embodiment, the adc controller 100 may wake up the adc 101 to work by using the control method of the adc described in the above embodiment, which is not described herein again.
Referring to fig. 3, in an embodiment, the control chip 10 further includes: a first memory 200, a DMA device 300 and a second memory 400, the first memory 200 being disposed within the analog-to-digital converter controller 100. The second memory 400 is electrically connected to the DMA device 300. The DMA device 300 is electrically connected to the analog-to-digital converter controller 100. The analog-to-digital converter controller 100 is configured to receive the data converted by the analog-to-digital converter 101 and store the converted data in the first memory 200. If the amount of data stored in the first memory 200 is greater than or equal to a predetermined threshold, the adc controller 100 outputs a request signal to the DMA device 300, where the request signal is used to instruct the DMA module 300 to move the data stored in the first memory 200 to the second memory 400.
In an embodiment, the manner described in the above embodiment may be adopted to determine whether the data amount stored in the first memory 200 is greater than or equal to the set threshold, and details are not repeated here. In one implementation, the first memory 200 may be integrated within the analog-to-digital converter controller 100. In one implementation, the DMA device 300 may be communicatively coupled to the analog-to-digital converter controller 100 via a bus. Specifically, the request signal output by the adc controller 100 may be transmitted to the DMA device 300 through a bus. Then, the DMA device 300 may move the data stored in the first memory 200 in the adc controller 100 to the second memory 400 via the bus, and the specific moving manner may refer to the foregoing embodiments and is not described herein again.
Referring to fig. 4, in one embodiment, the adc controller 100 includes: a register 110 and a data processing device 120. The data processing device 120 is electrically connected to the register 110, the first memory 200, and the DMA device 300, respectively. The data processing device 120 is configured to receive the data converted by the analog-to-digital converter 101 and store the converted data in the register 110. If the number of the data stored in the register 110 reaches a preset average number, averaging a plurality of the data corresponding to the preset average number to obtain average data, and storing the average data in the first memory 200.
In an embodiment, the manner described in the above embodiment may be adopted to determine whether the number of the data stored in the register 110 reaches the preset average number, and details are not described here. In one embodiment, the register 110 may be a register integrated within the analog-to-digital converter controller 100. In one embodiment, the first memory 200 may be a memory integrated within the analog-to-digital converter controller 100. In one embodiment, the data processing device 120 may be an MCU (micro processing unit) integrated within the analog-to-digital converter controller 100. In one embodiment, when the analog-to-digital converter 101 continuously performs data conversion, the data processing device 120 may store the received data converted by the analog-to-digital converter 101 to the register 110. After the data processing device 120 stores the data after the analog-to-digital conversion to the register 110, if the number of the data stored in the register 110 reaches the preset average number, the data processing device 120 may average a plurality of data corresponding to the preset average number and obtain average data. At the same time, the data processing device 120 stores the mean data into the first memory 200, and at this time, the first memory 200 stores the number of the data plus one. That is, the first memory 200 stores the mean data once, the first memory 200 stores the number of data cumulatively plus one.
If the number of the data stored in the register 110 does not reach the preset average number, the data processing device 120 continues to store the data converted by the analog-to-digital converter 101 in the register 110. Only if the number of data stored in the register 110 reaches the preset average number, the data processing device 120 may average a plurality of data corresponding to the preset average number. In one embodiment, the preset average number may be set according to actual requirements, for example, the preset average number may be set to 3.
In this embodiment, the analog-to-digital converter controller 100 may effectively reduce a sampling value deviation caused by voltage fluctuation and other factors by using the above manner of averaging a plurality of data converted by the analog-to-digital converter 101, so as to improve stability of data conversion by the analog-to-digital converter 101, so as to enable subsequent data processing to be more accurate.
Referring to fig. 5, in an embodiment, the control chip 10 further includes: the clock generation device 500. The clock generation device 500 is electrically connected to the analog-to-digital converter controller 100. The adc controller 100 is further configured to determine whether the adc 101 is in a power-down mode. If the analog-to-digital converter 101 is in the power-down mode, an idle signal is output to the clock generation device 500, so that the clock generation device 500 controls the analog-to-digital converter 101 to stop working.
In one implementation, the clock generation device 500 may be communicatively coupled to the analog-to-digital converter controller 100 via a bus. In an embodiment, the manner in which the adc controller 100 determines whether the adc 101 is in the power-down mode may refer to the manner described in the above embodiments, and details are not described here.
In summary, the present application first receives an event trigger signal, where the event trigger signal includes an interrupt trigger signal and/or a timing trigger signal and/or an external trigger signal, and the CPU does not output the event trigger signal. Responding the event trigger signal and waking up the analog-digital converter to work. According to the method, the analog-to-digital converter 101 is awakened to work, the whole process does not need participation of a CPU, and complete automatic processing is achieved, so that the power consumption of the CPU is reduced, the working performance of the CPU is improved, and the overall performance of a chip is finally improved.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A control method of an analog-to-digital converter is applied to a control chip, the control chip comprises a CPU and the analog-to-digital converter electrically connected with the CPU, and the method is characterized by comprising the following steps:
receiving an event trigger signal, wherein the event trigger signal comprises an external trigger signal or a trigger signal which is not output by the CPU and is inside the control chip;
responding the event trigger signal and waking up the analog-digital converter to work.
2. The method of controlling an analog-to-digital converter as claimed in claim 1, wherein after said step of controlling the operation of the analog-to-digital converter in response to said event trigger signal, said method further comprises:
receiving the data converted by the analog-to-digital converter and storing the converted data into a first memory;
and if the data amount stored in the first memory is larger than or equal to a set threshold value, outputting a request signal to a DMA module, wherein the request signal is used for instructing the DMA module to move the data stored in the first memory to a second memory.
3. The method of controlling an analog-to-digital converter according to claim 2, wherein the step of receiving the data converted by the analog-to-digital converter and storing the converted data in the first memory comprises:
receiving the data converted by the analog-to-digital converter and storing the converted data into a register;
and if the number of the data stored in the register reaches a preset average value number, averaging a plurality of data corresponding to the preset average value number to obtain average value data, and storing the average value data to the first memory.
4. The method of controlling an analog-to-digital converter according to claim 2, wherein after the step of receiving the data converted by the analog-to-digital converter and storing the converted data in a register, the method further comprises:
judging whether the analog-to-digital converter is in a power-down mode;
and if the analog-to-digital converter is in a power-down mode, outputting an idle signal to a clock generation device so that the clock generation device controls the analog-to-digital converter to stop working.
5. The method of controlling an analog-to-digital converter as claimed in claim 1, wherein said step of receiving an event trigger signal is preceded by the method further comprising:
and configuring the working mode of the analog-to-digital converter, wherein the working mode of the analog-to-digital converter comprises single-channel single sampling, single-channel set time sampling, single-channel continuous sampling, multi-channel single sampling, multi-channel set time sampling and multi-channel continuous sampling.
6. The method of controlling an analog-to-digital converter according to claim 1, the method further comprising:
and receiving a wake-up instruction output by the CPU, responding to the wake-up instruction and waking up the analog-to-digital converter to work.
7. A control chip, comprising: the CPU is electrically connected with the analog-to-digital converter through the analog-to-digital converter controller;
the analog-to-digital converter controller is used for receiving an event trigger signal and responding to the event trigger signal to wake up the analog-to-digital converter to work, wherein the event trigger signal comprises an external trigger signal or a trigger signal which is not output by the CPU and is inside the control chip.
8. The control chip of claim 7, further comprising: the first memory is arranged in the analog-to-digital converter controller, the second memory is electrically connected with the DMA device, and the DMA device is electrically connected with the analog-to-digital converter controller;
the analog-to-digital converter controller is used for receiving the data converted by the analog-to-digital converter and storing the converted data into the first memory, and if the data amount stored in the first memory is larger than or equal to a set threshold value, a request signal is output to the DMA device, and the request signal is used for instructing the DMA module to move the data stored in the first memory to a second memory.
9. The control chip of claim 8, wherein the analog-to-digital converter controller comprises: the data processing device is electrically connected with the DMA device, the register and the first memory respectively;
the data processing device is used for receiving the data converted by the analog-to-digital converter, storing the converted data into the register, averaging a plurality of data corresponding to the preset average number to obtain average data if the number of the data stored in the register reaches the preset average number, and storing the average data into the first memory.
10. The control chip of claim 7, further comprising: a clock generation device electrically connected to the analog-to-digital converter controller;
the analog-to-digital converter controller is further configured to determine whether the analog-to-digital converter is in a power-down mode, and if the analog-to-digital converter is in the power-down mode, output an idle signal to the clock generation device so that the clock generation device controls the analog-to-digital converter to stop working.
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| CN115079623A (en) * | 2022-08-23 | 2022-09-20 | 深圳市航顺芯片技术研发有限公司 | Control method and device of microcontroller chip and storage medium |
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| CN108897264A (en) * | 2018-09-27 | 2018-11-27 | 浙江大学 | Analog-digital converter control device applied widely for general-purpose system chip |
| CN109343992A (en) * | 2018-09-27 | 2019-02-15 | 浙江大学 | The flexible analog-digital converter control method matched applied to general main control chip |
| CN109375532A (en) * | 2018-09-10 | 2019-02-22 | 中国科学院上海应用物理研究所 | A kind of signal acquisition process device and its more data volume read methods |
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| CN109375532A (en) * | 2018-09-10 | 2019-02-22 | 中国科学院上海应用物理研究所 | A kind of signal acquisition process device and its more data volume read methods |
| CN108897264A (en) * | 2018-09-27 | 2018-11-27 | 浙江大学 | Analog-digital converter control device applied widely for general-purpose system chip |
| CN109343992A (en) * | 2018-09-27 | 2019-02-15 | 浙江大学 | The flexible analog-digital converter control method matched applied to general main control chip |
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| WO2022104990A1 (en) * | 2020-11-20 | 2022-05-27 | 清华大学 | Trigger device and brain-like computing system |
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Address after: Room 86, room 406, No.1, Yichuang street, Zhongxin Guangzhou Knowledge City, Huangpu District, Guangzhou City, Guangdong Province Applicant after: Southern Power Grid Digital Grid Research Institute Co.,Ltd. Applicant after: ELECTRIC POWER Research Institute CHINA SOUTHERN POWER GRID Applicant after: ZHEJIANG University Address before: 511458 Room 1301, Chengtou Building, 106 Fengze East Road, Nansha District, Guangzhou City, Guangdong Province (self-compiled 1301-12159) Applicant before: Southern Power Grid Digital Grid Research Institute Co.,Ltd. Applicant before: ELECTRIC POWER Research Institute CHINA SOUTHERN POWER GRID Applicant before: ZHEJIANG University |
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Application publication date: 20201023 |