CN100524170C - Controller for controlling memory to low power consumption mode and control method therefor - Google Patents
Controller for controlling memory to low power consumption mode and control method therefor Download PDFInfo
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Abstract
The invention provides a controller for making storage device enter into low power consumption mode and a control method. The invention is characterized in that the status controller can automatically generate low power consumption mode control signal after CPU completes read/write on storage device with low power consumption, and control the storage device enter into low power consumption mode; when read/write operation finished, the status controller sends reset signal to interrupt generator which start to time according to the reset signal and sends out an interrupt signal to the status controller when it gets to pre-set time value, and then the status controller generates a low power consumption control signal according to the interrupt signal and send it to the storage device.
Description
Technical Field
The present invention relates to low power consumption technologies, and in particular, to a controller and a control method for controlling a memory to enter a low power consumption mode.
Background
Due to the limitation of battery power supply, mobile devices such as mobile phones and the like have a memory, such as: the power consumption requirements of Synchronous Dynamic Random Access Memory (SDRAM) are very high. SDRAM is an important memory device in mobile devices, and may provide special power saving modes or low power modes, such as power off (POWERDOWN) mode, self refresh (Selfrefresh) mode, etc.
Generally, a memory having a low power consumption function such as an SDRAM provides only a low power consumption mode, and a special software is required to control the memory to enter the low power consumption mode. The basic idea of using software to control the memory to enter a low power mode is: detecting whether the mobile equipment needs to use the memory in real time, and controlling the memory to enter a normal working mode if the mobile equipment needs to use the memory; otherwise, the memory is controlled to enter a low power consumption mode. The use of memory as described herein means that the mobile device requires memory to participate in the process of implementing a certain function. Such as: video data of the MP4 is stored in SDRAM, which will be inevitably used when the mobile device implements the MP4 function, i.e. SDRAM participation is required. At the moment, when the software detects that the mobile equipment starts the MP4 video function, an instruction for entering a normal working mode is sent to the SDRAM; when the software detects that the mobile device shuts down the MP4 video function, it sends a command to the SDRAM to enter a low power mode. Certainly, in practical applications, software cannot directly send a command to the SDRAM, and generally, the CPU of the mobile device executes a command for controlling the SDRAM to enter a normal operating mode or a low power consumption mode, and the CPU sends a control command to the SDRAM.
In practical application, when the mobile device uses the SDRAM, that is, when the software controls the SDRAM to enter a normal operating mode, the CPU does not always perform read/write operations on the SDRAM, and a certain idle time generally exists between two consecutive read/write operations. Such as: during the process of playing MP4 video program, CPU reads a batch of data from SDRAM and stores the data in buffer. And then, the CPU directly reads the data from the buffer memory for playing, and reads the next batch of data from the SDRAM after the data in the buffer memory is played, and so on.
That is, in the prior art, between two consecutive times of reading/writing data from/to the memory by the CPU, the memory is actually in an idle state, but since it is in an operation mode by software control, power consumption is still relatively high.
It follows that the prior art has not been able to reduce the power consumption of memory idle times when the mobile device needs to use the memory.
Disclosure of Invention
In view of the above, the main objective of the present invention is to provide a controller for controlling a memory to enter a low power consumption mode, which can make the memory enter the low power consumption mode in the process of using the memory, so as to reduce power consumption when the memory is idle.
Aiming at the device provided by the invention, the invention also provides a method for controlling the memory to enter the low power consumption mode, so that the memory can enter the low power consumption mode in the process of using the memory, and the power consumption of the memory in idle state is reduced.
Aiming at the first invention purpose, the technical scheme provided by the invention is as follows:
a controller for controlling a memory into a low power consumption mode, the controller comprising at least:
the interrupt generator is used for receiving a reset signal from the state controller, starting timing and outputting an interrupt signal to the state controller when a preset time value is reached;
the state controller is used for outputting a reset signal to the interrupt generator when the read-write operation of the memory is finished, receiving the interrupt signal from the interrupt generator, determining the number of a low power consumption mode to be entered by the memory, generating a low power consumption mode control signal according to the number of the low power consumption mode and outputting the low power consumption mode control signal to the memory;
wherein the state controller includes:
the core controller is used for outputting a reset signal to the interrupt generator, receiving the interrupt signal input by the interrupt generator and outputting the serial number of the low power consumption mode to be entered by the memory to the control signal generator;
and the control signal generator is used for generating a low-power-consumption mode control signal according to the mode number input by the core controller and outputting the low-power-consumption mode control signal to the memory.
Preferably, the interrupt generator includes:
the timer is used for receiving a reset signal from the state controller, starting timing and outputting an interrupt signal to the state controller when a preset time value provided by the timer configuration register is reached;
and the timer configuration register is used for saving a preset time value which is solidified in the timer or written by the CPU in advance and providing the preset time value for the timer.
Preferably, the timer is a timer comprising one or more comparators;
the timer configuration register is a timer configuration register that stores one or more preset time values.
Preferably, the state controller further comprises:
the memory state register is used for recording the mode number of the current low-power-consumption mode of the memory;
the core controller is further used for reading the mode number of the current low-power-consumption mode of the memory from the memory state register, taking the next number of the current low-power-consumption mode as the number of the low-power-consumption mode to be entered, and outputting the number of the low-power-consumption mode to be entered to the memory state register.
Preferably, the memory is a synchronous dynamic random access memory SDRAM.
Aiming at the second invention purpose, the technical scheme provided by the invention is as follows:
a method for controlling a memory to enter a low power consumption mode is characterized in that a preset time value is set, and when the read-write operation of the memory is finished, the method further comprises the following steps:
A. the state controller sends a reset signal to the interrupt generator;
B. the interrupt generator starts timing according to the reset signal and sends an interrupt signal to the state controller when a preset time value is reached;
C. the state controller determines the number of the low power consumption mode to be entered by the memory according to the interrupt signal, and comprises the following steps: directly taking the mode number stored in a memory state register in the state controller in advance as the number of the low power consumption mode to be entered by the memory, or firstly inquiring the mode number of the current low power consumption mode of the memory recorded in the memory state register in the state controller and then taking the next number of the current mode number as the number of the low power consumption mode to be entered by the memory;
and generating a low power consumption mode control signal according to the number of the low power consumption mode, and sending the low power consumption mode control signal to a memory.
Preferably, the preset time value is one or more than one preset time value.
Preferably, the method for setting the preset time value includes: the preset time value is either fixed in the interrupt generator or written by the CPU into the interrupt generator.
Preferably, the memory is an SDRAM.
In summary, the controller and the control method for controlling the memory to enter the low power consumption mode provided by the invention have the following advantages:
(1) because the state controller can send the low-power mode control signal to the memory after the CPU finishes the read/write operation of the memory, namely, the memory is controlled to enter the low-power mode, even if the memory is used by the mobile device, the state controller can enter the low-power mode as long as the idle time between two continuous read/write operations reaches a certain limit, and the aim of further saving the battery energy of the mobile device is achieved.
(2) The invention can set a plurality of preset time values in the interrupt generator, and the state controller controls the memory to enter different low power consumption modes according to different idle times of the memory. When the idle time is short, the memory enters a low power consumption mode with higher power consumption and simple process, and the longer the idle time is, the memory enters a low power consumption mode with lower power consumption and complex process. Therefore, if the memory needs to be read/written after a short idle time, the memory can quickly exit from the low power consumption mode and enter into a normal working mode; if the idle time of the memory is long, the low-power-consumption mode with lower power consumption can be entered, and the purpose of reducing the power consumption to the maximum extent is achieved.
(3) The preset time value in the interrupt generator can be not only solidified in advance, but also written by the CPU, and the condition for controlling the memory to enter the low power consumption mode can be flexibly set.
Drawings
FIG. 1 is a schematic diagram of a system architecture in which a controller controls a memory to enter a low power mode;
FIG. 2 is a schematic diagram of a basic structure of a controller for controlling a memory to enter a low power consumption mode according to the present invention;
FIG. 3 is a schematic diagram of a basic structure of a first embodiment of the apparatus;
FIG. 4 is a flow chart of an aspect of the present invention;
fig. 5 is a flow chart of an embodiment of an application of the solution of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
In the invention, the low-power-consumption mode controller generates a low-power-consumption mode control signal after the CPU finishes the read/write operation of the memory, and controls the memory to enter a corresponding low-power-consumption mode.
Fig. 1 shows a schematic diagram of a system structure in which a low power mode controller according to the present invention is located. As shown in fig. 1, the system includes a CPU, a low power mode controller, and a memory. In practical application, when the CPU is going to read/write the memory, it will send a read/write control signal to the memory, perform a read/write operation on the memory, and read or write data from or into the memory. Since the number of bytes read/written is specified in the read/write control signal, the time to read/write a byte is generally fixed, which is roughly a few clock cycles. Therefore, when the CPU performs read/write operation on the memory, the low power consumption mode controller can determine the accurate time when the read/write operation is finished, so that the memory can be controlled to enter the low power consumption mode when the read/write operation is finished.
The memory described herein is a memory having a power saving function, i.e., a function capable of providing low power consumption, such as SDRAM, mobile RAM, etc.
The basic structure of the low power consumption mode controller is shown in fig. 2. In the present invention, the low power mode controller includes at least an interrupt generator 201 and a state controller 202.
The interrupt generator 201 is configured to receive a reset signal from the state controller 202, start timing, and output an interrupt signal to the state controller 202 when a preset time value is reached.
And a state controller 202 for outputting a reset signal to the interrupt generator 201 when the memory read/write operation is finished, receiving the interrupt signal from the interrupt generator 201, generating a low power consumption mode control signal, and outputting the low power consumption mode control signal to the memory.
When the memory read/write operation ends, the state controller 202 outputs a reset signal to the interrupt generator 201; the interrupt generator 201 starts timing after receiving the reset signal from the state controller 202, and outputs an interrupt signal to the state controller 202 when reaching a preset time value; when receiving the interrupt signal from the interrupt generator 201, the state controller 202 generates a low power consumption mode control signal and outputs the signal to the memory. When the state controller 202 sends the low power mode control signal to the memory, the memory may enter a corresponding low power mode according to the low power mode control signal.
In practical applications, a memory with low power consumption may provide one or more low power consumption modes. If the memory can provide more than one low power mode, the state controller 202 will generate a control signal instructing the memory to enter a certain low power mode. The low power mode control signal is associated with a specific memory, as long as the memory having the low power function can recognize the low power mode control signal sent by the state controller 202.
Such as: if the SDRAM is controlled to enter the low power mode, the low power mode control signal sent by the state controller 202 to the SDRAM also supports a specific standard proposed by a manufacturer of the SDRAM used, etc., in addition to complying with the JEDEC standard of the electronic component industries. How the SDRAM enters the low power mode belongs to the prior art, and the present invention is not described in detail.
Fig. 3 shows a basic structural diagram of an embodiment of the apparatus of the present invention. In this embodiment, the low power mode controller is to control the SDRAM to enter the low power mode. As shown in fig. 3, the interrupt generator 201 includes a timer configuration register 301 and a timer 302, and the status controller 202 includes a core controller 303, a control signal generator 304, and an SDRAM status register 305. Wherein,
a timer configuration register 301 for holding a preset time value written by the CPU and supplying the preset time value to a timer 302.
A timer 302 for receiving a reset signal from the core controller 303 and starting timing, and outputting an interrupt signal to the core controller 303 when a preset time value provided by the timer configuration register 301 is reached.
A core controller 303 for outputting a reset signal to the timer 302; receiving an interrupt signal input by the timer 302, reading a mode number of a current low power consumption mode of the SDRAM in the SDRAM status register 305, determining a mode number of the SDRAM which is to enter the low power consumption mode next time, outputting the mode number of the SDRAM which is to enter the low power consumption mode next time to the control signal generator 304, and recording the mode number of the SDRAM which is to enter the low power consumption mode next time as a current state of the SDRAM in the SDRAM status register 305.
And a control signal generator 304 for generating a low power consumption mode control signal according to the mode number input from the core controller 303 and outputting it to the SDRAM.
Here, the low power mode control signals are one-to-one corresponding to the pattern numbers, and the correspondence between the pattern numbers and the low power mode control signals to be generated may be stored in advance in the control signal generator 304. When the control signal generator 304 receives the mode number input by the core controller 303, the corresponding low power consumption mode control signal can be directly generated according to the corresponding relationship.
And an SDRAM status register 305 for recording the mode number of the current low power mode of the SDRAM.
When the SDRAM read-write operation is finished, the core controller 303 outputs a reset signal to the timer 302; the timer 302 starts timing, and outputs an interrupt signal to the core controller 303 when a preset time value is reached; the core controller 303 reads the mode number of the current low power consumption mode of the SDRAM in the SDRAM status register 305, determines the mode number of the SDRAM which is to enter the low power consumption mode next time, outputs the mode number of the SDRAM which is to enter the low power consumption mode next time to the control signal generator 304, and records the mode number of the SDRAM which is to enter the low power consumption mode next time as the current state of the SDRAM in the SDRAM status register 305; the control signal generator 304 generates a low power consumption mode control signal according to the mode number and outputs the same to the SDRAM.
In practical applications, the interrupt generator 201 may have the timer configuration register 301 or may not have the timer configuration register 301. If the timer configuration register 301 is not present, the timer 302 may represent the predetermined time value by means of ground and power. Such as: the power-connected bit represents a "1" and the ground bit represents a "0". If the preset time value is 5 and is represented by 101 in binary, the 2 nd bit and the 0 th bit of the input end of the timer can be connected with the power supply, and the 1 st bit can be connected with the ground. At this point, the timer 302 itself may act as an interrupt generator.
If there is the timer configuration register 301, the preset time value may be fixed in the timer configuration register 301 in advance, and the preset time value is not changed during the operation of the controller, or the preset time value may be written by the CPU according to the actual situation, and the timer 302 operates according to the preset time value written by the CPU. Then, the CPU may write a new preset time value into the timer configuration register 301 according to the actual situation, and the timer 302 operates according to the new preset time value.
In practical applications, the SDRAM may provide one or more low power modes. If the SDRAM provides a low power mode, then only one comparator is present in timer 302, only one preset time value is present in timer configuration register 301, and SDRAM status register 305 may be absent. That is, after the timer 302 receives the reset signal of the core controller 303, the timer 302 starts to count time, and when the comparator determines that the current timing value is equal to the preset time value, the timer 302 sends an interrupt signal to the core controller 303; the core controller 303 directly outputs a mode number, which is stored in advance in the SDRAM itself and is to be in a low power consumption mode, to the control signal generator 304; the control signal generator 304 generates a low power consumption mode control signal according to the mode number and outputs the generated low power consumption mode control signal to the SDRAM. Here, since the SDRAM provides only one low power mode, the core controller 303 may transmit a fixed certain number to the control signal generator 304, and the control signal generator 304 also generates only one low power mode control signal. Of course, what number the core controller 303 uses to indicate the low power consumption mode may be determined at the discretion of the user applying the present invention as long as the control signal generator 304 can recognize it.
If the SDRAM can provide more than one low power consumption mode, the timer 302 comprises more than one comparator, the timer configuration register 301 has more than one preset time value, and the SDRAM status register 305 for recording the current status of the SDRAM is required. Here, there is a one-to-one correspondence between the preset time value, the comparator in the timer 302, and the low power consumption mode. Taking the example that the SDRAM can provide three low power consumption modes: the timer 302 includes three comparators, and the timer configuration register 301 has three preset time values Ta, Tb and Tc, and Ta < Tb < Tc. Assuming that a corresponding relation exists among a preset time value Ta, the comparator 1 and the first low power consumption mode; a corresponding relation exists among the preset time value Tb, the comparator 2 and the low power consumption mode II; there is a correspondence between the preset time value Tc, the comparator 3, and the low power consumption mode three. When the timer 302 receives the reset signal of the core controller 303, the timer 302 starts counting time, in the process of counting time, Ta is provided to the comparator 1 for comparison, Tb is provided to the comparator 2 for comparison, and Tc is provided to the comparator 3 for comparison. When the comparator 1 determines that the current timing value is equal to Ta, the timer 302 sends an interrupt signal to the core controller 303, and the core controller 303 controls the SDRAM to enter the first low power mode. After that, the timer 302 still keeps counting time, when the comparator 2 determines that the current timing value is equal to Tb, the timer 302 sends an interrupt signal to the core controller 303, and the core controller 303 controls the SDRAM to enter the low power consumption mode two, and sequentially pushes the class.
By applying the scheme of the embodiment, the SDRAM can be controlled to enter different low power consumption modes. In practical application, other memories with low power consumption functions, such as a mobile RAM, can also be controlled to enter a low power consumption mode, so that the aim of further saving the battery energy of the mobile device is fulfilled. Of course, at this time, the status controller 202 does not include the SDRAM status register 305, but instead registers the status of the memory 305 in which the status of other memory having a low power consumption function is recorded.
Aiming at the device provided by the invention, the invention also provides a control method for controlling the memory to enter the low power consumption mode.
The basic idea of the invention is: and the state controller sends a low-power-consumption mode control signal to the memory after the read/write operation of the memory is finished, and controls the memory to enter a low-power-consumption mode.
Figure 4 shows a flow chart of the present invention. In the invention, a time value is preset in an interrupt generator, and when the CPU finishes the read-write operation of the memory, the method for controlling the memory to enter the low power consumption mode comprises the following steps:
step 401: the state controller outputs a reset signal to the interrupt generator;
step 402: the interrupt generator starts timing after receiving the reset signal and outputs an interrupt signal to the state controller when reaching a preset time value;
step 403: and the state controller generates a low power consumption mode control signal according to the interrupt signal and sends the low power consumption mode control signal to the memory.
The memory of the invention is a memory with low power consumption function, such as: SDRAM, etc.
In practical application, the memory with low power consumption function may provide one or more low power consumption modes, and in the present invention, the state controller generates control signals corresponding to different low power consumption modes according to the interrupt signal, and the memory may enter different low power consumption modes according to the different low power consumption mode control signals. The form of the low power mode control signal is related to a specific memory, as long as the memory having the low power function can recognize the low power mode control signal.
Such as: the low power mode control signal sent to the SDRAM complies with the standards of the SDRAM vendor used in addition to the JEDEC standard of the electronic component industries. How to enter the low power consumption mode of the memory such as the SDRAM belongs to the prior art, and the invention is not described in detail.
In practical application, the number and the size of the preset time values can be determined by a user applying the scheme of the invention. Generally, the number of the preset time values is equal to the number of the memory providing the low power consumption mode. Such as: the memory provides three low power consumption modes, and three preset time values are required to be set, and each preset time value corresponds to one low power consumption mode. The size of the preset time value can be determined according to practical conditions such as two adjacent read/write operation time intervals T of the CPU to the memory. Generally, at least one of the predetermined time values should be less than the time interval between two adjacent read/write operations of the memory. Of course, if the time interval between two adjacent read/write operations of the memory is relatively long, more than one preset time value can be set to be smaller than the time interval between two adjacent read/write operations of the memory.
Figure 5 shows a flow chart of an embodiment of the method of the present invention. In this embodiment, the low power mode controller sends a low power mode control signal to the SDRAM, that is, controls the SDRAM to enter different low power modes. The SDRAM can provide three low power consumption modes, namely a mode one, a mode two and a mode three; the CPU writes three preset time values, Ta, Tb, and Tc, respectively, in the interrupt generator in advance, and Ta < Tb < Tc. In this embodiment, Ta corresponds to mode one, Tb corresponds to mode two, and Tc corresponds to mode three. That is, if the timing value reaches Ta, the state control will control the SDRAM to enter the first low power consumption mode; if the timing value reaches Tb, the state control controls SDRAM to enter a second low power consumption mode; if the timing value reaches Tc, the state control will control the SDRAM to enter the third low power mode.
In addition, in the embodiment, the low power consumption mode of the SDRAM is denoted by a numeral, that is: the normal operation mode is denoted by 000, the mode one is denoted by 001, the mode two is denoted by 010, and the mode three is denoted by 011. When the CPU performs read/write operation on the SDRAM, the state controller records the current state of the SDRAM as 000; when the SDRAM is controlled to enter different low power consumption modes, the current state of the SDRAM is recorded as 001, 010 or 011.
As shown in fig. 5, when the read/write from the CPU to the SDRAM is finished, the method for controlling the SDRAM to enter the low power consumption mode of the present embodiment includes the following steps:
step 501: the state controller sends a reset signal to the interrupt generator, and the interrupt generator starts to time;
step 502: the interrupt generator sends an interrupt signal to the state controller when the current timing value reaches a preset time value;
step 503: the state controller inquires and records the mode number of the SDRAM in the current low power consumption mode, and then the next number of the current mode number is used as the mode number of the SDRAM which needs to enter the low power consumption mode next time;
step 504: and the state controller generates a low-power-consumption mode control signal according to the mode number and sends the low-power-consumption mode control signal to the SDRAM.
In this embodiment, there are three different preset time values Ta, Tb, and Tc, and according to the interval T between two adjacent times of the CPU performing the read/write operation on the SDRAM, the SDRAM is controlled to enter the low power consumption mode under the following three different conditions:
if Ta < T < Tb, steps 502-504 need only be performed once. That is, the interrupt generator starts timing after reset and sends an interrupt signal to the state controller when the timing reaches Ta; the state controller inquires and records the mode number of the SDRAM in the current low-power mode, determines that the current mode number of the SDRAM is 000, and takes the next number of the current mode number, namely 001 as the mode number of the SDRAM which needs to enter the low-power mode next time; and the state controller generates a corresponding low-power mode control signal according to the mode number 001, sends the corresponding low-power mode control signal to the SDRAM and controls the SDRAM to enter the mode one. After the SDRAM enters the mode one, the interrupt generator will continue to count time, but since the CPU initiates read/write operation to the SDRAM when the time of Tb does not arrive, the SARAM is immediately controlled to enter the working mode, and the current mode number of the SDRAM is recorded as 000 again.
If Tb < T < Tc, then steps 502-504 need to be repeated once. That is, after the SDRAM is controlled to enter the low power consumption mode according to the first condition, since the CPU has not initiated the read/write operation on the SDRAM, the interrupt generator will continue to count time, and send the interrupt signal to the state controller again when the timing reaches Tb; the state controller inquires and records the mode number of the SDRAM current low-power-consumption mode again, determines that the SDRAM current mode number is 001, and takes the next number, namely 010, as the mode number of the SDRAM which enters the low-power-consumption mode next time; and the state controller generates a corresponding low-power-consumption mode control signal according to the mode number 010, sends the low-power-consumption mode control signal to the SDRAM and controls the SDRAM to enter a mode two. After the SDRAM enters the second mode, the interrupt generator will continue to count time, but since the CPU initiates read/write operation to the SDRAM when the Tc time is not reached, the SARAM is immediately controlled to enter the working mode, and the current mode number of the SDRAM is recorded as 000 again.
If Tb < T < Tc, then steps 502-504 need to be executed repeatedly twice, i.e. SDRAM will enter low power consumption mode one, then enter low power consumption mode two, and finally enter low power consumption mode three. That is, after controlling the SDRAM to enter the second low power consumption mode according to the second condition, since the CPU has not initiated the read/write operation on the SDRAM, the interrupt generator will continue to count time, and send the interrupt signal to the state controller again when the counted time reaches Tc; the state controller inquires and records the mode number of the SDRAM current low-power-consumption mode again, determines that the SDRAM current mode number is 010, and takes the next number, namely 011, as the mode number of the SDRAM which needs to enter the low-power-consumption mode next time; and the state controller generates a corresponding low-power mode control signal according to the mode number 011, sends the corresponding low-power mode control signal to the SDRAM and controls the SDRAM to enter a mode three. After entering mode three, the SDRAM will be in a low power state until the CPU initiates a read/write operation to the SDRAM.
In practical application, which low power consumption mode of the SDRAM corresponds to each preset time value can be determined by a user applying the scheme of the invention. Generally, the less power consuming mode is more complex, and the time to return to the normal mode from the low power consumption mode is also more time consuming. Therefore, a mode in which power consumption is low can be associated with a relatively large preset time value. That is, the SDRAM can first enter a low power consumption mode with high power consumption but relatively simple, and when the CPU still does not read/write for a long time, the SDRAM can then enter a low power consumption mode with low power consumption but relatively complex. Therefore, if the SDRAM needs to perform read/write operation after a short idle time, the SDRAM can quickly exit from a low power consumption mode and enter a normal working mode; if the idle time of the SDRAM is very long, the low power consumption mode with lower power consumption can be entered, and the purpose of reducing the power consumption to the maximum extent is achieved.
In practical application, if the SDRAM only provides one low power consumption mode, the state controller does not need to record which low power consumption mode the SDRAM is currently in, and only needs to send a fixed mode number to the SDRAM directly after receiving an interrupt signal, that is, directly take the mode number stored in the SDRAM in advance as the number of the SDRAM which is to enter the low power consumption mode next time. Such as: "1" can be defined as the number of the low power consumption mode of the SDRAM, and after the state controller receives the interrupt signal, the low power consumption mode control signal is directly generated according to the number "1".
In addition, in practical application, when the state controller receives a read/write control signal from the CPU, the state controller may immediately send a control signal for exiting the low power consumption mode to the SDRAM, and then enter a normal operation mode control signal to control the read/write operation on the SDRAM.
In summary, the above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (9)
1. A controller for controlling a memory into a low power mode, the controller comprising:
the interrupt generator is used for receiving a reset signal from the state controller, starting timing and outputting an interrupt signal to the state controller when a preset time value is reached;
the state controller is used for outputting a reset signal to the interrupt generator when the read-write operation of the memory is finished, receiving the interrupt signal from the interrupt generator, determining the number of a low power consumption mode to be entered by the memory, generating a low power consumption mode control signal according to the number of the low power consumption mode and outputting the low power consumption mode control signal to the memory;
wherein the state controller includes:
the core controller is used for outputting a reset signal to the interrupt generator, receiving the interrupt signal input by the interrupt generator and outputting the serial number of the low power consumption mode to be entered by the memory to the control signal generator;
and the control signal generator is used for generating a low-power-consumption mode control signal according to the mode number input by the core controller and outputting the low-power-consumption mode control signal to the memory.
2. The controller of claim 1, wherein the interrupt generator comprises:
the timer is used for receiving a reset signal from the state controller, starting timing and outputting an interrupt signal to the state controller when a preset time value provided by the timer configuration register is reached;
and the timer configuration register is used for saving a preset time value which is solidified in the timer or written by the CPU in advance and providing the preset time value for the timer.
3. The controller of claim 2, wherein the timer is a timer comprising one or more comparators;
the timer configuration register is a timer configuration register that stores one or more preset time values.
4. The controller of claim 1, wherein the state controller further comprises:
the memory state register is used for recording the mode number of the current low-power-consumption mode of the memory;
the core controller is further used for reading the mode number of the current low-power-consumption mode of the memory from the memory state register, taking the next number of the current low-power-consumption mode as the number of the low-power-consumption mode to be entered, and outputting the number of the low-power-consumption mode to be entered to the memory state register.
5. A controller according to any of claims 1 to 4, characterized in that the memory is a synchronous dynamic random access memory SDRAM.
6. A method for controlling a memory to enter a low power consumption mode is characterized in that a preset time value is set, and when the read-write operation of the memory is finished, the method further comprises the following steps:
A. the state controller sends a reset signal to the interrupt generator;
B. the interrupt generator starts timing according to the reset signal and sends an interrupt signal to the state controller when a preset time value is reached;
C. the state controller determines the number of the low power consumption mode to be entered by the memory according to the interrupt signal, and comprises the following steps: directly taking the mode number stored in a memory state register in the state controller in advance as the number of the low power consumption mode to be entered by the memory, or firstly inquiring the mode number of the current low power consumption mode of the memory recorded in the memory state register in the state controller and then taking the next number of the current mode number as the number of the low power consumption mode to be entered by the memory;
and generating a low power consumption mode control signal according to the number of the low power consumption mode, and sending the low power consumption mode control signal to a memory.
7. The method of claim 6, wherein the preset time value is one or more preset time values.
8. The method according to claim 6, wherein the method for setting the preset time value comprises the following steps: the preset time value is either fixed in the interrupt generator or written by the CPU into the interrupt generator.
9. The method according to any of claims 6 to 8, wherein the memory is an SDRAM.
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| CNB2006100905292A CN100524170C (en) | 2006-06-27 | 2006-06-27 | Controller for controlling memory to low power consumption mode and control method therefor |
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| CN100458663C (en) * | 2007-04-24 | 2009-02-04 | 北京中星微电子有限公司 | Control method for low-power consumption RAM and RAM control module |
| CN101639725B (en) * | 2008-07-31 | 2013-07-17 | 国际商业机器公司 | Device and method for processing instruction and executive control device used by same |
| US8417979B2 (en) * | 2010-12-23 | 2013-04-09 | Western Digital Technologies, Inc. | Method and system for progressive power reduction of inactive device while maintaining ready status with host |
| US8463970B2 (en) * | 2011-01-04 | 2013-06-11 | Qualcomm Incorporated | Method and system for managing sleep states of interrupt controllers in a portable computing device |
| KR20140122567A (en) * | 2013-04-10 | 2014-10-20 | 에스케이하이닉스 주식회사 | Semiconductor memory device including power on reset circuit |
| CN112234698A (en) * | 2020-08-03 | 2021-01-15 | 青岛鼎信通讯股份有限公司 | Design scheme for quickly entering low power consumption during power failure of electric energy meter |
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