CN114706722A - Multifunctional CPCI board card applied to test, launch and control system and control method - Google Patents

Abstract

The invention discloses a multifunctional CPCI board card applied to a test, launch and control system and a control method, and relates to the technical field of aerospace test, launch and control, wherein the multifunctional CPCI board card comprises an FPGA processing module, a CPCI bus module, a CAN bus module, an AD conversion module and a FLASH module, and the FPGA processing module is used for completing the control of a PCI bus, the control of a Local bus, the communication control of the CAN bus, the acquisition control of analog quantity and the control of a state machine through a bridge chip; the CPCI bus module is used for transmitting data between the PCI bus and the Local bus through the bridge chip; the CAN bus module is used for realizing data receiving and transmitting between the FPGA processing module and external equipment through a plurality of paths of CAN controllers. The invention can effectively meet the application requirements of the aerospace measurement and control system.

Description

Multifunctional CPCI board card applied to test, launch and control system and control method

Technical Field

The invention relates to the technical field of aerospace measurement and launch control, in particular to a multifunctional CPCI board card applied to a measurement and launch control system and a control method.

Background

Currently, in the technical application of aerospace measurement and control systems, a board card or a device is usually used to respectively realize functions of CAN (Controller Area Network) bus communication, analog quantity acquisition and device accumulated working time statistics.

However, the existing method has the following defects: firstly, the function is single, and the universality is not possessed; but the volume power consumption is large and the application is limited. Therefore, a multifunctional card based on the CPCI (Compact Peripheral Component Interconnect) bus technology is urgently needed at present to meet the application requirements of the aerospace measurement and control system.

Disclosure of Invention

Aiming at the defects in the prior art, the invention aims to provide the multifunctional CPCI board card applied to the test, launch and control system and the control method, which can effectively meet the application requirements of the aerospace test, launch and control system.

In order to achieve the above object, the present invention provides a multifunctional CPCI board card for a test, launch and control system, comprising:

the FPGA processing module is used for completing control of a PCI bus, control of a Local bus, CAN bus communication control, analog quantity acquisition control and state machine control through a bridge chip;

the CPCI bus module is used for carrying out data transmission between the PCI bus and the Local bus through the bridge chip;

the CAN bus module is used for realizing data receiving and transmitting between the FPGA processing module and external equipment through a plurality of paths of CAN controllers;

the AD conversion module is used for sequentially gating one path of the multi-path voltage signals through the relay switch and then sending the multi-path voltage signals to the isolation circuit;

the FLASH module is used for reading the accumulated working time when the power is off last time when the multifunctional CPCI board card is started up and storing the read time;

the Local bus is used for connecting the FPGA processing module and the CPCI bus module, and the Local bus is used for connecting the CPCI bus module and the computer mainboard.

On the basis of the technical proposal, the device comprises a shell,

the FPGA processing module is also used for realizing the code storage and loading functions through a configuration chip;

the FPGA processing module comprises a clock circuit, and the clock circuit is used for providing a clock signal required by the operation of the FPGA processing module.

On the basis of the technical scheme, the CPCI bus module is also used for setting the working mode of the Local bus and the matching impedance of the PCI bus through a resistor and storing the configuration information of an internal register of the bridge chip through the EEPROM.

On the basis of the technical scheme, the CAN bus module is also used for realizing level conversion among the plurality of paths of CAN buses through a level conversion chip and realizing the CAN transceiving isolation function through an optical coupling isolation chip.

On the basis of the technical scheme, the AD conversion module is also used for sending the isolation voltage signal to the operational amplifier following circuit for processing, and sending the signal processed by the operational amplifier following circuit to the ADC conversion circuit to realize ADC conversion.

On the basis of the technical scheme, the multifunctional CPCI board card further comprises a power supply module, and the power supply module is used for supplying power to the FPGA processing module, the CPCI bus module, the CAN bus module, the AD conversion module and the FLASH module.

The invention provides a control method of a multifunctional CPCI board card, which is used for controlling the multifunctional CPCI board card and specifically comprises the following steps:

receiving data from the PCI bus to the Local bus based on a periodic polling mode;

and transmitting the data from the Local bus to the PCI bus based on the interrupt mode.

On the basis of the technical scheme, the method further comprises the following specific steps of receiving the CAN data:

inquiring the CAN status register to judge whether data exists in the receiving register: if no data exists, continuously carrying out circular query on whether data exists in the receiving register; if so, inquiring whether the FIFO is in a non-full state, and writing the data in the receiving register into the FIFO when the FIFO is in the non-full state;

and circularly inquiring whether the FIFO is in a non-empty state and whether the last data of the left port of the DRAM interval is read, if so, reading the data in the FIFO and writing the read data into the right port of the DRAM interval.

On the basis of the technical scheme, the method further comprises the following specific steps of sending the CAN data:

querying a DRAM status register to determine if data is present in a receive area of the DRAM: if no data exists, continuously performing cycle query on whether data exists in a receiving area of the DRAM; if the data exists, the data from the PCI bus to the Local bus is received, whether the FIFO is in a non-full state or not is inquired, and when the FIFO is in the non-full state, the data of the right port of the DRAM interval is read and the read data is written into the FIFO;

inquiring the CAN status register to judge whether data exists in the sending register: if so, continuously performing circular query on whether the data exists in the sending register or not; if no data exists, whether the FIFO is in a non-empty state or not is inquired, and when the FIFO is in the non-empty state, the data in the FIFO is read, the read data is written into a CAN transmission register, and the data is transmitted to external equipment.

On the basis of the above technical solution, the method further includes, for the acquisition of ADC data, specifically:

realizing multi-channel analog signals by a relay in a certain cycle and sequentially gating one channel for collection;

and filtering the acquired data, sending the filtered data to the right port of the DRAM data area, and providing the data to a computer mainboard for processing by the left port of the DRAM data area.

Compared with the prior art, the invention has the advantages that: through the arrangement of the FPGA processing module, the CPCI bus module, the CAN bus module, the AD conversion module, the FLASH module and the power module, the whole control flow is simple and clear, the real-time performance is high, the improvement of the intellectualization and integration of the measurement and launch control system is facilitated, and the application requirements of the aerospace measurement and launch control system are effectively met.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a multifunctional CPCI board card applied to a test, launch and control system in an embodiment of the invention;

fig. 2 is a flowchart of a method for controlling a multifunctional CPCI board card according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments.

Referring to fig. 1, the multifunctional CPCI board applied to a test, launch and control system according to an embodiment of the present invention includes an FPGA (Field Programmable Gate Array) processing module, a CPCI bus module, a CAN (Controller Area Network) bus module, an AD (analog-digital) conversion module, a FLASH memory module, and a power supply module. The Local bus is used for connecting the FPGA processing module and the CPCI bus module, and the Local bus is used for connecting the CPCI bus module and the computer mainboard. The invention relates to a multifunctional CPCI board card, which is a device organically integrating CPCI bus communication, CAN bus communication, analog quantity acquisition and device accumulated working time.

The multifunctional board card provided by the embodiment of the invention is designed by adopting an FPGA + PCI bridge chip as a core framework, performs information interaction with a computer mainboard through a CPCI bus, and performs data transmission with a plurality of other devices through a CAN bus. The realization method is that the data are processed by a method of scheduling a plurality of tasks in parallel, wherein the response level of each task is reasonably set according to the importance of the equipment and the communication frequency. The corresponding control operation can be executed according to the control instruction of the computer mainboard.

In the embodiment of the present invention, the FPGA processing module is configured to complete control of a PCI (Peripheral Component Interconnect) bus, control of a Local bus, CAN bus communication control, analog quantity acquisition control, and state machine control through a bridge chip. The FPGA processing module is also used for realizing the code storage and loading functions through a configuration chip; the FPGA processing module comprises a clock circuit, and the clock circuit is used for providing a clock signal required by the operation of the FPGA processing module. The FPGA processing module is also used for realizing the code storage and loading functions through the configuration chip.

Specifically, the FPGA processing module is connected with the CAN bus module to realize multi-path CAN bus logic, the FPGA processing module is connected with the FLASH module to realize FLASH read-write logic, the FPGA processing module is connected with the AD conversion module to realize multi-path AD acquisition logic, the FPGA processing module is connected with a Local bus interface in the CPCI bus module to realize Local bus logic, and the FPGA processing module is connected with a PCI bus interface in the CPCI bus module to realize PCI bus logic. The FPGA processing module further includes a FIFO (First Input First Output, First in First out Memory), a DRAM (Dynamic Random Access Memory), an FPGA circuit, and a configuration circuit.

In the embodiment of the invention, the CPCI bus module is used for transmitting data between the PCI bus and the Local bus through the bridge chip; the CPCI bus module is further configured to set a working mode of the Local bus and a matching impedance of the PCI bus through a resistor, and store configuration information of an internal register of the bridge chip through an EEPROM (Electrically Erasable Programmable read only memory).

The CPCI bus module specifically comprises an EEPROM circuit and a PCI bridge circuit, wherein the PCI bridge circuit comprises a Local bus interface, a PCI bus interface and a serial EEPROM configuration register. The PCI bridge circuit is also used to implement the corresponding control logic.

In the embodiment of the invention, the CAN bus module is used for realizing data receiving and transmitting between the FPGA processing module and external equipment through a plurality of CAN controllers; the CAN bus module is also used for realizing level conversion among the plurality of paths of CAN buses through a level conversion chip and realizing CAN transmitting and receiving isolation functions through an optical coupling isolation chip. The CAN bus module is also used for remotely switching the bus resistance matching function through a relay. Specifically, the CAN bus module includes a CAN controller and a CAN transceiver, and the CAN transceiver is used for interacting with an external device.

In the embodiment of the invention, the AD conversion module is used for sequentially gating one path of the multi-path voltage signals through the relay switch and then sending the multi-path voltage signals to the isolation circuit; the AD conversion module is further configured to send the isolated voltage signal to an operational amplifier follower circuit for processing, and send a signal processed by the operational amplifier follower circuit to an ADC (analog-to-digital conversion) conversion circuit, so as to implement ADC conversion.

In the embodiment of the invention, the FLASH module is used for reading the accumulated working time when the power is off last time when the multifunctional CPCI board card is started and storing the read time.

In the embodiment of the invention, the power supply module is used for supplying power to the FPGA processing module, the CPCI bus module, the CAN bus module, the AD conversion module and the FLASH module. Specifically, the power module converts input 5V into voltages 3.3V, 1.8V, 1.2V and 1.0V required by the operation of the board card through the switching power supply chip, and converts input 5V into voltages 2.5V required by the operation of the board card through the linear power supply chip. The power supply module is also used for converting the input 5V voltage into +/-15V voltage required by the working of the AD conversion module through the isolated non-voltage-stabilized direct current/direct current converter chip and converting the input 5V voltage into 5V voltage required by the working of the CAN bus module through the isolated power supply chip.

The multifunctional CPCI board card applied to the measurement, launch and control system of the embodiment of the invention has the advantages that through the arrangement of the FPGA processing module, the CPCI bus module, the CAN bus module, the AD conversion module, the FLASH module and the power supply module, the whole control flow is simple and clear, the real-time performance is very strong, the improvement of the intellectualization and integration of the measurement, launch and control system is facilitated, and the application requirements of the aerospace measurement, launch and control system are effectively met.

Referring to fig. 2, a control method of a multifunctional CPCI board according to an embodiment of the present invention is used for controlling the multifunctional CPCI board, and the control method specifically includes the following steps:

s1: receiving data from the PCI bus to the Local bus based on a periodic polling mode;

s2: and transmitting the data from the Local bus to the PCI bus based on the interrupt mode.

The software allocates Local bus data receiving and transmitting contents to a plurality of DRAM areas by taking a base address as an offset, and each DRAM area comprises 32 bits × 2 data of the nth power. When Local bus data are received, writing operation is carried out on the DRAM; when Local bus data is transmitted, a read operation is performed on the DRAM.

In the embodiment of the present invention, the receiving of the CAN data specifically includes:

inquiring the CAN status register to judge whether data exists in the receiving register: if no data exists, continuously carrying out circular query on whether data exists in the receiving register; if so, inquiring whether the FIFO is in a non-full state, and writing the data in the receiving register into the FIFO when the FIFO is in the non-full state;

and circularly inquiring whether the FIFO is in a non-empty state and whether the last data of the left port of the DRAM interval is read, if so, reading the data in the FIFO and writing the read data into the right port of the DRAM interval, and simultaneously setting the receiving interrupt to be effective.

In the embodiment of the present invention, the sending of the CAN data specifically includes:

querying a DRAM status register to determine if data is present in a receive area of the DRAM: if no data exists, continuously performing cycle query on whether data exists in a receiving area of the DRAM; if the data exists, the data from the PCI bus to the Local bus is received, whether the FIFO is in a non-full state or not is inquired, and when the FIFO is in the non-full state, the data of the right port of the DRAM interval is read and the read data is written into the FIFO;

inquiring the CAN status register to judge whether data exists in the sending register: if so, continuously performing cycle query on whether the data exists in the sending register; if no data exists, whether the FIFO is in a non-empty state or not is inquired, and when the FIFO is in the non-empty state, the data in the FIFO is read, the read data is written into a CAN transmission register, and the data is transmitted to external equipment.

In the embodiment of the present invention, the acquisition of ADC data specifically includes:

realizing multi-channel analog signals by a relay in a certain cycle and sequentially gating one channel for collection;

and filtering the acquired data, sending the filtered data to the right port of the DRAM data area, and providing the data to a computer mainboard for processing by the left port of the DRAM data area.

In the embodiment of the invention, the reading and writing of the FLASH data comprises the following steps: firstly, when the board card is used for power distribution, reading the accumulated working time of the last power failure from two FLASH sectors on the board by software; and comparing the two data, wherein the maximum time is the reference value of the accumulated working time. And secondly, accumulating according to the accumulated working time reference value, updating the accumulated working time, performing write-in operation on one of the two sectors of the FLASH every minute by adopting a ping-pong strategy, and simultaneously sending the updated accumulated working time to the right port of the DRAM data area, and the left port of the DRAM data area is sent to a computer mainboard for display and use by other equipment.

The above description is merely exemplary of the present application and is presented to enable those skilled in the art to understand and practice the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

Claims (10)

1. The utility model provides a be applied to multi-functional CPCI integrated circuit board of survey and launch control system which characterized in that includes:

the FPGA processing module is used for controlling a PCI bus, a Local bus, a CAN bus communication, an analog quantity acquisition and a state machine through a bridge chip;

the CPCI bus module is used for carrying out data transmission between the PCI bus and the Local bus through the bridge chip;

the CAN bus module is used for realizing data receiving and transmitting between the FPGA processing module and external equipment through a plurality of CAN controllers;

the AD conversion module is used for sequentially gating one path of the multi-path voltage signals through the relay switch and then sending the multi-path voltage signals to the isolation circuit;

the FLASH module is used for reading the accumulated working time when the power is off last time when the multifunctional CPCI board card is started up and storing the read time;

the Local bus is used for connecting the FPGA processing module and the CPCI bus module, and the Local bus is used for connecting the CPCI bus module and the computer mainboard.

2. The multifunctional CPCI board card applied to the measurement, launch and control system of claim 1, wherein:

the FPGA processing module is also used for realizing the code storage and loading functions through a configuration chip;

the FPGA processing module comprises a clock circuit, and the clock circuit is used for providing a clock signal required by the operation of the FPGA processing module.

3. The multifunctional CPCI board card applied to the measurement, launch and control system of claim 1, wherein: the CPCI bus module is also used for setting the working mode of the Local bus and the matching impedance of the PCI bus through a resistor and storing the configuration information of the internal register of the bridge chip through the EEPROM.

4. The multifunctional CPCI board card applied to the measurement, launch and control system of claim 1, wherein: the CAN bus module is also used for realizing level conversion among the plurality of paths of CAN buses through a level conversion chip and realizing CAN transmitting and receiving isolation functions through an optical coupling isolation chip.

5. The multifunctional CPCI board card applied to the measurement, launch and control system of claim 1, wherein: the AD conversion module is also used for sending the isolated voltage signal to the operational amplifier following circuit for processing, and sending the signal processed by the operational amplifier following circuit to the ADC conversion circuit to realize ADC conversion.

6. The multifunctional CPCI board card applied to the measurement, launch and control system of claim 1, wherein: the multifunctional CPCI board card further comprises a power supply module, and the power supply module is used for supplying power to the FPGA processing module, the CPCI bus module, the CAN bus module, the AD conversion module and the FLASH module.

7. A control method of a multifunctional CPCI board card, which is used for controlling the multifunctional CPCI board card of any one of claims 1 to 6, and is characterized in that: the control method specifically comprises the following steps:

receiving data from the PCI bus to the Local bus based on a periodic polling mode;

and transmitting the data from the Local bus to the PCI bus based on the interrupt mode.

8. The method for controlling a multifunctional CPCI board card according to claim 7, further comprising, for receiving CAN data, specifically:

inquiring the CAN status register to judge whether data exists in the receiving register: if no data exists, continuously carrying out circular query on whether data exists in the receiving register; if so, inquiring whether the FIFO is in a non-full state, and writing the data in the receiving register into the FIFO when the FIFO is in the non-full state;

and circularly inquiring whether the FIFO is in a non-empty state and whether the last data of the left port of the DRAM interval is read, if so, reading the data in the FIFO and writing the read data into the right port of the DRAM interval.

9. The method for controlling a multifunctional CPCI board card according to claim 7, further comprising, for the transmission of CAN data, specifically:

querying a DRAM status register to determine if data is present in a receive area of the DRAM: if no data exists, continuously performing cycle query on whether data exists in a receiving area of the DRAM; if the data exists, the data from the PCI bus to the Local bus is received, whether the FIFO is in a non-full state or not is inquired, and when the FIFO is in the non-full state, the data of the right port of the DRAM interval is read and the read data is written into the FIFO;

inquiring the CAN status register to judge whether data exists in the sending register: if so, continuously performing cycle query on whether the data exists in the sending register; if no data exists, whether the FIFO is in a non-empty state or not is inquired, and when the FIFO is in the non-empty state, the data in the FIFO is read, the read data is written into a CAN transmission register, and the data is transmitted to external equipment.

10. The method for controlling the multifunctional CPCI board card according to claim 7, further comprising, for the acquisition of ADC data, specifically:

a relay realizes a plurality of paths of analog signals in a certain period cycle and sequentially gates one path for collection;

and filtering the acquired data, sending the filtered data to the right port of the DRAM data area, and providing the data to a computer mainboard for processing by the left port of the DRAM data area.

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