CN101512496A - Device and method for monitoring operation of a flash memory - Google Patents
Device and method for monitoring operation of a flash memory Download PDFInfo
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- CN101512496A CN101512496A CNA2006800418711A CN200680041871A CN101512496A CN 101512496 A CN101512496 A CN 101512496A CN A2006800418711 A CNA2006800418711 A CN A2006800418711A CN 200680041871 A CN200680041871 A CN 200680041871A CN 101512496 A CN101512496 A CN 101512496A
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Abstract
A flash memory device includes an array of memory cells for storing data pages, at least one buffer (e.g. a memory buffer and a cache buffer) for transferring the data pages to and from the array of memory cells and a host, and an output pin. A logic mechanism is operative to select, from among a plurality of conditions related to an operation on the array of memory cells, a condition that drives a signal being output on the output pin. A data page transfer by the host is contingent on the signal being output on the output pin.
Description
Technical field
Present invention relates in general to a kind of method of operating of monitoring flash memory device effectively that is used for.
Background technology
Flush memory device cicada just for many years.Technical known standard flash memory device is with arranging in groups memory array-the be called as page and/or piece-store data.
An example of technical known nand flash memory device is the device No.K9K4G08U1M that Samsung produces.The data page of this device (here with-DS represent) is whole to be hereby incorporated by reference.
When with the flash memory swap data, usually from/whole data page is written to the memory array or from memory array simultaneously in single job to the internal buffer that is called as page-buffer (or register) and reads.The host apparatus that flash memory connected transmits data/data are sent to this page-buffer from this page-buffer.
Divide two stages to realize from the process of flush memory device reading of data.In the phase one, data are sent to the page-buffer of flush memory device from memory array.In subordinate phase, data are sent to host apparatus from page-buffer.
The process that writes data into flush memory device also divides two stages to realize, promptly in the phase one, data are sent to the page-buffer of flush memory device from host apparatus, and in subordinate phase, data are sent to memory array from page-buffer.
Data between host apparatus and page-buffer transmit by the hardware of host apparatus and/or software module control, so the beginning that transmits of these data and finishing directly by these module controls.Yet the data between page-buffer and memory array transmit and are independently carried out by flush memory device usually, and get involved without host apparatus.So the hardware of host apparatus and/or software module are not also known such transmission sequential.
Because it is time-consuming (this stage continues tens to the hundreds of microsecond) that the data between page-buffer and memory array transmit, the special notification of busy memory array is provided for host apparatus.This notice is implemented as by flush memory device and produces and by " ready/busy " hardware signal of host apparatus monitoring.
On the embodiment of hardware signal, the above-mentioned notice of busy memory array can be further provided to host device software in status information via " status register ".
For example, behind complete operation, hardware signal can generate the interruption for host apparatus, be ready for the new operation of execution with the expression flush memory device, perhaps as an alternative, the software module of host apparatus can the poll memory status register, waits for this incident.
Comprise host apparatus for the time that exchanges data spent between host apparatus and flush memory device
Buffer and buffer
The memory array delivery time at interval.Along with the data page size increase of existing flush memory device, host apparatus
The buffer delivery time also increases, and become can with buffer
The memory array delivery time compares.For example, have the 2K byte data page, technically in the known nand flash memory device, host apparatus
The buffer delivery time is every page 50 to 100 microsecond typically, and buffer
The memory array time for reading is every page 20 to 50 microsecond, and buffer
Memory array page program (writing) time is every page 200 to 800 microsecond.
Therefore, in order to improve throughput of system, some flush memory device comprises additional data buffer, and promptly cache buffer memory device is used for carrying out simultaneously data and transmits between host apparatus and this cache buffer memory device and between page-buffer and memory array.
Should be pointed out that its data page has only adopted the cache buffer memory device that is used for page program at the nand flash memory device that is hereby incorporated by reference, yet, also have other device, also use cache buffer memory device to be used for read operation.
In order to provide necessary transmission time sequence information to host apparatus, comprise that the existing flush memory device of such cache buffer memory device comprises two logics " ready/busy " indication to realize time efficiency.First indication is defined as " cache buffer memory device ready/busy " (or only " ready/busy "), the availability of the cache buffer memory device that is used to represent that relevant data transmits.Second indication is defined as " ready really/busy ", is used to represent the current state of memory array.
In fact, host apparatus need use this two indications.The next data that " cache buffer memory device ready/busy " indication is used to trigger in a series of data transmit transmit, and " ready really/busy " indication is used to represent that the current operation that whether moves in flush memory device is finished, memory array be empty, and can start different operations.This can occur in and read when switching to page program or vice versa from the page when needs, when perhaps occurring in and to know current page program when application program and finish really (page data is arranged in memory array, and not only in buffer) and can start the next procedure of application program.
Yet, in the known technically flush memory device, have only " hypervelocity ready/busy " indication for example and (promptly with " hardware mode " by generating for the interruption of application program, be provided as hardware " ready/busy " signal) processed, and " ready really/busy " indication is only by the software module poll of host apparatus, therefore increase the complicacy of this module, reduced its dirigibility and time efficiency.
A kind of selection of dealing with this situation is to adopt by two logics " ready/busy " indication of flush memory device as hardware signal output.
Yet such method is unpractiaca, because it has violated standard NAND flash interface, and the similar device that does not comprise cache buffer memory device is not possessed compatibility.
The existing method that is used for the operation of monitoring flash memory device can not realize two logics " ready/busy " indication in " hardware " mode.
Therefore, extensively recognize the method for operating that needs a kind of flush memory device and be used to monitor this flush memory device, this is very favorable, and this method is the alternative method of prior art, makes that flush memory device is compatible for standard NAND flash interface.
Summary of the invention
Therefore, main purpose of the present invention provides a kind of alternative method of prior art of the operation that is used for the monitoring flash memory device.
The present invention relates to a kind of flush memory device and the method for operating that is used to monitor this flush memory device of novelty, and provide two logics " ready/busy " indication that realizes with hardware mode simultaneously as single hardware signal, so that flush memory device is compatible for standard NAND flash interface.
Flush memory device of the present invention comprises logic mechanism, and its operation changes the logical meaning (that is, calling the condition of this signal) of the signal of exporting on the output pin between a plurality of signals with the request of being declared according to main frame.
According to the present invention, a kind of flush memory device is provided, comprising: the memory cell array that (a) is used to store page of data; (b) be used at least one buffer that page of data is sent to main frame and is sent to memory cell array from main frame from memory cell array; (c) output pin; And (d) logic mechanism, this logic mechanism operation is to select to drive the condition of the signal of exporting at output pin from a plurality of conditions relevant with the operation of memory cell array.
Preferably, the condition of the signal that driving is exported on output pin is: memory cell array is busy (promptly, memory cell array is being addressed and is reading, is programming, is upgrading, wiping or the like), an or buffer busy (that is, this memory buffer is being addressed and is reading, programmes, upgrades, wipes or the like).Preferably, this condition is compound condition (i.e. the boolean combination of two other conditions), for example memory cell array is busy busy with buffer (for example memory buffer), memory cell array is busy or memory buffer is busy, memory cell array is not busy busy with memory buffer, memory cell array is not busy or memory buffer is busy, memory cell array is busy or not with memory buffer, memory cell array is busy or memory buffer is not busy, memory cell array is not busy or not with memory buffer, and memory cell array is not busy or memory buffer is not busy.
Alternatively, the condition that is invoked at the signal of exporting on the output pin is an operation failure.
Alternatively, the condition that is invoked at the signal of exporting on the output pin can be a logical operational state, wipes failure or the like as page program failure, piece.
Preferably, logic mechanism is according to the described condition of at least one command selection that receives from main frame.As an alternative, when receiving order, the described logic mechanism of this command operation is to change this condition at every turn.Preferably also continue to change till flush memory device receives reset command, perhaps till flush memory device is powered on.Obviously, even without reset command or power on, this order also can be cancelled by the order of back.Preferably also turning back to before the operation under the default mode for only lasting change of write/erase operation.Preferably also make described logic mechanism according to the described condition of command selection that receives from main frame, make each order corresponding to a corresponding different condition (for example setting) by relevant parameters.
According to the present invention, a kind of method of operating that is used for the monitoring flash memory device also is provided, this method may further comprise the steps: (a) send a command to flush memory device, the indication flush memory device is selected a condition from a plurality of conditions, and the state of output pin changes with this understanding; (b) state of the change by the perception output pin is inquired this condition.
Take place when preferably, the page of data of being undertaken by main frame is transmitted in the selected condition of inquiry temporarily.
Preferably, described condition is that memory cell array is busy, the busy or compound condition (for example, memory cell array (no) is busy, and/or memory buffer (no) is busy) of buffer (for example memory buffer).
Preferably, described condition is an operation failure.
Preferably, the condition that is invoked at the signal of exporting on the output pin can be a logical operational state, wipes failure or the like such as page program failure, piece.
To understand other features and advantages of the present invention from following accompanying drawing and description.
Description of drawings
In order to understand embodiments of the invention better, with reference to the accompanying drawings, identical Reference numeral is represented corresponding part or unit among the figure, in the drawings:
Unique accompanying drawing is the block diagram according to preferred flush memory device of the present invention.
Embodiment
The present invention relates to a kind of flush memory device and the method for operating that is used to monitor this flush memory device of novelty, provide two logics " ready/busy " indication that realizes in " hardware " mode as single hardware signal simultaneously, make that flush memory device is compatible for standard NAND flash interface.
Flush memory device according to the present invention comprises logic mechanism, and its operation selects to drive the condition of the signal of exporting on output pin with the request of being declared by main frame alternatively.This condition be from after the operation to the operation that is in the memory cell array under the busy condition or for example after operation, select the relevant a plurality of conditions of failure indication.
As the example that uses such " ready/busy " indication, hardware signal can be to the interruption of main frame behind complete operation, the expression flush memory device has been ready for new operation, and perhaps as an alternative, main frame can change to search state by the poll memory state.
Flush memory device of the present invention can be used for declaring hardware signal equally, and " cache ready/busy " indication, only " ready really/busy " indication or " cache ready/busy " and " ready really/busy " indication are provided simultaneously only are provided.Flush memory device can also select compound condition (i.e. the boolean combination of two other conditions) as described condition, busy busy such as memory cell array with buffer, memory cell array is busy or memory buffer is busy, memory cell array is not busy busy with memory buffer, memory cell array is not busy or memory buffer is busy, memory cell array is busy or not with memory buffer, memory cell array is busy or memory buffer is not busy, memory cell array is not busy or not with memory buffer, and memory cell array is not busy or memory buffer is not busy.
Referring now to Fig. 1, there is shown the block diagram of preferred flush memory device 10 of the present invention.Flush memory device 10 comprises and is used to store the memory array 12 of the storage unit C1 of page of data to Cn.The host apparatus 20 that flush memory device connected is sent to page of data I/O (I/O) interface unit 34 and transmits page of data from this input/output interface unit 34 via data-signal 36.
Whole data page is written to storage unit or it is read/be read into page-buffer 16 from page-buffer 16.Flush memory device 10 comprises additional data buffer-cache buffer memory device 18, is used for carrying out the data transmission between host apparatus 20 and the cache buffer memory device 18 and between cache buffer memory device 18 and storage unit 12 simultaneously.Data simultaneously transmit the total handling capacity that has improved flush memory device 10.
Status information such as two logics " ready really/busy " and " cache ready/busy " indication, also is provided to host apparatus 20 from the memory status register 32 that is connected to logic mechanism 22.This status information is sent to host apparatus 20 from memory status register 32 via I/O (I/O) interface unit 34.
In preferred embodiments more of the present invention, the order of 20 that declared from host apparatus, as to be used to change RDY/BSY signal 26 meaning is operation logic mechanism 22 as follows:
In a preferred embodiment, implement an order, the meaning of this command conversion " ready/busy " signal when each host apparatus sends this order.
In a further advantageous embodiment, provide a pair of order, make each order that RDY/BSY signal 26 is set and be different meanings.
In the 3rd preferred embodiment, the order that comprises relevant parameter is provided, make the meaning of RDY/BSY signal 26 be explained by explicitly according to this parameter.
In the 4th preferred embodiment, an order is provided, this command operation logic mechanism 22 the metasemy of RDY/BSY signal 26 to default setting, until run into reset command or the incident that powers on till.
In the 5th preferred embodiment, an order is provided, this command operation logic mechanism 22 changes the meaning of RDY/BSY signal 26, till occurring from " busy " state transformation to " being ready to " state (after such conversion, automatically returning to previous state).
The present invention is described to provide two logics " cache ready/busy " and " ready really/busy " indication here.Yet the present invention is not limited only to this two logic indications, but the indication of other logical operational state in the storage component part that can be applicable to equally provide in a similar fashion (for example, page program failure, piece are wiped failure or the like).
Mentioned the nand flash memory device although should be pointed out that the present invention.Yet, be appreciated that other embodiment within the scope of the invention also is possible, therefore relate to any equipment and the method for the operation that is used for the monitoring flash memory device.
After describing the present invention for some specific embodiment of the present invention, be to be understood that, the description does not here also mean that restriction, because those skilled in the art can advise other modification now, it has covered the such modification in the scope that belongs to appended claims.
Claims (18)
1. flush memory device comprises:
(a) be used to store the memory cell array of page of data;
(b) be used between described memory cell array and main frame transmitting at least one buffer of described page of data;
(c) output pin; And
(d) logic mechanism, this logic mechanism operation is to select to drive the condition of the signal of exporting at output pin from a plurality of conditions relevant with the operation of described memory cell array.
2. the flush memory device of claim 1, the condition of wherein said selection is that described memory cell array is busy.
3. the flush memory device of claim 1, the condition of wherein said selection is that a buffer in described at least one buffer is busy.
4. the flush memory device of claim 1, the condition of wherein said selection is a compound condition.
5. the flush memory device of claim 1, the condition of wherein said selection is an operation failure.
6. the flush memory device of claim 1, the condition of wherein said selection is the logical operational state of selecting from the group that comprises following state: page program failure and piece are wiped failure.
7. the flush memory device of claim 1, wherein said logic mechanism is according to the described condition of at least one command selection that receives from described main frame.
8. the flush memory device of claim 7, when wherein receiving described at least one order, the described logic mechanism of described at least one command operation is to change described condition at every turn.
9. the flush memory device of claim 7, wherein said logic mechanism keeps described selection, until run into the incident of selecting from the group that comprises reset command and power on till.
10. the flush memory device of claim 7, wherein said logic mechanism keeps described selection during only starting individual command.
11. the flush memory device of claim 7, wherein said logic mechanism are according to the described condition of described at least one command selection that receives from described main frame, each described at least one order is corresponding to a corresponding different condition.
12. a method of operating that is used for the monitoring flash memory device, this method may further comprise the steps:
(a) send a command to flush memory device, select a condition with the indication flush memory device from a plurality of conditions, the state of output pin changes with this understanding; With
(b) state of the described change by the described output pin of perception is inquired the condition of described selection.
13. page of data wherein takes place to the described inquiry of the condition of described selection and transmits in the method for claim 12 temporarily.
14. the method for claim 12, the condition of wherein said selection are that memory cell array is busy.
15. the method for claim 12, the condition of wherein said selection are that buffer is busy.
16. the method for claim 12, the condition of wherein said selection is a compound condition.
17. the method for claim 12, the condition of wherein said selection is an operation failure.
18. the method for claim 12, the condition of wherein said selection are the logical operational state of selecting from the group that comprises following state: page program failure and piece are wiped failure.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US73470805P | 2005-11-09 | 2005-11-09 | |
| US60/734,708 | 2005-11-09 | ||
| US11/399,343 | 2006-04-07 |
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| Publication Number | Publication Date |
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| CN101512496A true CN101512496A (en) | 2009-08-19 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNA2006800418711A Pending CN101512496A (en) | 2005-11-09 | 2006-11-06 | Device and method for monitoring operation of a flash memory |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103403681A (en) * | 2010-12-20 | 2013-11-20 | 马维尔国际贸易有限公司 | Descriptor scheduler |
| CN107229570A (en) * | 2016-03-23 | 2017-10-03 | 爱思开海力士有限公司 | Storage arrangement and its operating method |
| CN108874303A (en) * | 2017-05-09 | 2018-11-23 | 西部数据技术公司 | The stocking system and method that nonvolatile memory command collision avoids |
-
2006
- 2006-11-06 CN CNA2006800418711A patent/CN101512496A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103403681A (en) * | 2010-12-20 | 2013-11-20 | 马维尔国际贸易有限公司 | Descriptor scheduler |
| CN103403681B (en) * | 2010-12-20 | 2018-09-18 | 马维尔国际贸易有限公司 | Descriptor scheduler |
| CN107229570A (en) * | 2016-03-23 | 2017-10-03 | 爱思开海力士有限公司 | Storage arrangement and its operating method |
| CN108874303A (en) * | 2017-05-09 | 2018-11-23 | 西部数据技术公司 | The stocking system and method that nonvolatile memory command collision avoids |
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Application publication date: 20090819 |