WO2020239027A1

WO2020239027A1 - Fpga circuit, system, configuration method, and computer readable medium

Info

Publication number: WO2020239027A1
Application number: PCT/CN2020/092924
Authority: WO
Inventors: 徐浩
Original assignee: 深圳市紫光同创电子有限公司
Priority date: 2019-05-29
Filing date: 2020-05-28
Publication date: 2020-12-03
Also published as: JP7024119B2; JP2021529361A; CN110347620A

Abstract

Embodiments of the present application provide an FPGA circuit, a system, a configuration method, and a computer readable medium. The FPGA circuit comprises a physical layer, a data strobe signal gating circuit connected to the physical layer, and a delay compensation loop connected to the data strobe signal gating circuit. The physical layer sends a read command to an external memory, and sends a window control signal to the data strobe signal gating circuit at the same time, such that the external memory outputs, upon completion of a read operation, a data strobe signal to the data strobe signal gating circuit. The window control signal sequentially passes through the data strobe signal gating circuit and the delay compensation loop, and uses the signal that has passed through the delay compensation loop as a target window signal. The delay compensation loop comprises a delay loop and a compensation path. The compensation path is provided between any two devices in the delay loop, and forms at least two delay paths by means of different impedance values. The data strobe signal gating circuit is used to adjust, according to the target window signal and the data strobe signal, a position of the target window signal relative to the data strobe signal. The invention improves flexibility of delay compensation, and enhances operational stability of FPGA DDR interfaces.

Description

FPGA circuit, system, setting method and computer readable medium

Cross references to related applications

This application claims the priority of the Chinese patent application with the application number 201910459457.1 and titled "A FPGA Circuit and System" filed with the Chinese Patent Office on May 29, 2019, the entire content of which is incorporated into this application by reference.

Technical field

The embodiments of the present application relate to but not limited to the field of integrated circuit design, and specifically relate to but not limited to an FPGA (Field-Programmable Gate Array) circuit, system, setting method, and computer readable medium.

Background technique

In DDR (Double Data Rate, double-rate synchronous dynamic random access memory) memory, its input and output data are synchronized with the rising and falling edges of the clock. Therefore, a bidirectional DQS (Data Strobe) with the same frequency as the clock is required in read and write operations. Signal, data strobe signal) signal to capture data. This DQS signal is in a high-impedance state when not in use, and the DQS signal window is usually obtained through the DQS-GATE related circuit to obtain the correct DQS signal. At the same time, to ensure that the DQS_GATE detection circuit can dynamically delay according to the change of VT conditions in practical applications Time adjustment, DQS_GATE circuit will send the DQS window enable signal through the loop output and then input. Since the DQS signal and the window control signal reach the inside of the DQS_GATE circuit through different paths, the delay caused by the change of VT between the two cannot be exactly the same, so the traditional compensation scheme may not be able to achieve the relative position of the DQS signal and the window signal with the VT It remains unchanged when changed, resulting in unstable interface operation.

Summary of the invention

The FPGA circuit, system, setting method, and computer readable medium provided by the embodiments of the present application mainly solve the technical problem that the relative time delay of the data strobe signal and the window signal is not constant, which causes the FPGA DDR interface to work unstable.

In the first aspect, an embodiment of the present application provides an FPGA circuit including a physical layer, a data strobe signal gating circuit connected to the physical layer, and a data strobe signal gating delay compensation circuit connected to the data strobe signal gating circuit The physical layer is used to send a read command to the external memory, and at the same time send a window control signal to the data strobe signal gating circuit, so that the external memory outputs a data strobe signal to the data strobe signal gate when the read operation is completed Control circuit; the window control signal sequentially passes through the data strobe signal gating circuit, the data strobe signal gating delay compensation loop, and the signal passing through the data strobe signal gating delay compensation loop is used as the target window signal Wherein, the data strobe signal gated delay compensation loop includes a delay loop and a compensation path, the compensation path is arranged between any two devices in the delay loop, and the compensation path is formed by different impedance values at least Two delayed paths; the data strobe signal gating circuit is used to adjust the position of the target window signal relative to the data strobe signal according to the target window signal and the data strobe signal.

Optionally, the FPGA circuit further includes a first circuit, and the physical layer sends a read command to an external memory through the first circuit; the first circuit includes a first input-output logic, a first input-output module, a first The pad, the first input/output logic is connected to the physical layer, and the first pad is connected to the external memory.

Optionally, the FPGA circuit further includes a second circuit configured to send the data strobe signal fed back by the external memory when the read operation is completed to the data strobe signal gating control Circuit.

Optionally, the second circuit includes a second pad, a second input-output module, and a second input-output logic connected in sequence, the second pad is connected to an external memory, and the second input-output logic is connected to a data strobe signal gate. Control circuit connection.

Optionally, the delay loop includes a third input-output logic, a third input-output module, a third pad, a fourth pad, a fourth input-output module, and a fourth input-output logic connected in sequence, where the third input The output logic and the fourth input and output logic are respectively connected to both ends of the data strobe signal gating circuit; the compensation path is arranged between any two adjacent devices in the delay loop.

Optionally, the compensation path is arranged in the delay loop, between the third pad and the fourth pad.

Optionally, the compensation path includes at least two sub-paths connected in parallel, and different impedances between the sub-paths form different delays.

Optionally, the compensation path includes four sub-paths connected in parallel, and the impedances of the sub-paths are 50%, 75%, 100%, and 120%, respectively.

Optionally, the compensation path includes at least one sub-path, and the impedance of the sub-path is an adjustable impedance.

Optionally, the compensation path includes a sub-path, and the impedance of the sub-path is adjustable. By adjusting the impedance of the sub-path, different delays are formed.

Optionally, the data strobe signal gating circuit includes: a window generation module for converting a parallel window control signal into a serial window control signal; a window position adjustment module for controlling a serial window control signal The position of the data strobe is adjusted; the selection module is used to select one from the target window control signal and the serial window control signal adjusted by the window position adjustment module, and output it to the data strobe signal gating processing module; The data strobe signal gating processing module is used to perform a logical AND operation on the data strobe signal and the signal selected by the selection module.

Optionally, the selection module includes a two-input selector.

Optionally, the two-input selector is used to select one of the two input signals as an output.

Optionally, the first terminal of the window generating module is connected to the physical layer, and the second terminal of the window generating module is connected to the window position adjustment module.

Optionally, the second terminal of the window position adjustment module is logically connected to the first terminal of the selection module and the third input and output of the delay loop respectively.

Optionally, the first terminal of the selection module is logically connected to the third input/output of the delay loop, the second terminal of the selection module is logically connected to the fourth input/output of the delay loop, and the selection module The third terminal of is connected to the data strobe signal gating processing module.

Optionally, the first terminal of the data strobe signal gating processing module is connected to the third terminal of the selection module, and the first terminal of the data strobe signal gating processing module is connected to the second circuit The second input and output are logically connected.

In a second aspect, an embodiment of the present application also provides an FPGA system, including a memory and the above FPGA circuit, wherein the memory receives a read command sent by the physical layer in the FPGA circuit, and when the read operation is completed, outputs data Strobe signal to data strobe signal gating circuit.

In a third aspect, an embodiment of the present application also provides an FPGA circuit setting method, which is applied to the above FPGA system. The FPGA system includes a memory and an FPGA circuit. The FPGA circuit includes a physical layer and a data strobe signal gating circuit connected to the physical layer. A data strobe signal gating delay compensation loop connected to the data strobe signal gating circuit, the method includes: the physical layer sends a read command to an external memory, and sends a window control signal to the data strobe signal gating circuit of the FPGA circuit The window control signal sequentially passes through the data strobe signal gating circuit and the data strobe signal gating delay compensation loop to obtain the target window signal; the external memory receives the read command sent by the physical layer, and outputs the data when the read operation is completed The strobe signal is sent to the data strobe signal gating circuit; the data strobe signal gating circuit adjusts the position of the target window signal relative to the data strobe signal according to the target window signal and the data strobe signal.

In a fourth aspect, an embodiment of the present application also provides a computer-readable medium having program code executable by a processor, and the program code causes the processor to execute the foregoing method.

The beneficial effects of the present invention are:

An FPGA, a system, a setting method, and a computer readable medium provided according to embodiments of the present application include a physical layer, a data strobe signal gating circuit connected to the physical layer, and a data strobe signal gating circuit connected to the data strobe signal gating circuit. Pass signal gating delay compensation loop; the physical layer is used to send the read command to the external memory, and at the same time send the window control signal to the data strobe signal gating circuit, so that the external memory will output the data strobe signal to the Data strobe signal gating circuit; the window control signal sequentially passes through the data strobe signal gating circuit and the data strobe signal gating delay compensation loop, and the signal passing through the data strobe signal gating delay compensation loop is used as the target window signal; Among them, the data strobe signal gated delay compensation loop includes a delay loop and a compensation path. The compensation path is arranged between any two devices in the delay loop, and the compensation path forms at least two delayed paths through different impedance values; data selective communication The number gating circuit is used to adjust the position of the target window signal relative to the data strobe signal according to the target window signal and the data strobe signal. Therefore, by setting the compensation path in the delay compensation loop, the flexibility of delay compensation is improved, and the stability of the FPGA DDR interface is also improved.

Other features and corresponding beneficial effects of the present invention are described in the latter part of the specification, and it should be understood that at least some of the beneficial effects will become apparent from the description in the specification of the present invention.

Description of the drawings

FIG. 1 is a block diagram of the FPGA circuit structure provided by Embodiment 1 of the application;

Fig. 2 is a block diagram of the FPGA system structure provided by the first embodiment of the application;

FIG. 3 is a method flowchart of the FPGA circuit setting method provided by an embodiment of the application;

FIG. 4 is a storage unit provided by an embodiment of the present application for storing or carrying program code for implementing the FPGA circuit setting method according to the embodiment of the present application.

Detailed ways

In order to make the objectives, technical solutions, and advantages of the present invention clearer, the following further describes the embodiments of the present invention in detail through specific implementations in conjunction with the accompanying drawings. It should be understood that the specific embodiments described here are only used to explain the present invention, but not to limit the present invention.

Example one:

This embodiment provides an FPGA circuit. Please refer to FIG. 1. The circuit includes a physical layer (PhysicalLayer, PHY) 101, and a data strobe signal gating circuit (Data Strobe Signal GATING, DQS GATING) 102 connected to the physical layer 101 , The data strobe signal gating delay compensation circuit 103 connected to the data strobe signal gating circuit 102.

The physical layer 101 is used to send a read command to an external memory, and at the same time send a window control signal to the data strobe signal gating circuit 102, the window control signal may be a GATE window control signal.

When the read operation is completed, the external memory outputs a data strobe signal (DQS signal) to the data strobe signal gating circuit 102; wherein, the external memory executes a corresponding read operation according to the read command sent by the physical layer 101.

The window control signal sequentially passes through the data strobe signal gating circuit 102 and the data strobe signal gating delay compensation circuit 103, and the signal passing through the data strobe signal gating delay compensation circuit 103 is used as the target window signal; among them, the data selection communication The number-gated delay compensation loop 103 includes a delay loop 1031 and a compensation path 1032. The compensation path 1032 is arranged between any two devices in the delay loop 1031, and the compensation path 1032 forms at least two delay paths through different impedance values; data selection The pass signal gating delay compensation circuit 103 is a circuit that is sent from the data strobe signal gating circuit 102 and returns to the data strobe signal gating. The circuit includes a delay circuit 1031 and a compensation path 1032, of which the compensation path 1032 It is set between any two devices in the delay loop 1031, and is specifically used to compensate the corresponding delay for the delay loop 1031, so as to adjust the delay of the window control signal passing through it, and obtain the corresponding target window signal.

The data strobe signal gating circuit 102 is used to adjust the position of the target window signal relative to the data strobe signal according to the target window signal and the data strobe signal.

In some embodiments, the physical layer 101 for sending a read command to the external memory may include:

The physical layer 101 is used to send a read command to an external memory through a first circuit; the first circuit includes a first input and output logic (InOut Logic, IOL) 11, a first input and output module (InOut Block, IOB) 12, and a first A pad (PAD) 13, the first input/output logic 11 is connected to the physical layer 101, and the first pad 13 is connected to an external memory.

In some embodiments, when the read operation of the external memory is completed, outputting the data strobe signal to the data strobe signal gating circuit 102 may include: when the read operation is completed, the external memory outputs the data strobe signal to the data selection communication through the second circuit. No. gate control circuit 102; the second circuit includes a second pad 23, a second input-output module 22, and a second input-output logic 21 connected in sequence. The second pad 23 is connected to an external memory, and the second input-output logic 21 and The data strobe signal gating circuit 102 is connected.

In some embodiments, the delay loop 1031 may include a third input-output logic 31, a third input-output module 32, a third pad 33, a fourth pad 43, a fourth input-output module 42, and a fourth input that are sequentially connected. Output logic 41, where the third input and output logic 31 and the fourth input and output logic 41 are respectively connected to both ends of the data strobe signal gating circuit 102; the compensation path 1032 is arranged in the delay loop 1031, and any two adjacent devices between.

Specifically, the compensation path 1032 may be provided between the third pad 33 and the fourth pad 43 in the delay loop 1031.

In some embodiments, the compensation path 1032 includes at least two sub-paths connected in parallel, and different impedances between the sub-paths form different delays. The compensation path 1032 may include four sub-paths connected in parallel, and the impedances of the sub-paths are 50%, 75%, 100%, and 120%, respectively.

In some embodiments, the compensation path 1032 includes at least one sub-path, and the impedance of the sub-path is adjustable. The two compensation paths 1032 are described above. One is to connect multiple sub-paths in parallel to achieve different delays by connecting different sub-paths according to the different impedances set in the sub-paths; the second is to pass Only one sub-path or more is set, the impedance of the sub-path is set to be adjustable, and different delays are realized by adjusting the magnitude of the impedance.

In some embodiments, the data strobe signal gating circuit 102 may include: a window generation module 1021 for converting parallel window control signals into serial window control signals. The window position adjustment module 1022 is used to adjust the position of the serial window control signal. The selection module (Multiplexer, MUX selection module) 1023 is used to select one of the target window control signal and the serial window control signal adjusted by the window position adjustment module 1022, and output it to the data strobe signal gate Control processing module (DQS GATE processing module) 1024. The data strobe signal gating processing module 1024 is used to perform a logical AND operation on the data strobe signal and the signal selected by the selection module 1023, and its output is the data strobe signal after gating and filtering, that is, the DQS_GATED signal.

In some embodiments, the selection module 1023 includes a two-input selector. The two-input selector is used to select one of the two input signals as the output; in this embodiment, the two-input selector can meet the selection requirements, of course, those skilled in the art can select other input options accordingly This embodiment does not limit it.

As a way, the first terminal of the window generation module 1021 is connected to the physical layer, the second terminal of the window generation module 1021 is connected to the window position adjustment module 1022, and the second terminal of the window position adjustment module 1022 is connected to the selection The first terminal of the module 1023 is connected to the third input/output logic 31 of the delay loop. In addition, the first terminal of the selection module 1023 is connected to the third input/output logic 31 of the delay loop, the second terminal of the selection module 1023 is connected to the fourth input/output logic 41 of the delay loop, and the third terminal of the selection module 1023 is connected Connect with the data strobe signal gating processing module 1024. At the same time, the first terminal of the data strobe signal gating processing module 1024 is connected to the third terminal of the selection module 1023, the first terminal of the data strobe signal gating processing module 1024 and the second input and output of the second circuit Logic 21 is connected.

An FPGA circuit provided according to this embodiment includes a physical layer, a data strobe signal gating circuit connected to the physical layer, and a data strobe signal gating delay compensation loop connected to the data strobe signal gating circuit; the physical layer Used to send the read command to the external memory, and at the same time send the window control signal to the data strobe signal gating circuit; when the read operation of the external memory is completed, output the data strobe signal to the data strobe signal gating circuit; the window control signals in turn After the data strobe signal gating circuit and the data strobe signal gating delay compensation circuit, the signal passing through the data strobe signal gating delay compensation loop is used as the target window signal; wherein the data strobe signal gating delay compensation loop includes The delay loop and the compensation channel. The compensation channel is arranged between any two devices in the delay loop, and the compensation channel forms at least two kinds of delay channels through different impedance values; the data strobe signal gating circuit is used according to the target window signal and the signal , Adjust the position of the target window signal relative to the data strobe signal. Therefore, by setting the compensation path in the delay compensation loop, the flexibility of delay compensation is improved, and the stability of the FPGA DDR interface is also improved.

Please refer to FIG. 2, this embodiment also provides an FPGA system. The FPGA system 20 includes a memory 21 and the FPGA circuit 10 of the above embodiment. The memory 21 receives a read command sent by the physical layer 101 in the FPGA circuit 10. And when the read operation is completed, the data strobe signal is output to the data strobe signal gating circuit 102.

Referring to FIG. 3, this embodiment also provides a circuit setting method, which is applied to the FPGA system described above. The FPGA system includes a memory and an FPGA circuit. The FPGA circuit includes a physical layer and a data strobe signal connected to the physical layer. The gating circuit, and the data strobe signal gating delay compensation loop connected to the data strobe signal gating circuit, the method includes: step S301 to step S304.

Step S301: The physical layer sends a read command to the external memory, and sends a window control signal to the data strobe signal gating circuit of the FPGA circuit.

Step S302: The window control signal sequentially passes through the data strobe signal gating circuit and the data strobe signal gating delay compensation circuit to obtain the target window signal.

Step S303: The external memory receives the read command sent by the physical layer, and outputs a data strobe signal to the data strobe signal gating circuit when the read operation is completed.

Step S304: The data strobe signal gating control circuit adjusts the position of the target window signal relative to the data strobe signal according to the target window signal and the data strobe signal.

Referring to FIG. 4, this embodiment also provides a computer-readable storage medium. The computer-readable storage medium 410 is included in a computer for storing information (such as computer-readable instructions, data structures, computer program modules, or other data). A volatile or nonvolatile, removable or non-removable medium implemented in any method or technology. The computer-readable storage medium 410 includes, but is not limited to, RAM (Random Access Memory), ROM (Read-Only Memory, read-only memory), EEPROM (Electrically Erasable Programmable read only memory), electrically erasable programmable read-only memory Storage), flash memory or other storage technology, CD-ROM (Compact Disc Read-Only Memory), digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage systems Or any other medium that can be used to store desired information and that can be accessed by a computer.

The computer-readable storage medium 410 in this embodiment may be used to store one or more computer programs 411, and the stored one or more computer programs 411 may be executed by a processor to implement the FPGA setting method in the foregoing embodiments.

This embodiment also provides a computer program 411 (or computer software). The computer program 411 may be distributed on a computer-readable medium and executed by a computer system to implement the FPGA setting method in the foregoing embodiments.

This embodiment also provides a computer program product, including a computer readable system, on which the computer program as shown above is stored. The computer-readable system in this embodiment may include the computer-readable storage medium shown above.

It can be seen that those skilled in the art should understand that all or some of the steps, systems, and functional modules/units in the methods disclosed above can be implemented as software (which can be implemented by computer program code executable by a computing system ), firmware, hardware and their appropriate combination. In hardware implementations, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may consist of several physical components. The components are executed cooperatively. Some physical components or all physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit .

In addition, as is well known to those of ordinary skill in the art, communication media usually contain computer-readable instructions, data structures, computer program modules, or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and may include any information delivery medium. Therefore, the present invention is not limited to any specific combination of hardware and software.

The above content is a further detailed description of the embodiments of the present invention in combination with specific implementations, and it cannot be considered that the specific implementations of the present invention are limited to these descriptions. For those of ordinary skill in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

An FPGA circuit comprising a physical layer, a data strobe signal gating circuit connected to the physical layer, and a delay compensation loop connected to the data strobe signal gating circuit;

The physical layer is used to send a read command to the external memory and at the same time send a window control signal to the data strobe signal gating circuit, so that the external memory outputs a data strobe signal to the data strobe signal when the read operation is completed. Data strobe signal gating circuit;

The window control signal sequentially passes through the data strobe signal gating circuit and the data strobe signal gating delay compensation circuit, and the signal passing through the data strobe signal gating delay compensation circuit is used as the target window signal; wherein, The data strobe signal gated delay compensation loop includes a delay loop and a compensation path, the compensation path is arranged between any two devices in the delay loop, and the compensation path forms at least two types of delays through different impedance values ’S access;

The data strobe signal gating circuit is used to adjust the position of the target window signal relative to the data strobe signal according to the target window signal and the data strobe signal.
The FPGA circuit of claim 1, further comprising a first circuit, the physical layer sends a read command to an external memory through the first circuit; the first circuit includes a first input and output connected in sequence Logic, a first input/output module, a first pad, the first input/output logic is connected to the physical layer, and the first pad is connected to the external memory.
The FPGA circuit according to claim 1, further comprising a second circuit for sending the data strobe signal fed back by the external memory when the read operation is completed to the data strobe Pass signal gating circuit.
The FPGA circuit of claim 3, wherein the second circuit comprises a second pad, a second input-output module, and a second input-output logic connected in sequence, and the second pad is connected to the external memory , The second input and output logic is connected with the data strobe signal gating circuit.
The FPGA circuit of claim 1, wherein the delay loop comprises a third input-output logic, a third input-output module, a third pad, a fourth pad, a fourth input-output module and A fourth input-output logic, wherein the third input-output logic and the fourth input-output logic are respectively connected to two ends of the data strobe signal gating circuit; the compensation path is arranged in any of the delay loops Between two adjacent devices.
8. The FPGA circuit of claim 5, wherein the compensation path is provided in the delay loop and is located between the third pad and the fourth pad.
The FPGA circuit according to any one of claims 1 to 6, wherein the compensation path includes at least two sub-paths connected in parallel, and different impedances between the sub-paths form different delays.
8. The FPGA circuit of claim 7, wherein the compensation path includes four sub-paths connected in parallel, and the impedances of the sub-paths are 50%, 75%, 100%, and 120%, respectively.
The FPGA circuit according to any one of claims 1 to 6, wherein the compensation path includes at least one sub-path, and the impedance of the sub-path is an adjustable impedance.
The FPGA circuit according to any one of claims 1 to 6, wherein the compensation path comprises a sub-path, and the impedance of the sub-path is adjustable impedance.
7. The FPGA circuit according to any one of claims 1 to 6, wherein the data strobe signal gating circuit comprises:

A window generating module for converting the parallel window control signal into a serial window control signal;

A window position adjustment module, used to adjust the position of the serial window control signal;

The selection module is configured to select one from the target window control signal and the serial window control signal adjusted by the window position adjustment module, and output it to the data strobe signal gating processing module;

The data strobe signal gating processing module is used to perform a logical AND operation on the data strobe signal and the signal selected by the selection module.
The FPGA circuit of claim 11, wherein the selection module includes a two-input selector.
The FPGA circuit of claim 12, wherein the two-input selector is used to select one of the two input signals as the output.
11. The FPGA circuit of claim 11, wherein the first terminal of the window generating module is connected to the physical layer, and the second terminal of the window generating module is connected to the window position adjustment module.
11. The FPGA circuit of claim 11, wherein the second terminal of the window position adjustment module is logically connected to the first terminal of the selection module and the third input and output of the delay loop.
The FPGA circuit of claim 11, wherein the first terminal of the selection module is logically connected to the third input and output of the delay loop, and the second terminal of the selection module is connected to the fourth terminal of the delay loop. The input and output are logically connected, and the third terminal of the selection module is connected to the data strobe signal gating processing module.
The FPGA circuit of claim 11, wherein the first terminal of the data strobe signal gating processing module is connected to the third terminal of the selection module, and the data strobe signal gating processing module The first terminal of is logically connected to the second input and output of the second circuit.
An FPGA system, comprising a memory and the FPGA circuit according to any one of claims 1-17, wherein the memory receives a read command sent by the physical layer in the FPGA circuit, and outputs data when the read operation is completed Strobe signal to data strobe signal gating circuit.
An FPGA circuit setting method, characterized by being applied to the FPGA system of claim 18, the method comprising:

The physical layer sends the read command to the external memory, and sends the window control signal to the data strobe signal gating circuit of the FPGA circuit;

The window control signal sequentially passes through the data strobe signal gating control circuit and the data strobe signal gating delay compensation loop to obtain the target window signal;

The external memory receives the read command sent by the physical layer, and outputs a data strobe signal to the data strobe signal gating circuit when the read operation is completed;

The data strobe signal gating circuit adjusts the position of the target window signal relative to the data strobe signal according to the target window signal and the data strobe signal.
A computer-readable medium, wherein the computer-readable storage medium stores program code, and the program code can be called by a processor to execute the method according to claim 19.