CN112731823A - FPGA interconnection line circuit and FPGA interconnection line delay reduction method - Google Patents

FPGA interconnection line circuit and FPGA interconnection line delay reduction method Download PDF

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CN112731823A
CN112731823A CN201911033728.3A CN201911033728A CN112731823A CN 112731823 A CN112731823 A CN 112731823A CN 201911033728 A CN201911033728 A CN 201911033728A CN 112731823 A CN112731823 A CN 112731823A
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positive feedback
feedback circuit
switch module
output
circuit
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王俊
温长清
张勇
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Shenzhen State Micro Electronics Co Ltd
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Shenzhen State Micro Electronics Co Ltd
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • G05B19/0423—Input/output
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/10—Plc systems
    • G05B2219/11—Plc I-O input output
    • G05B2219/1102—Speed up I-O manipulation

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  • Engineering & Computer Science (AREA)
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Abstract

The invention provides an FPGA (field programmable gate array) interconnection line circuit and an FPGA interconnection line delay reduction method, wherein the FPGA interconnection line circuit comprises a switch module, a positive feedback circuit and an output buffer, wherein the input end of the positive feedback circuit is connected with the output end of the switch module, and the output end of the positive feedback circuit is connected with the input end of the output buffer; the input end of the positive feedback circuit receives the signal output by the switch module, and the signal is output to the output buffer after being pulled up or pulled down; therefore, the invention can accelerate the signal output turnover speed, further achieve the purpose of reducing the interconnection line delay, reduce the delay occupied by the programmable interconnection module, optimize the performance of the programmable interconnection module to a certain extent and improve the speed of the whole chip.

Description

FPGA interconnection line circuit and FPGA interconnection line delay reduction method
Technical Field
The invention relates to the Field of FPGA (Field-Programmable Gate Array) design, in particular to an FPGA interconnection line circuit and an FPGA interconnection line delay reducing method.
Background
FPGAs are further developed based on Programmable devices such as PAL (Programmable Array Logic), GAL (general Array Logic), CPLD (Complex Programmable Logic Device), and the like. The Circuit is used as a semi-custom Circuit in the field of Application Specific Integrated Circuits (ASICs), not only overcomes the defects of the custom Circuit, but also overcomes the defect that the number of gate circuits of the original programmable device is limited.
Referring to fig. 1, a basic FPGA is composed of several parts: the programmable input/output IO module 101, the programmable logic module 103 and the programmable interconnection module 102, wherein the programmable input/output IO module 101 is used for connecting an external signal and the FPGA to realize communication between the FPGA and the outside, and various level standards can be realized according to requirements; the programmable logic module 103 is the basis for the FPGA to implement various logics, and usually uses LUT and flip-flop resources to implement various combinational logics and sequential logics; and the programmable interconnection module 102 is used for connecting various resources in the FPGA.
Therefore, the programmable interconnection module plays a role in bridging and is responsible for mutual communication among the logic modules and transmission of input and output signals among the interconnection modules, and therefore the programmable interconnection module is a part of vital resources in the FPGA device. However, as the process size is further reduced, the proportion of delay of the interconnection line is higher and higher, and each main signal of the FPGA device is transmitted through the interconnection line, so that the influence of the delay of the interconnection line on the speed of the FPGA is further increased, and the performance of the FPGA device is seriously influenced.
Disclosure of Invention
The invention aims to solve the main technical problem of providing an FPGA interconnection line circuit and an FPGA interconnection line time delay reduction method, and solves the problem of overlarge time delay of the existing interconnection line circuit.
In order to solve the above technical problem, the present invention provides an FPGA interconnect circuit, including:
the circuit comprises a switch module, a positive feedback circuit and an output buffer;
the input end of the positive feedback circuit is connected with the output end of the switch module, and the output end of the positive feedback circuit is connected with the input end of the output buffer.
Optionally, the positive feedback circuit includes a pull-up positive feedback circuit and a pull-down positive feedback circuit.
Optionally, the pull-up positive feedback circuit includes a first PMOS transistor and a first NMOS transistor, and the pull-down positive feedback circuit includes a second PMOS transistor and a second NMOS transistor;
the source electrode of the first PMOS tube is connected with a VDD end, the drain electrode of the first PMOS tube is connected with the output end of the switch NMOS tube, the grid electrode of the first PMOS tube is connected with the source electrode of the first NMOS tube, the grid electrode of the first NMOS tube is connected with the output end of the switch NMOS tube, and the drain electrode of the first NMOS tube is connected with a ground end GND;
the source electrode of the second PMOS tube is connected with a VDD end, the grid electrode of the second PMOS tube is connected with the output end of the switch NMOS tube, the drain electrode of the second PMOS tube is connected with the grid electrode of the second NMOS tube, the source electrode of the second NMOS tube is connected with the output end of the switch NMOS tube, and the drain electrode of the second NMOS tube is connected with a ground end GND.
Optionally, the interconnection line circuit further includes a control circuit, and the control circuit is connected to the switch module and controls the switch module to be turned on or turned off.
Optionally, the switch module includes a first-stage NMOS transistor and a second-stage NMOS transistor, the first-stage NMOS transistor and the second-stage NMOS transistor are connected in series, and the switch module is connected to the gate of the first-stage NMOS transistor and the gate of the second-stage NMOS transistor respectively.
Optionally, the control circuit includes two NMOS tubes and a phase inverter module, where the phase inverter module is disposed between the two NMOS tubes and is respectively connected to the two NMOS tubes;
the grid electrodes of the two NMOS tubes are connected with an ADDR end, and one end of the phase inverter module is connected with the grid electrode of the first-stage NMOS tube and the grid electrode of the second-stage NMOS tube.
In order to solve the above problems, the present invention further provides a method for reducing delay of an FPGA interconnection line, including:
the input end of the positive feedback circuit receives a signal output by the switch module;
and the positive feedback circuit pulls up or pulls down the signal and outputs the signal to an output buffer.
Optionally, the step of outputting the signal to an output buffer after the positive feedback circuit pulls up or pulls down the signal includes:
when an input signal is turned from 0 to VDD, the signal is pulled up through the positive feedback circuit and then the VDD is output;
when the input signal is inverted from VDD to 0, the signal is pulled down through the positive feedback circuit and then is output to GND.
Optionally, the method for reducing delay of the FPGA interconnection line further includes:
when the switch module is in a closed state, the positive feedback circuit is pulled to a high potential or a low potential.
Optionally, before the input end of the positive feedback circuit receives the signal output by the switch module, the method further includes:
judging whether the voltage value at the connection part of the control circuit and the switch module is a high level or not;
and if so, the control circuit controls the switch module to be conducted for signal transmission.
The invention has the beneficial effects that:
the invention provides an FPGA (field programmable gate array) interconnection line circuit and an FPGA interconnection line delay reduction method, wherein the FPGA interconnection line circuit comprises a switch module, a positive feedback circuit and an output buffer, wherein the input end of the positive feedback circuit is connected with the output end of the switch module, and the output end of the positive feedback circuit is connected with the input end of the output buffer; the input end of the positive feedback circuit receives the signal output by the switch module, and the signal is output to the output buffer after being pulled up or pulled down; therefore, the invention can accelerate the signal output turnover speed, further achieve the purpose of reducing the interconnection line delay, reduce the delay occupied by the programmable interconnection module, optimize the performance of the programmable interconnection module to a certain extent and improve the speed of the whole chip.
Additional features and corresponding advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
FIG. 1 is a schematic diagram of a general structure of an FPGA;
FIG. 2 is a diagram of a generic programmable interconnect structure;
FIG. 3 is a schematic diagram of a general programmable interconnect circuit;
fig. 4 is a schematic diagram of an FPGA interconnect circuit structure according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a control circuit according to an embodiment of the present invention;
fig. 6 is a schematic flowchart of a method for reducing delay of an FPGA interconnection line according to a second embodiment of the present invention;
fig. 7 is a schematic diagram of a working flow of a control circuit according to a second embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The interconnection line bridges the programmable input/output IO module and the programmable logic module in the FPGA device, so the transmission speed of the interconnection line determines whether the whole system can rapidly complete the design customized by a user to a certain extent. For the programmable interconnect module, which generally has a two-layer structure, specifically, as shown in fig. 2, the programmable interconnect module is substantially a MUX (multiplexer) array module, and the MUX inside the programmable interconnect module implements a programmable function, and in order to ensure the signal strength, a buffer may exist inside the MUX to strengthen the signal strength. As shown in fig. 2, 1 represents a first layer and 2 represents a second layer. The primary function of the first layer is to ensure communication between the programmable interconnect modules 102. The second layer 2 serves to ensure that signals from the programmable interconnect module are transmitted to the programmable logic module 103. The first layer includes two types of MUXs, 11 and 12 respectively, 11 being input sources of another programmable interconnect module or an output of a programmable logic module; 11 may be output directly to another programmable interconnect module or may be input to 21 via 12, an intermediate MUX, and finally input to programmable logic module 103 via 21.
Referring to fig. 3, fig. 3 is a schematic diagram of a general programmable interconnect circuit, in which a MUX is formed by two stages of switch NMOS transistors connected in series, and the output of the NMOS transistor is output to the input of another MUX through a restorer and an output buffer.
In order to solve the problem of overlarge delay of the existing interconnection line circuit, the FPGA interconnection line circuit comprises a switch module, a positive feedback circuit and an output buffer, wherein the input end of the positive feedback circuit is connected with the output end of the switch module, and the output end of the positive feedback circuit is connected with the input end of the output buffer; the input end of the positive feedback circuit receives the signal output by the switch module, and the signal is output to the output buffer after being pulled up or pulled down, so that the loss of threshold voltage can be avoided, and the time delay of the interconnection line can be reduced. The present invention will be described in further detail with reference to the following detailed description and accompanying drawings.
The first embodiment is as follows:
the FPGA interconnect circuit provided by this embodiment includes: the circuit comprises a switch module, a positive feedback circuit and an output buffer; the input end of the positive feedback circuit is connected with the output end of the switch module, and the output end of the positive feedback circuit is connected with the input end of the output buffer.
In this embodiment, the positive feedback circuit includes a pull-up positive feedback circuit and a pull-down positive feedback circuit, where the pull-up positive feedback circuit is configured to pull up a signal to a high level, and the pull-down positive feedback circuit is configured to pull down the signal to a low level.
In this embodiment, the pull-up positive feedback circuit includes a first PMOS transistor and a first NMOS transistor, and the pull-down positive feedback circuit includes a second PMOS transistor and a second NMOS transistor, specifically, as shown in fig. 4, the first PMOS transistor is MP1, the second PMOS transistor is MP2, the first NMOS transistor is MN1, and the second NMOS transistor is MN 2; the MP1, the MP2, the MN1 and the MN2 respectively comprise three ends which are respectively a source electrode, a drain electrode and a grid electrode, the pull-up positive feedback circuit comprises a circuit consisting of the MP1 and the MN1, the source electrode of the MP1 is connected with a VDD end, the drain electrode of the MP1 is connected with the output end of the switch module, the grid electrode of the MP1 is connected with the source electrode of the MN1, the grid electrode of the MN1 is connected with the output end of the switch module, and the drain electrode of the MN1 is connected with a grounding end GDN; the pull-down positive feedback circuit comprises a circuit consisting of MP2 and MN2, wherein the source of MP2 is connected with a VDD end, the grid of MP2 is connected with the output end of the switch module, the drain of MP2 is connected with the grid of MN2, the output end of the source of MN2 is connected with the output end of the switch module, and the drain of MN2 is connected with a ground end GND.
Here, VDD is an operating voltage.
It should be understood that the programmable interconnect module is substantially a MUX array module, and the switch module can be used as a MUX, the drain of MP1 and the source of MN2 are connected to the output terminal of the MUX, the gate of MN1 and the gate of MP2 are connected to the output terminal of the MUX, the source of MN1 is connected to the gate of MP1, the source of MP2 is connected to the gate of MN2, the sources of MP1 and MP2 are connected to VDD, and the drains of MN1 and MN2 are connected to GND.
In this embodiment, when the MUX does not operate, the output terminal of the MUX is pulled up to a high level by the positive feedback loop of the pull-up positive feedback circuit, or pulled down to a low level by the positive feedback loop of the pull-down positive feedback circuit, so that the static power consumption of the post-stage circuit can be reduced.
In this embodiment, the switch module includes a first-stage NMOS transistor and a second-stage NMOS transistor, the first-stage NMOS transistor and the second-stage NMOS transistor are connected in series, and the first-stage NMOS transistor and the second-stage NMOS transistor constitute a preceding-stage NMOS switch transistor, specifically, as shown in fig. 4, the first-stage NMOS transistor is composed of 12 NMOS transistors, which are MN3 to MN 14; the second-stage NMOS transistor comprises 3 NMOS transistors, namely MN 15-MN 17, the drains of MN 3-MN 6 are connected with the source of MN15, the drains of MN 7-MN 10 are connected with the source of MN16, the drains of MN 11-MN 14 are connected with the source of MN17, and the drains of MN 15-MN 17 are output ends of the preceding-stage NMOS switching transistor.
It should be noted that the number of the first-stage NMOS transistors, the number of the second-stage NMOS transistors, and the serial connection manner in this embodiment are only used to illustrate the present invention, and are not used to limit the present invention.
Specifically, when the front-stage NMOS switching tube works and an input signal is inverted from 0 to VDD, the MUX output terminal can only be charged to VDD-2VTH, but through the positive feedback effect of MN1 and MP1, the output terminal does not have threshold loss when outputting a high level, and can output VDD quickly; when the input signal is inverted from VDD to 0, the output end can only be discharged to 2VTH, but the threshold value is not increased when the output end outputs low level through the positive feedback effect of MP2 and MN2, and one GND can be rapidly output. In the mode, because the slow pull-up and pull-down process of the traditional circuit is not used, the time delay of the MUX is reduced, the performance of the programmable interconnection module is optimized, and the speed of the whole chip is improved.
VTH is a turn-on voltage.
In this embodiment, the FPGA interconnection line circuit further includes a control circuit, and the control circuit is connected to the switch module and controls the switch module to be turned on or turned off. Specifically, as shown in fig. 5, the control circuit includes two NMOS transistors and an inverter module, the two NMOS transistors are MN18 and MN19, the inverter module is disposed between MN18 and MN19 and connected to MN18 and MN19, the inverter module includes an inverter I3 and an inverter I4, and the inverter I3 and the inverter I4 are connected in parallel; the gates of MN18 and MN19 are connected with the ADDR end, the drain of MN18 is connected on a parallel line of an inverter I3 and an inverter I4, the source of MN19 is connected on a parallel line of an inverter I3 and an inverter I4, the inverter I4 is provided with two ends which are a q end and a qb end respectively, and the q end is connected with the gates of MN 3-MN 17 of the MUX.
In this embodiment, the power domain of the control circuit is different from the power domains at other places of the interconnection line, the power voltage value of the control circuit is slightly higher than the power voltage at other places, when ADDR is high, MN18 and MN19 are turned on, the q terminal and the qb terminal output the data and datan values respectively, and the high potential of the q terminal is also different from the power voltage of MUX due to the difference of the power domains. For the preceding NMOS switching tube, the grid voltage is higher, and the NMOS tube is conducted faster, so that the conduction of the switching NMOS tube is accelerated by increasing the grid voltage value of the preceding NMOS switching tube, and the time delay is reduced.
The FPGA interconnection circuit provided by the embodiment comprises a switch module, a positive feedback circuit and an output buffer; the input end of the positive feedback circuit is connected with the output end of the switch module, the output end of the positive feedback circuit is connected with the input end of the output buffer, the voltage recovery is accelerated through the pull-up or pull-down of the positive feedback circuit, the time delay is reduced, and the speed of the whole circuit is increased; the FPGA interconnection circuit is also provided with control circuits in other power domains to control the preceding NMOS switching tube, the conduction of the switching NMOS tube is accelerated by increasing the grid voltage value of the preceding NMOS switching tube, and the time delay is further reduced, so that the performance of the programmable interconnection module is optimized, and the speed of the whole chip is improved.
Example two:
on the basis of the FPGA interconnection line circuit provided in the above embodiment, the embodiment provides a method for reducing delay of an FPGA interconnection line, as shown in fig. 6, and the specific steps include:
s601, receiving a signal output by a switch module at the input end of a positive feedback circuit;
in this embodiment, the positive feedback circuit includes a pull-up positive feedback circuit and a pull-down positive feedback circuit, the pull-up positive feedback circuit is configured to pull up a signal to a high level, and the pull-down positive feedback circuit is configured to pull down the signal to a low level; the pull-up positive feedback circuit comprises a circuit consisting of MP1 and MN1, wherein the source electrode of MP1 is connected with a VDD end, the drain electrode of MP1 is connected with the output end of the switch module, the grid electrode of MP1 is connected with the source electrode of MN1, the grid electrode of MN1 is connected with the output end of the switch module, and the drain electrode of MN1 is connected with a grounding end GDN; the pull-down positive feedback circuit comprises a circuit consisting of MP2 and MN2, wherein the source of MP2 is connected with a VDD end, the grid of MP2 is connected with the output end of the switch module, the drain of MP2 is connected with the grid of MN2, the output end of the source of MN2 is connected with the output end of the switch module, and the drain of MN2 is connected with a ground end GND.
In this embodiment, the switch module includes a first-stage NMOS transistor and a second-stage NMOS transistor, the first-stage NMOS transistor and the second-stage NMOS transistor are connected in series, and the first-stage NMOS transistor and the second-stage NMOS transistor form a preceding-stage NMOS switch transistor.
And S602, the positive feedback circuit pulls up or pulls down the input signal and outputs the signal to the output buffer.
In this embodiment, the working state of the positive feedback circuit has two states, one is that the pull-up MUX outputs high level, and the other is that the pull-down MUX outputs low level.
In this embodiment, when an input signal is inverted from 0 to VDD, the signal is pulled up by the positive feedback circuit and then VDD is output; specifically, when the front-stage NMOS switching tube works and an input signal is inverted from 0 to VDD, the MUX output terminal can only be charged to VDD-2VTH, but through the positive feedback effect of MN1 and MP1, the output terminal does not have threshold loss when outputting a high level, and can output VDD quickly; when an input signal is inverted from VDD to 0, the signal is pulled down through the positive feedback circuit and then outputs GND, specifically, when the input signal is inverted from VDD to 0, an output end can only be discharged to 2VTH, but through the positive feedback effect of MP2 and MN2, a threshold value is not increased when the output end outputs a low level, and one GND can be quickly output.
The output VDD or GND can be output to the input of other MUXs through the output buffer, the loss of threshold voltage cannot be caused, and the delay of the interconnection line circuit is reduced through the pull-up or pull-down of the positive feedback circuit.
In this embodiment, the control circuit controls the switch module to be turned on or off, that is, the control circuit controls the working state or the off state of the preceding-stage NMOS switching tube, specifically referring to fig. 6, the method includes the following steps:
s701, judging whether a voltage value at the connection position of the control circuit and the switch module is a high level or not; if yes, executing S602, if no, executing S603;
s702, the control circuit controls the switch module to be conducted and carries out signal transmission;
and S703, the switch module is in a closed state.
The power domain of the control circuit is different from the power domains of other places of the interconnection line, the power voltage value of the control circuit is slightly higher than the power voltage of other places, and the high potential of the q end is also different from the power voltage of the MUX due to the difference of the power domains. For the preceding NMOS switching tube, the grid voltage is higher, and the NMOS tube is conducted faster, so that the conduction of the switching NMOS tube is accelerated by increasing the grid voltage value of the preceding NMOS switching tube, and the time delay is reduced.
In this embodiment, when the MUX does not operate, the output terminal of the MUX is pulled up to a high level by the positive feedback loop of the pull-up positive feedback circuit, or pulled down to a low level by the positive feedback loop of the pull-down positive feedback circuit, so that the static power consumption of the post-stage circuit can be reduced.
According to the FPGA interconnection line delay shortening method, the input end of the positive feedback circuit receives a signal output by the switch module, the signal is output to the output buffer after being pulled up or pulled down, the preceding-stage NMOS switch tube is controlled by the control circuit in other power domains, the conduction of the switch NMOS tube is accelerated by increasing the grid voltage value of the preceding-stage NMOS switch tube, the delay is reduced, the speed of the whole circuit is accelerated, and the performance of the programmable interconnection module is optimized.
Example three:
the FPGA interconnection circuit has universality, does not need any special unit structure for which FPGA device, and only needs to design a positive feedback circuit on the interconnection circuit. Specific interconnection circuits participate in the above embodiments, and are not described herein.
Aiming at the problem of overlarge delay of the existing interconnection line circuit, the FPGA interconnection line circuit is provided with the positive feedback circuit, the input end of the positive feedback circuit receives a signal output by the switch module, and the signal is output to the output buffer after being pulled up or pulled down; the method can realize the purpose of accelerating the turning speed of signal output, further reducing the delay of interconnection lines, reducing the delay occupied by the programmable interconnection module, optimizing the performance of the programmable interconnection module to a certain extent and improving the speed of a whole chip.
The foregoing is a more detailed description of the present invention that is presented in conjunction with specific embodiments, and the practice of the invention is not to be considered limited to those descriptions. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims (10)

1. An FPGA interconnection circuit is characterized by comprising a switch module, a positive feedback circuit and an output buffer;
the input end of the positive feedback circuit is connected with the output end of the switch module, and the output end of the positive feedback circuit is connected with the input end of the output buffer.
2. The FPGA interconnect line circuit of claim 1, wherein said positive feedback circuit comprises a pull-up positive feedback circuit and a pull-down positive feedback circuit.
3. The FPGA interconnect circuit of claim 2, wherein the pull-up positive feedback circuit comprises a first PMOS transistor and a first NMOS transistor, and the pull-down positive feedback circuit comprises a second PMOS transistor and a second NMOS transistor;
the source electrode of the first PMOS tube is connected with a VDD end, the drain electrode of the first PMOS tube is connected with the output end of the switch module, the grid electrode of the first PMOS tube is connected with the source electrode of the first NMOS tube, the grid electrode of the first NMOS tube is connected with the output end of the switch module, and the drain electrode of the first NMOS tube is connected with a ground end GND;
the source electrode of the second PMOS tube is connected with a VDD end, the grid electrode of the second PMOS tube is connected with the output end of the switch module, the drain electrode of the second PMOS tube is connected with the grid electrode of the second NMOS tube, the source electrode of the second NMOS tube is connected with the output end of the switch module, and the drain electrode of the second NMOS tube is connected with a ground end GND.
4. The FPGA interconnect circuit of claim 1, further comprising a control circuit coupled to the switch module and controlling the switch module to open or close.
5. The FPGA interconnect circuit of claim 4, wherein the switch module comprises a first stage NMOS transistor and a second stage NMOS transistor, the first stage NMOS transistor and the second stage NMOS transistor being connected in series, the switch module being connected to a gate of the first stage NMOS transistor and a gate of the second stage NMOS transistor, respectively.
6. The FPGA interconnect circuit of claim 5, wherein said control circuit comprises two NMOS transistors and an inverter module disposed between and connected to said two NMOS transistors, respectively;
the grid electrodes of the two NMOS tubes are connected with an ADDR end, and one end of the phase inverter module is connected with the grid electrode of the first-stage NMOS tube and the grid electrode of the second-stage NMOS tube.
7. A delay shortening method for FPGA interconnection lines is characterized by comprising the following steps:
the input end of the positive feedback circuit receives a signal output by the switch module;
and the positive feedback circuit pulls up or pulls down the signal and outputs the signal to an output buffer.
8. The FPGA interconnect delay shortening method of claim 7, wherein the outputting the signal to an output buffer after the positive feedback circuit performs a positive feedback function comprises:
when an input signal is turned from 0 to VDD, the signal is pulled up through the positive feedback circuit and then the VDD is output;
when the input signal is inverted from VDD to 0, the signal is pulled down through the positive feedback circuit and then is output to GND.
9. The FPGA interconnect delay shortening method of claim 7, further comprising:
when the switch module is in a closed state, the positive feedback circuit is pulled to a high potential or a low potential.
10. The FPGA interconnect delay shortening method of claim 7, wherein said positive feedback circuit input further comprises, prior to receiving a signal output by a switch module:
judging whether the voltage value at the connection part of the control circuit and the switch module is a high level or not;
and if so, the control circuit controls the switch module to be conducted and transmits signals.
CN201911033728.3A 2019-10-28 2019-10-28 FPGA interconnection line circuit and FPGA interconnection line delay reduction method Pending CN112731823A (en)

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