CN101510776A

CN101510776A - FPGA wiring and programmable switch structure

Info

Publication number: CN101510776A
Application number: CNA2009100585635A
Authority: CN
Inventors: 李平; 黄国辉; 丛伟林; 郑博文; 苏世碧; 李文昌
Original assignee: CHENGDU SINO MICROELECTRONICS SYSTEM Co Ltd
Current assignee: CHENGDU SINO MICROELECTRONICS SYSTEM Co Ltd
Priority date: 2009-03-11
Filing date: 2009-03-11
Publication date: 2009-08-19

Abstract

The invention discloses an FPGA wiring programmable switch structure and relates to the technology of integrated circuit. The switch structure comprises a configuration circuit, a first SRAM and an MOS switch, the MOS switch is connected with a point (L1) and a point (L2). The switch structure is characterized by also comprising a buffer circuit connected with the MOS switch in parallel; one end of the buffer circuit is connected with point (L1) while the other end thereof is connected with point (L2), and the control end of the buffer circuit is connected with the configuration circuit by a second SRAM. The programmable switch structure has the advantages that under the condition that time sequence can not meet the requirements, PIP constraint is added to constrain the PIP type of a key path so as to significantly improve the time sequence features of wiring.

Description

The FPGA wiring and programmable switch structure

Technical field

The present invention relates to integrated circuit technique.

Background technology

FPGA mainly is made of a large amount of programmable logic cells, input-output unit and interconnection resource.Fig. 1 is the syndeton of logical block and adjacent switch matrix.The switch matrix of covering logic structure provides general interconnection for the wiring of the molecule on the entire device.Be divided into three types according to different length of arrangement wire: single long line, two long line, six double-length lines and long line.The level of different long lines has been connected alteration switch box array with the grid that vertically is interwoven, the switch enclosure array comprises several programmable switch artiss PIP.PIP unlatching or closing state by the decision of the content of SRAM in the programmable storage.By PIP is carried out Programming Design, determined the break-make of signal routing.

Under present process conditions, wiring delay has substantially exceeded gate delay, makes that the delay of critical path is always because the long institute of wiring causes in the common design.In order to solve the excessive problem of wiring delay, the modification that the designer has to repeatedly designs, and often for a critical path has prolonged the design cycle, even causes the design failure.

In Fig. 1, the cross-coupled part of various interconnection resources is exactly tie point PIP able to programme, among Fig. 1 shown in the black round dot.Traditional PIP structure is to utilize common nmos switch or cmos switch to form.Fig. 2 has shown common PIP transmitting switch.Utilize PIP structure shown in Figure 2 can realize the wire interconnects of any direction, but in some design,, can only remodify design, till satisfying temporal constraint in case the wiring delay in a certain path can not satisfy the sequential requirement of design.Along with the scale of circuit design is increasing, sequential requires also more and more harsher.The time sequence modification of a large-scale Design of Digital Circuit is very difficult, and the designer usually because a certain timing path can not meet the demands and constantly modification design, has prolonged the design cycle.

Summary of the invention

Technical problem to be solved by this invention is, a kind of FPGA wiring and programmable switch structure is provided, and can programme as required, improves the sequential requirement on the basis of not revising original design.

The technical scheme that the present invention solve the technical problem employing is, the FPGA wiring and programmable switch structure, comprise configuration circuit, a SRAM and MOS switch, MOS switch tie point L1 and L2, also comprise buffer circuits with the MOS switch in parallel, buffer circuits one tip node L1, other end contact L2, the control end of buffer circuits is connected with configuration circuit by the 2nd SRAM.

Described buffer circuits comprises buffer two parallel connections, that direction is opposite; The input contact L1 of a buffer, output contact L2, two control ends meet a SRAM and the 2nd SRAM respectively; The output contact L1 of another buffer B2, input contact L2, two control ends meet a SRAM and the 2nd SRAM respectively.Described MOS switch is a nmos switch.

Described buffer is made of the metal-oxide-semiconductor of NAND gate, NOR gate and two series connection, and an input of NAND gate is as a control end of buffer, and an input of another input of NAND gate and NOR gate links to each other, as the data input pin of buffer; Another input of NOR gate is as another control end of buffer; The grid of the output termination inverter PMOS pipe of NAND gate, the grid of the output termination inverter NMOS pipe of NOR gate, the tie point of PMOS pipe and NMOS pipe is as the output of buffer.

The invention has the beneficial effects as follows, under the situation that sequential can not meet the demands, add the PIP constraint, retrain the PIP type of critical path, can obviously improve the temporal characteristics of wiring, particularly, do not need to change the design input.

The present invention is further illustrated below in conjunction with accompanying drawing and background technology.

Description of drawings

Fig. 1 is the connection diagram of logical block and adjacent switch matrix.

Fig. 2 is general PIP structural representation, and a is the CMOS structure, and b is the NMOS structure.

Fig. 3 is a structural representation of the present invention.

Fig. 4 is the structure chart of buffer of the present invention.

Embodiment

Some environment for use of FPGA requires very harsh to the transmission delay of some critical path signals, must have precedence over the input that clock signal arrives trigger as the signal of critical path, with avoid occurring signal settling time deficiency problem.But in the design of at a high speed large-scale digital system, usually to grow Distance Transmission and cause signal when clock signal is effective, not to be ready in advance owing to the signal of critical path, cause signal can not satisfy the requirement of settling time, the metastable state situation occurs.The equivalence in transmission path of common nmos switch is a transmission resistance.Under actual conditions, NMOS transmission resistance, conductor resistance and lead capacitance have determined the size of signal delay, and the length of lead has determined the equivalent resistance and the equivalent capacity of lead.

In general, the size of lead time-delay and square relation in direct ratio of conductor length, therefore, the length that reduces transfer wire can reduce the time-delay of transmission signals greatly.Because square being directly proportional of transmission delay and conductor length, the present invention adds buffer in the middle of lead, longly be the lead of the L lead that to be divided into two length be L/2 with one, even additionally increased the gate delay of buffer, but because the gate delay of buffer can effectively reduce the transmission delay of signal so greatly less than the transmission line time-delay.

Embodiments of the invention are as follows:

FPGA wiring and programmable switch structure of the present invention, comprise configuration circuit, a SRAM and MOS switch, MOS switch tie point L1 and L2, also comprise buffer circuits with the MOS switch in parallel, buffer circuits one tip node L1, other end contact L2, the control end of buffer circuits is connected with configuration circuit by the 2nd SRAM.

Described buffer circuits comprises buffer B1, B2 two parallel connections, that direction is opposite; The input contact L1 of buffer B1, output contact L2, two control ends meet a SRAM and the 2nd SRAM respectively; The output contact L1 of buffer B2, input contact L2, two control ends meet a SRAM and the 2nd SRAM respectively.

Described MOS switch is a nmos switch.

The PIP transmission node of Fig. 3 is made of a nmos switch, two buffer B1 and B2, to satisfy different directions, the design requirement of different temporal constraints.Configuration circuit is configured in switching signal S in the SRAM memory cell, and the switching signal of buffer is OE and S.When S is high level, adopt common transmission path; When S is low level and OE when being high level, then utilize the buffer transmission signals.Based on this kind PIP structure, make in the design of some sequential harshnesses, if common nmos switch can not make wiring satisfy temporal constraint, then utilize B1 or B2 buffer to improve the routing path sequential.Simultaneously, B1 and B2 constitute loop structure, have guaranteed the correctness of level transmissions.The structure of buffer B1 or B2 as shown in Figure 4.

In the buffer structure of Fig. 4, the data input is divided into two-way, one the tunnel outputs to the grid level of inverter PMOS pipe with OE by NAND gate, and other one tunnel input and S signal output to the grid level of inverter NMOS pipe by NOR gate, and final data is from the drain electrode output of inverter.

Based on this invention technology, when design,, can solve sequential and require harsh design by corresponding steps.FPGA design generally comprises five general big steps: design input, design integration and functional verification, gate leve comprehensively, placement-and-routing, timing verification.In common design, if sequential can not meet the demands, the designer must design input again and revise, and again layout is connected up.But,, under the situation that sequential can not meet the demands,, can improve the temporal characteristics of wiring by the PIP type of constraint critical path based on the PIP structure of this invention technology.

Claims

1, FPGA wiring and programmable switch structure, comprise configuration circuit, a SRAM and MOS switch, MOS switch tie point (L1) and (L2), it is characterized in that, also comprise buffer circuits with the MOS switch in parallel, buffer circuits one tip node (L1), other end contact (L2), the control end of buffer circuits is connected with configuration circuit by the 2nd SRAM.

2, FPGA wiring and programmable switch structure as claimed in claim 1 is characterized in that, described buffer circuits comprises buffer two parallel connections, that direction is opposite (B1), (B2); The input contact (L1) of buffer (B1), output contact (L2), two control ends meet a SRAM and the 2nd SRAM respectively; The output contact (L1) of buffer (B2), input contact (L2), two control ends meet a SRAM and the 2nd SRAM respectively.

3, FPGA wiring and programmable switch structure as claimed in claim 1 is characterized in that, described MOS switch is a nmos switch.

4, FPGA wiring and programmable switch structure as claimed in claim 1, it is characterized in that, described buffer is made of the metal-oxide-semiconductor of NAND gate, NOR gate and two series connection, an input of NAND gate is as a control end of buffer, an input of another input of NAND gate and NOR gate links to each other, as the data input pin of buffer; Another input of NOR gate is as another control end of buffer; The grid of the output termination inverter PMOS pipe of NAND gate, the grid of the output termination inverter NMOS pipe of NOR gate, the tie point of PMOS pipe and NMOS pipe is as the output of buffer.