CN203968107U - Multichannel final election device - Google Patents
Multichannel final election device Download PDFInfo
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- CN203968107U CN203968107U CN201420397088.0U CN201420397088U CN203968107U CN 203968107 U CN203968107 U CN 203968107U CN 201420397088 U CN201420397088 U CN 201420397088U CN 203968107 U CN203968107 U CN 203968107U
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- inverter
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Abstract
The utility model relates to a kind of multichannel final election device, and multichannel final election device comprises that M inverter, the N M with control bit selects 1 Port Multiplier; A described N M selects i input parallel connection of 1 Port Multiplier, then is connected with the output of i the described inverter with control bit, and wherein N, M are integer, the exponential that M is 2, and i=1,2 ..., M; In the time that described control bit is the first level, described inverter with control bit output high-impedance state, in the time that i control bit is second electrical level, the individual described inverter with control bit of described i is opened, and N M selects 1 Port Multiplier described in gating.A kind of multichannel final election device that the utility model provides is applied to fpga chip, and the distortion of anti-stop signal long-distance transmissions makes signal output keep complete linearity, has reduced power consumption simultaneously.
Description
Technical field
The utility model relates to integrated circuit (IC) design field, is specifically related to multichannel final election device.
Background technology
Field programmable gate array (Field-Programmable Gate Array, FPGA), it is the product further developing on the basis of the programming devices such as PAL, GAL, CPLD.It occurs as a kind of semi-custom circuit in application-specific integrated circuit (ASIC) field, has both solved the deficiency of custom circuit, has overcome again the limited shortcoming of original programming device gate circuit number.
For fpga chip, because its area of 80% is interconnection structure, therefore interconnection structure is the critical function module of FPGA, for realize circuit function, improve circuit performance there is important effect.Interconnection structure is made up of multichannel final election device, and Fig. 1 is that in prior art, a multichannel final election device drives the data channel of other three multichannel final election devices to simplify circuit structure diagram, and its weak point is:
(1) as shown in Figure 1 in the time that the output of a multichannel final election device connects three loads, because of the resistance value (R1 of the metal wire before load, R2, R3) from tens ohm to hundreds of ohm difference, prime of the prior art drives and will connect the PMOS pipe in the maintenance logical zero circuit in load by transmission gate, PMOS pipe is equivalent to a pull-up resistor in effect, the resistance of the metal wire before this PMOS pipe and load forms dividing potential drop, pull-up resistor is stronger, the time delay of signal is also just larger, and then has influence on the long-distance transmissions of signal;
(2) as shown in Figure 1, the output of a multichannel final election device connects 32 inputs, and 1 input represents a fan-out, and these 32 inputs are exactly 32 fan-outs.Can open 1 input, 2 inputs, reach at most 32 inputs.The input of opening is more, fan-out is just more, can be along with fanout object difference from the sequential that is input to output, when the signal of each fan-out becomes 1 from 0, the PMOS pipe of inverter drive is equivalent to a pull-up resistor in effect, fan-out is more, pull-up resistor in parallel is stronger, dead resistance dividing potential drop on metal wire before pull-up resistor meeting and load, pull-up resistor is stronger, the time delay of signal is also just larger, when pull-up resistor is less than metal wire resistance, signal just can not transmit, from a fan-out, to 32 fan-outs, the value of time delay is not that equal proportion changes, when fan-out is more, large many of time delay meeting.Signal keeps complete linearity is that number and time of delay of load is proportional, when the value of time delay is not that equal proportion makes signal output be difficult to the linearity that keeps complete when changing.
(3) in the time that fan-out number is larger, large from the physical distance of load because driving, the resistance of metal wire is very huge, add pull-up resistor in load cause the rising edge of signal and trailing edge more slow, the time of intermediate state can increase, and electric leakage can increase and causes power consumption larger.
Utility model content
The purpose of this utility model is to be to solve above-mentioned weak point of the prior art, and a kind of multichannel final election device is provided.Be applied to fpga chip, anti-stop signal transmission distortion, makes signal output keep complete linearity, has reduced power consumption simultaneously.
For achieving the above object, the utility model provides a kind of multichannel final election device, and multichannel final election device comprises that M inverter, the N M with control bit selects 1 Port Multiplier;
A described N M selects i input parallel connection of 1 Port Multiplier, then is connected with the output of i the described inverter with control bit, and wherein N, M are integer, the exponential that M is 2, and i is 1,2 ..., M;
In the time that described control bit is the first level, described inverter with control bit output high-impedance state, in the time that i control bit is second electrical level, the individual described inverter with control bit of described i is opened, and N M selects 1 Port Multiplier described in gating.
Preferably, described M selects 1 Port Multiplier to be specially 64 and selects 1 Port Multiplier; Described 64 select 1 Port Multiplier to comprise that 8 select 1 Port Multiplier, a P type metal-oxide-semiconductor P1, the 2nd P type metal-oxide-semiconductor P2, inverter D0;
The output that in the first order each 8 selected 1 Port Multiplier selects the input of 1 Port Multiplier to be connected with in the second level one 8 respectively, one 8 input that selects the drain electrode of the output of 1 Port Multiplier, a described P type metal-oxide-semiconductor P1 and the drain electrode of described the 2nd P type metal-oxide-semiconductor P2 to be connected to described inverter D0 in the described second level, the grid input initialize signal of a described P type metal-oxide-semiconductor P1, the source electrode of the source electrode of the one P type metal-oxide-semiconductor P1 and the 2nd P type metal-oxide-semiconductor P2 joins and connects power supply, and the grid of described the 2nd P type metal-oxide-semiconductor P2 is connected with the output of described inverter D;
When described initialize signal init is second electrical level, when the input of inverter D0 is the first level, the output of inverter D0 is second electrical level, the drain electrode of the one P type metal-oxide-semiconductor P1 is high-impedance state, the input of inverter D0 can be given and is pulled to the first level by the 2nd P type metal-oxide-semiconductor P2,64 do not select 1 Port Multiplier described in gating, in the time that described initialize signal init is the first level, described in gating, 64 select 1 Port Multiplier.
A kind of multichannel final election device that the utility model provides is applied to fpga chip, and the distortion of anti-stop signal long-distance transmissions makes signal output keep complete linearity, has reduced power consumption simultaneously.
Brief description of the drawings
Fig. 1 is that in prior art, a multichannel final election device drives the data channel of other three multichannel final election devices to simplify circuit structure diagram;
The structure chart of a kind of multichannel final election device that Fig. 2 provides for the utility model embodiment;
In a kind of multichannel final election device that Fig. 3 provides for the utility model embodiment 64 selects the structure chart of 1 Port Multiplier;
The multichannel final election device that Fig. 4 provides for the utility model embodiment drives the data channel of other three multichannel final election devices to simplify circuit structure diagram.
Embodiment
Below by drawings and Examples, the technical solution of the utility model is described in further detail.
The utility model embodiment has proposed a kind of multichannel final election device, is applied in the interconnection structure of fpga chip.Fig. 1 shows a multichannel final election device in prior art and drives the data channel of other three multichannel final election devices to simplify circuit structure diagram, and its weak point is: signal transmission distortion, it is larger that signal output is difficult to maintenance complete linearity and power consumption.The multichannel final election device that the utility model provides comprises that M inverter, the N M with control bit selects 1 Port Multiplier;
N M selects i input parallel connection of 1 Port Multiplier, then is connected with the output of i the described inverter with control bit, and wherein N, M are integer, the exponential that M is 2, and i is 1,2 ..., M;
In the time that control bit is the first level, the inverter output high-impedance state with control bit, in the time that i control bit is second electrical level, opens with the inverter of control bit for i, and a gating N M selects 1 Port Multiplier.Wherein, the first level is specially 1, and second electrical level is specially 0.
The structure chart of a kind of multichannel final election device that Fig. 2 provides for the utility model embodiment, below with N=32, M=64 is example, the circuit structure of a kind of multichannel final election device in conjunction with Fig. 2 to the present embodiment describes, and this multichannel final election device comprises 64 inverter C11-C88 with control bit, selects 1 Port Multiplier for 32 64.
All 64 select the first input end i1 of 1 Port Multiplier to be connected in parallel, be connected with the output of the inverter D1 with control bit C11 again, all 64 select the second input i2 of 1 Port Multiplier to be connected in parallel, be connected with the output of the inverter D2 with control bit C12 again, the rest may be inferred, all 64 select the 60 four-input terminal i64 of 1 Port Multiplier to be connected in parallel, then are connected with the output of the inverter D64 with control bit C88.
Wherein, C11-C88 represents respectively 64 control bits of these 64 inverters, and inverter has power supply, and control bit is exactly the switch of controlling power supply opening or closing.
In a kind of multichannel final election device that Fig. 3 provides for the utility model embodiment 64 selects the structure chart of 1 Port Multiplier, selects the practical circuit diagram of 1 Port Multiplier to describe below to 64.
Concrete, 64 select 1 Port Multiplier to comprise that 8 select 1 Port Multiplier, a P type metal-oxide-semiconductor P1, the 2nd P type metal-oxide-semiconductor P2, inverter D0;
The output that in the first order each 8 selected 1 Port Multiplier selects the input of 1 Port Multiplier to be connected with in the second level one 8 respectively, in the second level 8 selects output, the drain electrode of a P type metal-oxide-semiconductor P1 and the drain electrode of the 2nd P type metal-oxide-semiconductor P2 of 1 Port Multiplier to be connected to the input of inverter D0, the grid input initialize signal init of the one P type metal-oxide-semiconductor P1, the source electrode of the source electrode of the one P type metal-oxide-semiconductor P1 and the 2nd P type metal-oxide-semiconductor P2 joins and connects power supply, and the grid of described the 2nd P type metal-oxide-semiconductor P2 is connected with the output of described inverter D0.
When initialize signal init is second electrical level, when the input of inverter D0 is the first level, the output of inverter D0 is second electrical level, the drain electrode of the one P type metal-oxide-semiconductor P1 is high-impedance state, the input of inverter D0 can be given and is pulled to the first level by the 2nd P type metal-oxide-semiconductor P2, gating 64 does not select 1 Port Multiplier, and in the time that initialize signal init is the first level, gating 64 selects 1 Port Multiplier.
Wherein, it is 8 that 8 in the first order selected the quantity of 1 Port Multiplier, and it is 1 that the quantity of 1 Port Multiplier is selected in 8 in the second level, and 8 select 1 Port Multiplier to be made up of 8 N-type metal-oxide-semiconductors.
In actual applications, 100 with interior input bit wide, and the Port Multiplier of output bit wide can be connected with 2 grades of Port Multipliers, and similar circuit as implied above is realized, and has not just enumerated here.
Fig. 3 circuit is copied to 32 to be connected in parallel, input the inverter of tape splicing control bit respectively for 64 and just obtained a kind of multichannel final election device that the utility model embodiment as shown in Figure 2 provides, each parallel connection of i.e. 64 inputs 32 times, has just become a kind of multichannel final election devices that 64 inputs 32 are exported.
Below in conjunction with Fig. 2 and Fig. 3, the course of work of a kind of multichannel final election device to the utility model embodiment proposition describes, specific as follows:
Start from power on, specific as follows:
By C11-C88 totally 64 control positions 1, first keep the power-off of inverter D1-D64, inverter D1-D64 closes, and its output is high-impedance state or 0.S1-S8, totally 16 control positions 0 of S21-S28 keeps all N-type metal-oxide-semiconductors to close, and 64 selects the not any a-road-through of gating road of 1 Port Multiplier, makes the position that outputs to inverter D0 input keep high-impedance state.
Then start initialization, specific as follows:
Initialize signal init keeps setting to 0, and makes the maintenance logical zero circuit that be made up of the 2nd P type metal-oxide-semiconductor P2 and inverter D0, exports 0 state.Now should be noted, select for 32 64 as shown in Figure 21 Port Multiplier when in parallel, each 64 selects in 1 circuit and has an init, and these 32 init can not drag down simultaneously, the time delay of several NS, can cause chip cisco unity malfunction because drag down simultaneously.
Wherein, the 2nd P type metal-oxide-semiconductor P2 and inverter D0 composition keep the circuit of logical zero, its operation principle is as follows: be 1 in the input of inverter D0, the output of inverter D0 can keep 0, then in the situation that inverter D0 has exported 0, the drain electrode of the one P type metal-oxide-semiconductor P1 is become to high resistant, and the output or 0 that pulls into 1. such reverser D0 is given in the input meeting of inverter D0 by the 2nd P type metal-oxide-semiconductor P2.
After initialization completes, initialize signal init puts 1, keep the output 0 automatically of logical zero circuit, first completing init discharges, control C11-C88 and open the control bit of wanting gating Na mono-road signal, want the control position 0 of gating Na mono-road signal, by S1-S8, totally 16 control bit gatings of S21-S28 has opened that signal of control bit.So just completed the input of 64 signals, 32 passages of gating, finally obtain the process of 32 outputs.
A large amount of multichannel final election device application scenarios, more than 90% final election device is not used.The input of final election device can hang on the transmission line of signal.The load of the input of traditional multichannel final election device, can be transfused to line and see, particularly eight 8 of this shared control bit S1-S8 are as shown in Figure 3 selected 1 Port Multiplier, and fan-out, the load of input all can be larger.The multichannel final election device that Fig. 4 provides for the utility model embodiment drives the data channel of other three multichannel final election devices to simplify circuit structure diagram, this there is shown the data channel reduced graph after the some inverters with control bit of gating, for example needing gating control bit is the inverter D1 of C11, in the time that control bit C11 is 0, inverter D1 opens, 32 the 64 first input end i1 that select 1 Port Multiplier that are gating in Fig. 2, in the utility model embodiment, input comes in just to access the inverter with control bit, and its effect is as follows:
(1) prime of the prior art drives and will select the transmission gate of 1 Port Multiplier composition to connect the PMOS pipe in back maintenance logical zero circuit by two-stage 8 as shown in Figure 1, resistance (R1, R2 and R3) the formation dividing potential drop of the metal wire before this PMOS pipe and load, can cause the distant signal cannot normal transmission.The utility model adds after the inverter with control bit, 64 select the output of 32 multichannel final election devices only to drive each 64 inverters with control bit that select the input of 32 multichannel final election devices, the i.e. output of the multichannel final election device input of 3 inverters respectively as shown in Figure 4, keeping the 2nd P type metal-oxide-semiconductor P2 in logical zero circuit is that to select the inverter of 32 multichannel final election device inside by 64 be that input in Fig. 4 drives inverter to drive, instead of driven by prime, therefore just can not exist the resistance of the metal wire before PMOS pipe and load to form dividing potential drop, and then can be because the resistance value influences of the metal wire before load be to the long-distance transmissions of signal,
(2) in prior art, in PMOS effect of inverter drive, be equivalent to a pull-up resistor, fan-out is more, pull-up resistor in parallel is stronger, dead resistance dividing potential drop on the metal wire before pull-up resistor meeting and load, and pull-up resistor is stronger, the time delay of signal is also just larger, when pull-up resistor is less than metal wire resistance, signal just can not transmit, from a fan-out, to 32 fan-outs, the value of time delay is not that equal proportion changes.As shown in Figure 4, it is that input in Fig. 4 drives inverter to drive that the 2nd P type metal-oxide-semiconductor P2 that keeps logical zero circuit selects the inverter of 32 multichannel final election device inside by 64, therefore just can not exist the resistance of the metal wire before PMOS pipe and load to form dividing potential drop, make pull-up resistor stronger, the time delay of signal is also just larger.Thereby make signal transmission keep complete linearity;
(3) in the prior art, in the time that fan-out number is larger, large from the physical distance of load because driving, the resistance of metal wire is very huge, the pull-up resistor of adding in load causes, rising edge and the trailing edge of signal are more slow, and the time of intermediate state can increase, and electric leakage can increase and causes power consumption larger.The utility model embodiment inputs into and just accesses after the inverter with control bit, drive apart from the physical distance of load and reduce, the resistance of metal wire is negligible with respect to pull-up resistor, the rising edge of signal and trailing edge can be steeper, the time of intermediate state is very little, thereby makes power-dissipation-reduced.
The utility model embodiment has proposed a kind of multichannel final election device, in the structure of this multichannel final election device, increase the inverter with control bit, the distortion of anti-stop signal long-distance transmissions, make signal output can keep complete linearity, also reduce power consumption, be applied to, in the interconnection structure in fpga chip, improve the systematic function of chip.
It should be noted last that, above embodiment is only unrestricted in order to the technical solution of the utility model to be described, although the utility model is had been described in detail with reference to preferred embodiment, those of ordinary skill in the art is to be understood that, can modify or be equal to replacement the technical solution of the utility model, and not depart from the spirit and scope of technical solutions of the utility model.
Claims (2)
1. a multichannel final election device, is characterized in that, described multichannel final election device comprises that M inverter, the N M with control bit selects 1 Port Multiplier;
A described N M selects i input parallel connection of 1 Port Multiplier, then is connected with the output of i the described inverter with control bit, and wherein N, M are integer, the exponential that M is 2, and i is 1,2 ..., M;
In the time that described control bit is the first level, described inverter with control bit output high-impedance state, in the time that i control bit is second electrical level, the individual described inverter with control bit of described i is opened, and N M selects 1 Port Multiplier described in gating.
2. multichannel final election device according to claim 1, is characterized in that, described M selects 1 Port Multiplier to be specially 64 and selects 1 Port Multiplier;
Described 64 select 1 Port Multiplier to comprise that 8 select 1 Port Multiplier, a P type metal-oxide-semiconductor P1, the 2nd P type metal-oxide-semiconductor P2, inverter D0;
The output that in the first order each 8 selected 1 Port Multiplier selects the input of 1 Port Multiplier to be connected with in the second level one 8 respectively, one 8 input that selects the drain electrode of the output of 1 Port Multiplier, a described P type metal-oxide-semiconductor P1 and the drain electrode of described the 2nd P type metal-oxide-semiconductor P2 to be connected to described inverter D0 in the described second level, the grid input initialize signal init of a described P type metal-oxide-semiconductor P1, the source electrode of the source electrode of the one P type metal-oxide-semiconductor P1 and the 2nd P type metal-oxide-semiconductor P2 joins and connects power supply, and the grid of described the 2nd P type metal-oxide-semiconductor P2 is connected with the output of described inverter D0;
When described initialize signal init is second electrical level, when the input of inverter D0 is the first level, the output of inverter D0 is second electrical level, the drain electrode of the one P type metal-oxide-semiconductor P1 is high-impedance state, the input of inverter D0 can be given and is pulled to the first level by the 2nd P type metal-oxide-semiconductor P2,64 do not select 1 Port Multiplier described in gating, in the time that described initialize signal init is the first level, described in gating, 64 select 1 Port Multiplier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201420397088.0U CN203968107U (en) | 2014-07-17 | 2014-07-17 | Multichannel final election device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201420397088.0U CN203968107U (en) | 2014-07-17 | 2014-07-17 | Multichannel final election device |
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| CN203968107U true CN203968107U (en) | 2014-11-26 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105322950A (en) * | 2014-07-17 | 2016-02-10 | 京微雅格（北京）科技有限公司 | Multipath check device |
-
2014
- 2014-07-17 CN CN201420397088.0U patent/CN203968107U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105322950A (en) * | 2014-07-17 | 2016-02-10 | 京微雅格（北京）科技有限公司 | Multipath check device |
| CN105322950B (en) * | 2014-07-17 | 2018-09-11 | 京微雅格（北京）科技有限公司 | Multichannel final election device |
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