CN109240832A - A kind of hardware reconstruction system and method - Google Patents
A kind of hardware reconstruction system and method Download PDFInfo
- Publication number
- CN109240832A CN109240832A CN201811113981.5A CN201811113981A CN109240832A CN 109240832 A CN109240832 A CN 109240832A CN 201811113981 A CN201811113981 A CN 201811113981A CN 109240832 A CN109240832 A CN 109240832A
- Authority
- CN
- China
- Prior art keywords
- pcie
- crossbar switch
- resource pool
- switch
- resource
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/54—Interprogram communication
- G06F9/547—Remote procedure calls [RPC]; Web services
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
Abstract
The invention discloses a kind of hardware reconstruction system and methods, the calculating such as GPU, FPGA, GPU, IPU, SSD and storage resource can be decoupled from server by PCIe multibus and crossbar switch technology and be come out by the present invention, and realize the interconnection for the stratification such as interconnecting in the pond of Heterogeneous Computing and memory resource pool between interconnection, pond.By based on the connection re-configurability in pond with the configuration offer standard PCIe computing resource of remote PCI e crossbar switch.Pass through the introducing of PCIe switch, the scalability and performance advantage for making full use of PCIe to communicate, can create the high highly available system of cost performance, can support most of heterogeneous device, versatility is stronger, and can reduce data transfer delay, system complexity and power consumption.
Description
Technical field
The present invention relates to field of computer technology, more particularly to a kind of hardware reconstruction system and method.
Background technique
At present in magnanimity node server use process, each component resource of presence server (CPU, memory, disk,
SSD, network I/O, GPU, FPGA etc.) utilization rate it is unbalanced caused by the wasting of resources and energy waste and these component resources
High cost caused by respectively server hardware caused by upgrading period difference frequently upgrades.Domestic data center service
Mostly by Ethernet connection there are agreements too fat to move, the high problem of power consumption between each hardware resource of device, and InfiniBand etc. is even
Special equipment is connect and needs, device dependence is strong.The enterprises such as Baidu, Tencent, Huawei are started to be calculated with server, storage, be transmitted
The decoupling of equal components resource and pond turn to direction and carry out architectural studies, including pond storage service, Heterogeneous Computing resource (FPGA,
GPU, CPU, IPU) pondization service etc..But it is limited only to complete machine level currently based on PCIe hardware resource pool, and also visiting
Rope does not form standard.And merely with PCIe extended capability, it is ignored in the advantage for communicating and reconstructing scheduling.
Summary of the invention
The present invention provides a kind of hardware reconstruction system and methods, to solve in prior art hardware reconstruction to all parts
The unbalanced problem of utilization rate.
On the one hand, the present invention provides a kind of hardware reconstruction systems includes:
Between each resource pool and the resource pool closed on, the multichannel interface connection based on remote PCI e crossbar switch, resource
Multichannel interface connection in pond based on PCIe crossbar switch, remote PCI e crossbar switch and the PCIe crossbar switch in resource pool,
It is connected together by shared interface, forms the double-deck crossbar configuration based on PCIe crossbar switch and remote PCI e crossbar switch
Link；
Wherein, the resource pool includes computing resource pool and/or memory resource pool, and each processor passes through resource in resource pool
PCIe crossbar switch inside pond is interconnected, and when being attached configuration, is configured inside resource pool by configuration information
PCIe crossbar switch connection relationship is calculating and storage resource inside the specified PCIe bus assignment resource pool of CPU, realizes meter
It calculates and is directly connected between resource pool, memory resource pool inner treater, support computing resource and the distribution of storage resource dynamic on-demand；
The remote PCI e crossbar switch is interconnected by shared interface and each resource pool, realizes the resource based on PCIe protocol
Point-to-point peer switch between pond configures the connection of remote PCI e crossbar switch by configuration information when being attached configuration
Relationship is the processor resource in the specified PCIe bus assignment Adjacent resource pond of CPU, carries out calculating and storage money between resource pool
Source dynamically distributes.
Preferably, the shared interface supports two kinds of interface modes of transparent bridge and non-transparent bridge, can be configured to main side
Mouthful or from port, interconnected between realizing port by PCIe shared interface cable.
Preferably, the PCIe crossbar switch in the resource pool includes with the realization of PCIe switching backplane, PCIe switching backplane
Multichannel PCIe bus slot and PCIe exchange chip.
Preferably, the remote PCI e crossbar switch is realized with PCIe switch, realizes the point-to-point exchange between resource pool
Mode, including one of following or a variety of: packet switch, circuit switching and virtual channel exchange.
Preferably, virtual channel exchange multiple shares the same physical channel for being made up of virtual channel
Virtual circuit exchange connection, and virtual circuit exchange connection can connect with packet switch connection and circuit switching cooperate to transmit
Flow data.
It preferably, further include compiler；The compiler is used for according to known internuclear stream communication situation, for every
Know stream communication distribution path, and determine that virtual circuit exchange connection, circuit switching connection are connected with packet switch, at runtime basis
As a result, establishing each exchange connection by the link information prestored, the communication between different resource pond is respectively being corresponded to for communication compiling
Exchange connection on transmitted.
Preferably, the remote PCI e crossbar switch includes multiple input units, and a crossbar switch crosses over unit, path
Computing unit, virtual channel allocation unit, crossbar switch allocation unit and circuit configuration unit；
The input unit, for the virtual channel number after the PCIe device configuration output arbitration for connection, each input
Unit includes n output virtual channel VC1-VCn, and a bypass channel, a PS state stores and a VCS state storage,
The input unit exchanges VCS signal with the input virtual channel of PCIe device and port input signal is connected, the storage of PS state
The virtual channel state of corresponding basic packet switch router, VCS state store corresponding virtual circuit and exchange connection status, work as input
When for VCS signal, then the corresponding output virtual channel of input virtual channel is directly found by the information in the storage of VCS state
Number, VCS signal is directly output to the corresponding PCIe device of output virtual channel number, and each input unit increases a bypass
Unit is crossed over to allow packet switched data piece to be directly inputted to the crossbar switch in channel；
The path-calculating element exists for establishing the port ID- routed path or address: Port routed path for transmission
The data slice of packet switch connection provides path arbitration result；
The virtual channel allocation unit, for the path arbitration result according to the path-calculating element or according to PS shape
State stores information, for input data piece distribution output virtual channel number；
The circuit configuration unit is matched for providing the crossbar switch prestored in the data slice that circuit switching connects for transmission
Confidence breath；
The crossbar switch allocation unit stores information for storing preset circuit configuration by circuit configuration, directly
Crossbar switch is configured, the data slice that circuit switching is connected directly enters the intersection by by-pass switch and opens
It closes and crosses over unit；
The crossbar switch exports data packet for the arbitration scheduling result according to the input unit across unit
To the corresponding PCIe device of output virtual channel number.
Preferably, the computing resource pool includes one of following or a variety of: CPU, GPU, FPGA, IPU.
Preferably, the memory resource pool includes one of following or a variety of: SSD, HDD.
On the other hand, the present invention provides a kind of hardware reconstruction methods, and this method is using hardware described in any of the above-described kind
Reconfiguration system, comprising:
Step 1: PCIe bus being scanned by management node, acquisition is connected to PCIe crossbar switch in PCIe multibus and pond
On PCIe device port information, wherein the management node be preset cpu node；
Step 2: the remote PCI e crossbar switch that PCIe crossbar switch shared interface connects in pond where management node obtains
PCIe device port information；
Step 3: CPU, GPU, FPGA, IPU, SSD, HDD for specifying PCIe bus to connect according to user requirements analysis etc. is hard
The type and quantity of part equipment；
Step 4: the type and quantity of the hardware device according to needed for step 3 judge local computing and memory resource pool
Whether interior resource is enough, and step 5 is transferred to if enough, not enough, is transferred to step 7；
Step 5: management node configures the configuration space of the PCIe crossbar switch in resource pool, according to depth-first
Searching algorithm is that specified PCIe bus configuration distributes required processor, PCIe crossbar switch in configured pool, and is connected in pond
Principal and subordinate's bus of device port, the information such as command register are managed everywhere in PCIe crossbar switch；
Step 6: passing through PCIe data needed for the packet format of PCIeDMA or the PCIe link layer protocol of the standard building present invention
Packet accesses the equipment for being connected to specified PCIe bus, terminates the configuration of PCIe hardware reconstruction；
Step 7: management node configures the configuration space of the PCIe crossbar switch in resource pool, total for specified PCIe
Line distributes available calculating and storage resource；
Step 8: management node configures remote PCI e crossbar switch, carries out empty friendship according to remote PCI e crossbar switch
Channel, packet switch channel, circuit-switched channels configuration are changed, two kinds of connecting interfaces of transparent bridge and non-transparent bridge are supported, needed for connection
Adjacent calculating and memory resource pool；
Step 9: management node is needed for specified PCIe bus assignment local resource pond according to Depth Priority Algorithm
Processor, processor needed for selected adjacent resource pool, in configured pool/remote PCI e crossbar switch, and it is connected to PCIe intersection
Principal and subordinate's bus of device port, the information such as command register are managed everywhere in switch, and are transferred to step 6.
The present invention has the beneficial effect that:
The present invention GPU, FPGA, GPU, IPU, SSD etc. can be calculated by PCIe multibus and crossbar switch technology and
Storage resource is decoupled from server and is come out, and is realized and the layers such as interconnected in the pond of Heterogeneous Computing and memory resource pool between interconnection, pond
The interconnection of secondaryization.The connection re-configurability of configuration offer standard PCIe computing resource based on PCIe crossbar switch is provided.Pass through
The introducing of PCIe switch can create the high highly available system of cost performance, make full use of expanding by PCIe communication
Malleability, performance advantage, can support most of heterogeneous device, and versatility is stronger；PCIe configuration feature is provided, it can be according to data center
The performance of server needs switching at runtime to calculate, storage and network, can be the calculate node of application distribution correct amount, each to count
Calculating storage resource can be managed collectively, flexible allocation, support connection reconstruct；Data transfer delay, system complex can be reduced
Property and power consumption, Save power consumption rate is up to 50% in data-intensive environment.
The above description is only an overview of the technical scheme of the present invention, in order to better understand the technical means of the present invention,
And it can be implemented in accordance with the contents of the specification, and in order to allow above and other objects of the present invention, feature and advantage can
It is clearer and more comprehensible, the followings are specific embodiments of the present invention.
Detailed description of the invention
By reading the following detailed description of the preferred embodiment, various other advantages and benefits are common for this field
Technical staff will become clear.The drawings are only for the purpose of illustrating a preferred embodiment, and is not considered as to the present invention
Limitation.And throughout the drawings, the same reference numbers will be used to refer to the same parts.In the accompanying drawings:
Fig. 1 is a kind of hardware reconstruction system architecture schematic diagram of the embodiment of the present invention；
Fig. 2 be the embodiment of the present invention it is a kind of based in pond/the specific framework of hardware reconstruction system of long-range crossbar switch shows
It is intended to；
Fig. 3 is the reconstruct schematic diagram based on PCIe crossbar switch in the resource pool of the embodiment of the present invention；
Fig. 4 is the reconstruct schematic diagram based on remote PCI e crossbar switch between the resource pool of the embodiment of the present invention；
Fig. 5 is the remote PCI e cross bar structure schematic diagram of the embodiment of the present invention；
Fig. 6 is the PCIe transaction packet package head format schematic diagram of the embodiment of the present invention；
Fig. 7 is the flow diagram of PCIe hardware reconstruction of embodiment of the present invention configuration.
Specific embodiment
Exemplary embodiments of the present disclosure are described in more detail below with reference to accompanying drawings.Although showing the disclosure in attached drawing
Exemplary embodiment, it being understood, however, that may be realized in various forms the disclosure without should be by embodiments set forth here
It is limited.On the contrary, these embodiments are provided to facilitate a more thoroughly understanding of the present invention, and can be by the scope of the present disclosure
It is fully disclosed to those skilled in the art.
First embodiment of the invention provides a kind of hardware reconstruction system, referring to Fig. 1, comprising:
Between each resource pool and the resource pool closed on, the multichannel interface connection based on remote PCI e crossbar switch, resource
Multichannel interface connection in pond based on PCIe crossbar switch, remote PCI e crossbar switch and the PCIe crossbar switch in resource pool,
It is connected together by shared interface, forms the double-deck crossbar configuration based on PCIe crossbar switch and remote PCI e crossbar switch
Link；
Wherein, the resource pool includes computing resource pool and/or memory resource pool, and each processor passes through resource in resource pool
PCIe crossbar switch inside pond is interconnected, and when being attached configuration, is configured inside resource pool by configuration information
PCIe crossbar switch connection relationship is calculating and storage resource inside the specified PCIe bus assignment resource pool of CPU, realizes meter
It calculates and is directly connected between resource pool, memory resource pool processor, support computing resource and the distribution of storage resource dynamic on-demand；
The remote PCI e crossbar switch is interconnected by shared interface and each resource pool, realizes the resource based on PCIe protocol
Point-to-point peer switch between pond configures the connection of remote PCI e crossbar switch by configuration information when being attached configuration
Relationship is the processor resource in the specified PCIe bus assignment Adjacent resource pond of CPU, carries out calculating and storage money between resource pool
Source dynamically distributes.
The present invention GPU, FPGA, GPU, IPU, SSD etc. can be calculated by PCIe multibus and crossbar switch technology and
Storage resource is decoupled from server and is come out, and is realized and the layers such as interconnected in the pond of Heterogeneous Computing and memory resource pool between interconnection, pond
The interconnection of secondaryization.The connection re-configurability of configuration offer standard PCIe computing resource based on PCIe crossbar switch is provided.Pass through
The introducing of PCIe switch makes full use of the scalability and performance advantage communicated by PCIe, can create cost performance height
Highly available system, can support most of heterogeneous device, versatility is stronger；PCIe configuration feature is provided, it can be according in data
The performance of central server needs switching at runtime to calculate, storage and network, can be the calculate node of application distribution correct amount, respectively
Calculating storage resource can be managed collectively, flexible allocation, support connection reconstruct；It is multiple that data transfer delay, system can be reduced
Polygamy and power consumption, Save power consumption rate is up to 50% in data-intensive environment.
It should be noted that shared interface described in the embodiment of the present invention supports two kinds of interface moulds of transparent bridge and non-transparent bridge
Formula can be configured to master port or from port, interconnect between realizing port by PCIe shared interface cable.
In the embodiment of the present invention, the PCIe crossbar switch in the resource pool is with the realization of PCIe switching backplane, PCIe exchange
Bottom plate includes multichannel PCIe bus slot and PCIe exchange chip.
In the embodiment of the present invention, the remote PCI e crossbar switch is realized with PCIe switch, realizes the point between resource pool
To an exchanged form, including one of following or a variety of: packet switch, circuit switching and virtual channel exchange.
The exchange of virtual channel described in the embodiment of the present invention multiple shares the same physics for being made up of virtual channel
The virtual circuit in channel exchanges connection, and virtual circuit exchange connection can connect cooperation with packet switch connection and circuit switching and come
Transmit flow data.
System described in the embodiment of the present invention further includes compiler；The compiler, for according to known internuclear circulation
Believe situation, be every known flow allocation of communications path, and determines that virtual circuit exchange connection, circuit switching connection and packet switch connect
It connects, is connected at runtime according to communication compiling as a result, establishing each exchange by the link information prestored, between different resource pond
Communication is transmitted in corresponding exchange connection.
In the embodiment of the present invention, the remote PCI e crossbar switch includes multiple input units, and a crossbar switch is crossed over
Unit, path-calculating element, virtual channel allocation unit, crossbar switch allocation unit and circuit configuration unit；
The input unit, for the virtual channel number after the PCIe device configuration output arbitration for connection, each input
Unit includes n output virtual channel VC1-VCn, and a bypass channel, a PS state stores and a VCS state storage,
The input unit exchanges VCS signal with the input virtual channel of PCIe device and port input signal is connected, the storage of PS state
The virtual channel state of corresponding basic packet switch router, VCS state store corresponding virtual circuit and exchange connection status, work as input
When for VCS signal, then the corresponding output virtual channel of input virtual channel is directly found by the information in the storage of VCS state
Number, VCS signal is directly output to the corresponding PCIe device of output virtual channel number, and each input unit increases a bypass
Unit is crossed over to allow packet switched data piece to be directly inputted to the crossbar switch in channel；
The path-calculating element exists for establishing the port ID- routed path or address: Port routed path for transmission
The data slice of packet switch connection provides path arbitration result；
The virtual channel allocation unit, for the path arbitration result according to the path-calculating element or according to PS shape
State stores information, for input data piece distribution output virtual channel number；
The circuit configuration unit is matched for providing the crossbar switch prestored in the data slice that circuit switching connects for transmission
Confidence breath；
The crossbar switch allocation unit stores information for storing preset circuit configuration by circuit configuration, directly
Crossbar switch is configured, the data slice that circuit switching is connected directly enters the intersection by by-pass switch and opens
It closes and crosses over unit；
The crossbar switch exports data packet for the arbitration scheduling result according to the input unit across unit
To the corresponding PCIe device of output virtual channel number.
It should be noted that computing resource pool described in the embodiment of the present invention includes one of following or a variety of: CPU,
GPU, FPGA, IPU, etc..The memory resource pool includes one of following or a variety of: SSD, HDD, etc..Specific ability
The technical staff in domain can be configured according to actual needs, and the present invention is not especially limited this.
Detailed explanation and illustration is carried out below in conjunction with Fig. 1-6 system described in the embodiment of the present invention:
As shown in Figure 1, the present invention constructs a series of resource pools first, and between each resource pool and the resource pool closed on, base
It is connected in the multichannel interface of remote PCI e crossbar switch, the multichannel interface connection in resource pool based on PCIe crossbar switch, remotely
PCIe crossbar switch in PCIe crossbar switch and resource pool, is connected together by shared interface, formed based on crossbar switch and
The double-deck crossbar configuration link of remote PCI e crossbar switch supports star topology, network topology, tree-shaped between each resource pool
A variety of connection relationships such as topology and full connection topology；
Wherein, resource pool includes computing resource pool and/or memory resource pool, and each processor passes through in resource pool in resource pool
The crossbar switch in portion is interconnected.Computing resource pool includes the Heterogeneous Computings resource such as CPU, GPU, FPGA, IPU, memory resource pool
The storage resources such as including SSD, HDD.Each calculating memory resource pool contains the pond CPU, the pond GPU, the pond FPGA, the pond IPU, storage pool
Deng at least one resource pool.Wherein: the pond CPU contains muti-piece CPU processor, and the pond GPU contains muti-piece GPU processor, FPGA
Pond contains muti-piece FPGA processor, and the pond IPU contains the IPU processor such as muti-piece Cambrian, storage pool contain muti-piece SSD,
The hard-disc storages resource such as HDD, each calculating and storage resource externally pass through PCIe bus and are attached with crossbar switch.Connected
When connecing configuration, the crossbar switch connection relationship inside resource pool is configured by configuration information, is the specified PCIe bus assignment of CPU
Calculating and storage resource inside resource pool are realized and are directly connected between computing resource pool, memory resource pool inner treater, are propped up
Hold computing resource and the distribution of storage resource dynamic on-demand.
Crossbar switch in resource pool includes multiple shared interfaces, and shared interface support transparent bridge and two kinds of non-transparent bridge connect
Mouth mold formula can be configured to master port or from port, interconnect, can connect between realizing port by PCIe shared interface cable
The PCIe device of arbitrary standards PCIe3.0 interface.Shared interface crossbar switch by multichannel PCIe bus and the pond CPU, the pond GPU,
The pond FPGA, the pond IPU, in storage pool everywhere in reason device be directly connected to, configuration information can be passed through and control specified input interface and output
The direct-connected relationship of interface can configure crossbar switch and specify PCIe bus assignment by the way that reconfiguration information is inputted crossbar switch
It calculates, storage resource, is calculated for CPU, FPGA, GPU, IPU, the memory etc. of multichannel PCIe bus assignment cascade on the bus
And storage resource.
Remote PCI e crossbar switch realizes point-to-point peer switch between the resource pool based on PCIe protocol.It is long-range to intersect
Switch is attached by shared interface and the crossbar switch in resource pool, realizes the communication interconnection between resource pool.Connected
When connecing configuration, long-range crossbar switch connection relationship is configured by configuration information, is the specified PCIe bus assignment Adjacent resource of CPU
The processor resource in pond supports calculating and storage resource between resource pool to dynamically distribute.
By input reconstruct configuration information to crossbar switch, crossbar switch occupies feelings according to user demand and current system
Condition changes the connection relationship of the virtual PCI Bridge in crossbar switch by configuration information, is connected to it for specified PCIe bus assignment
In calculating and storage resource.Such as a moment specifies the system 1 in PCIe bus for 4 pieces of GPU, 4 pieces of CPU, 4 pieces of FPGA, 8
Block SSD；Subsequent time configures crossbar switch by reconfiguration information, and the computing system connected in the PCIe bus becomes system 2,
Including 2 pieces of CPU, 1 piece of GPU, 1 piece of FPGA, 2 pieces of SSD；Subsequent time again configures crossbar switch by reconfiguration information, and the PCIe is total
The computing system connected on line becomes system 3, including 1 piece of CPU, 1 piece of GPU, 1 piece of FPGA, 2 pieces of SSD.Pass through change to be formed
The connection relationship between storage resource is calculated, so that hardware system supports computing capability and concatenation ability reconstruct, to be formed
It calculates and the dynamic on-demand of storage resource distributes.
As shown in Fig. 2, the embodiment of the present invention includes 6 calculating and memory resource pool, 1 remote PCI e crossbar switch and 1
A main controlled node.Wherein: including 1 piece of PCIe crossbar switch backboard in each resource pool, it includes multichannel PCIe that PCIe, which intersects backboard,
Bus slot and 1 PEX8796 exchange chip, the calculating such as CPU, GPU, FPGA, IPU, SSD and storage resource insertion PCIe intersect
In the slot for switching backboard, the interconnection reconstruct in resource pool is realized.By PCIe shared interface connecting line and far between resource pool
Journey crossbar switch is connected, and the MiniSAS interface cable of the shared interface connection line options PCIex4 of present case is realized.It is long-range to intersect
Switch realizes that the PCIe switch of the implementation case includes 12 ports in the form of PCIe switch, can support 12 meters
It calculates and the point-to-point peer switch of memory resource pool, 12 ports can be configured to transparent bridge mode and non-transparent bridge mode,
Transparent bridge mode for connect calculating/memory resource pool without CPU, non-transparent bridge mode be used to connect include host calculating/
Memory resource pool.Main controlled node is connected by remote PCI e crossbar switch with multiple calculating and memory resource pool, for reconstructing
Configuration and Data Transmission Controlling.Main controlled node is by PCIe crossbar switch in remote PCI e crossbar switch and resource pool to connection
Hardware device is scanned, by PCIe crossbar switch in resource pool, remote PCI e crossbar switch according to reconstruct configuration information
It is configured, distributes different calculating and storage resource for CPU, realize hardware system reconstruct.
As shown in figure 3, the reconfiguration system based on crossbar switch in the resource pool of another specific implementation case of the invention,
Wherein, crossbar switch is realized in the form of PCIe switching backplane in resource pool, and PCIe switching backplane includes that multichannel PCIe bus is inserted
Slot and PCIe exchange chip.It will be in crossbar switch backboard slot in different calculating and storage resource insertion pond.The resource pool
Hardware structure dynamic construction uses the method based on PCIe multiple bus and crossbar switch, and configuration information controls the defeated of crossbar switch
The interconnecting relation of incoming interface and output interface.The hardware resources such as difference CPU, GPU, FPGA, IPU, SSD, HDD are connected in figure
The different PCIe bus slot of crossbar switch, CPU, which can choose, to be connected to the hardware device group of specified bus slot and builds up difference
Computing system.By configuring the crossbar switch in resource pool, the hardware device connected in PCIe bus can change.Example
Such as: for subsequent time by changing crossbar configuration, the hardware resource of the PCIe buses such as PCIe bus 1, PCIe bus 2 connection can
To be exchanged, additions and deletions etc. change, to form new computing system.
For the hardware resources such as CPU, GPU, FPGA, IPU, SSD, HDD in different calculating and memory resource pool
Reconstruction Mechanism is as shown in Figure 4.It is interconnected between Adjacent resource pond by remote PCI e crossbar switch, is handled between realization resource pool
The communication of device.Remote PCI e crossbar switch is realized in the form of PCIe switch, including multiple PCIe shared ports, different resource
The hardware structure dynamic construction in pond is realized based on the control of remote PCI e crossbar switch.
Such as: the hardware resource of resource pool 1 and resource pool 2 is carried out by remote PCI e crossbar switch shown in Fig. 4 in figure
Connection allows resource pool 1 and the hardware resource of resource 2 directly can realize data interaction by the transmission of PCIe.Remote PCI e intersects
Switch is connected together with the crossbar switch in resource pool by shared interface.It is formed and is opened based on crossbar switch and remote PCI e intersection
The double-deck crossbar configuration link of pass.When being attached configuration, calculating and storage resource are configured by configuration information first
Crossbar switch connection relationship inside pond calculates with the specified PCIe bus assignment inside memory resource pool and stores money to calculate
Source；Then the remote PCI e crossbar switch between resource pool is configured, realizes that resource pool is directly connected to resource pool.As shown in Figure 4
Resource pool between hardware reconstruction mechanism, can be made by the configuration to crossbar switch and remote PCI e crossbar switch in pond
Obtain may be implemented to be in communication with each other between SSD, CPU in CPU, FPGA and mainboard 2 in mainboard 1, without influencing other hardware money
The use in source.
Fig. 5 is the composed structure schematic diagram of long-range crossbar switch, as shown in figure 5, the embodiment of the present invention is supported in following
One or more exchanged forms: packet switch PS, circuit switching (CS) and virtual channel exchange VCS.Virtual channel exchange, for passing through
Virtual channel forms multiple virtual circuits exchange connections for sharing the same physical channel, and virtual circuit exchange connection can be with
Cooperation is connect with packet switch connection and circuit switching to transmit flow data.According to known internuclear stream communication situation, pass through compiling
Device is every known flow allocation of communications path, and determines that virtual circuit exchange connection, circuit switching connection are connected with packet switch,
It is established respectively according to communication compiling as a result, link information is stored in each PCIe exchanger by the link information prestored when operation
Exchange connects, and the communication between different motherboard resources ponds is transmitted in corresponding exchange connection.
Compared with basic packet switcher, the exchanger of mixed strategy of the present invention needs some additional hardware: including side
Paths, circuit configuration storage and the storage of VCS state.Remote PCI e crossbar switch includes multiple input units, and an intersection is opened
It closes and crosses over, path computing, the submodules such as virtual channel distribution, crossbar switch distribution, circuit configuration.
Wherein: input unit is used for the virtual channel number after the PCIe device configuration output arbitration for connection, each input
Unit includes n output virtual channel VC1-VCn, a bypass channel, a PS state storage and a VCS state storage.
The input unit exchanges VCS signal and port input signal with the input virtual channel of PCIe device and is connected, VCS signal and defeated
The port numbers of the number and PCIe device that enter signal correspond.Virtual the leading to of the corresponding basic packet switch router of PS state storage
Road state.VCS state stores corresponding virtual circuit and exchanges connection status.When input is VCS signal, then directly pass through VCS shape
Information in state storage finds the corresponding output virtual channel number of input virtual channel, and it is empty that VCS signal is directly output to output
The quasi- corresponding PCIe device of channel number；PS state and VCS state have all respectively contained n domain, this corresponding n virtual channel.And
And n virtual channel is connected with packet switch by virtual circuit exchange connection and is shared.And each input unit increases a bypass
Channel allows data slice not need through virtual channel, is directly inputted to crossbar switch across submodule.
Path calculation module is attached with input unit, for establishing the port ID- routed path or address: Port routing
Path provides path arbitration result in the data slice that packet switch connects for transmission.Wherein ID- port routing table provides PCIe device
Map paths relationship number between port numbers；Address: Port routing table is provided between PCIe device physical address and port numbers
Map paths relationship.Communication path arbitration is carried out according to the ID in PCIe transaction packet, address when operation.
Virtual channel allocation unit stores letter for the path arbitration result according to path-calculating element or according to PS state
Breath, for input data piece distribution output virtual channel number；
Circuit configuration unit, for providing the crossbar configuration prestored letter in the data slice that circuit switching connects to transmit
Breath, storage are used to connect the link information of storage physical channel to circuit switching, distribute with crossbar switch distribution and virtual channel
Module is attached, and circuit switching connection is established by setting circuit configuration information.
Crossbar switch allocation unit stores information for storing preset circuit configuration by circuit configuration, directly to friendship
Fork puts capable configuration into, and the data slice that circuit switching is connected directly enters crossbar switch across son by by-pass switch
Module；
Data packet is output to output for the arbitration scheduling result according to input unit across submodule by crossbar switch
The corresponding PCIe device of virtual channel number.
For the mixed strategy for realizing support circuit-switched, packet switch and virtual channel exchange, this patent has modified PCIe thing
It is engaged in the PCIe transaction layer packet header wrapped, exchange flag bit being added in reserved field, as shown in Figure 6.Carrying out PCIe crossbar switch
When hardware reconstruction configures, according to the exchange flag bit in PCIe transaction layer packet header, corresponding exchanging policy is selected.
If the exchange flag bit in input signal PCIe transaction layer packet header is input virtual channel VCS signal, directly logical
VCS status information is crossed, finds the corresponding output virtual channel number of input virtual channel, it is empty that VCS signal is directly output to output
The quasi- corresponding PCIe device of channel number.
If input signal is PCIe port input signal, needs to be inputted in input unit according to PCIe port first and believe
Number carry out arbitration scheduling.It is that transmission is handed in circuit if the exchange flag bit in PCIe transaction layer packet header is circuit-switched signals
The data slice for changing connection reaches input unit, and crossbar switch is stood across submodule according to the link information prestored in circuit configuration
It configures, then the data slice directly passes through bypass channel and enters crossbar switch across submodule, and crossbar switch crosses over submodule
Data packet is directly output to corresponding PCIe device according to configuration result.
If input signal is PCIe port input signal, needs to be inputted in input unit according to PCIe port first and believe
Number carry out arbitration scheduling.It is that transmission connects in packet switch if the exchange flag bit in PCIe transaction layer packet header is packet switch signal
The data slice that connects reaches input unit, then first according to the path arbitration result of path-calculating element or according to PS status information,
Output virtual channel number is distributed for input data piece, output virtual port number is then sent to crossbar switch and crosses over submodule,
Data packet, according to arbitration scheduling result, is output to the corresponding PCIe of output virtual channel number and set by crossbar switch across submodule
It is standby.
Second embodiment of the invention provides a kind of hardware reconstruction method, and referring to Fig. 7, this method application present invention first is real
Apply any hardware reconstruction system in example, comprising:
Step 1: PCIe bus being scanned by management node, acquisition is connected to PCIe crossbar switch in PCIe multibus and pond
On PCIe device port information, wherein the management node be preset cpu node；
Step 2: the remote PCI e crossbar switch that PCIe crossbar switch shared interface connects in pond where management node obtains
PCIe device port information；
Step 3: CPU, GPU, FPGA, IPU, SSD, HDD for specifying PCIe bus to connect according to user requirements analysis etc. is hard
The type and quantity of part equipment；
Step 4: the type and quantity of the hardware device according to needed for step 3 judge local computing and memory resource pool
Whether interior resource is enough, and step 5 is transferred to if enough, not enough, is transferred to step 7；
Step 5: management node configures the configuration space of the PCIe crossbar switch in resource pool, according to depth-first
Searching algorithm is that specified PCIe bus configuration distributes required processor, PCIe crossbar switch in configured pool, and is connected in pond
Principal and subordinate's bus of device port, the information such as command register are managed everywhere in PCIe crossbar switch；
Step 6: passing through PCIe data needed for the packet format of PCIeDMA or the PCIe link layer protocol of the standard building present invention
Packet accesses the equipment for being connected to specified PCIe bus, terminates the configuration of PCIe hardware reconstruction；
Step 7: management node configures the configuration space of the PCIe crossbar switch in resource pool, total for specified PCIe
Line distributes available calculating and storage resource；
Step 8: management node configures remote PCI e crossbar switch, carries out empty friendship according to remote PCI e crossbar switch
Channel, packet switch channel, circuit-switched channels configuration are changed, two kinds of connecting interfaces of transparent bridge and non-transparent bridge are supported, needed for connection
Adjacent calculating and memory resource pool；
Step 9: management node is needed for specified PCIe bus assignment local resource pond according to Depth Priority Algorithm
Processor, processor needed for selected adjacent resource pool, in configured pool/remote PCI e crossbar switch, and it is connected to PCIe intersection
Principal and subordinate's bus of device port, the information such as command register are managed everywhere in switch, and are transferred to step 6.
The embodiment of the present invention is realized by the way that configuration is reconstructed to crossbar switch, remote PCI e crossbar switch in resource pool
Computing capability reconstruct, concatenation ability reconstruct.For details, reference can be made to first embodiment of the invention, the embodiment of the present invention is not made this in detail
It discusses.
The embodiment of the present invention can at least bring it is below the utility model has the advantages that
1. the embodiment of the present invention supports the Heterogeneous Computings resources such as CPU, GPU, FPGA, IPU, the storage resources such as SSD, HDD point
Cloth is interconnected between each memory resource pool by remote PCI e crossbar switch, storage resource in each calculating and memory resource pool
Each CPU, GPU in pond, FPGA, IPU, it is interconnected by PCIe multibus and crossbar switch between storage resource, so that hardware resource
Can be decoupling, improve the dynamic configurability of network；
2. the present invention provides the stratification interconnection scheme of PCIe crossbar switch and remote PCI e crossbar switch in a kind of pond, lead to
It crosses and is configured in pond with remote PCI e crossbar switch, can be needed according to the performance of data center server for application distribution just
When the calculate node and memory node of quantity, each storage resource that calculates can be managed collectively, and flexible allocation is each hard by reconstructing
Connection between part resource can effectively promote hardware frame so that hardware structure supports computing capability and concatenation ability to construct on demand
The performance and efficiency of structure；
3. the present invention provides a kind of remote PCI e crossbar configuration scheme of hybrid switching mechanism, while packet being supported to hand over
It changes, circuit switching and virtual channel three kinds of exchanged forms of exchange, wherein virtual channel exchange can directly pass through crossbar switch, configure
It is more easy, while supporting to use packet switch or circuit switching in link conflict, guarantee efficiently to be based on PCIe multiple bus
With the communication link of crossbar switch.
It should be noted that PCIe crossbar switch described in the embodiment of the present invention can be realized by PCIeswitch chip,
Crossbar switch function can also be realized by FPGA.
Algorithm and display are not inherently related to any particular computer, virtual system, or other device provided herein.
Various general-purpose systems can also be used together with teachings based herein.As described above, it constructs required by this kind of system
Structure be obvious.In addition, the present invention is also not directed to any particular programming language.It should be understood that can use various
Programming language realizes summary of the invention described herein, and the description done above to language-specific is to disclose this hair
Bright preferred forms.
In the instructions provided here, numerous specific details are set forth.It is to be appreciated, however, that implementation of the invention
Example can be practiced without these specific details.In some instances, well known method, structure is not been shown in detail
And technology, so as not to obscure the understanding of this specification.
Similarly, it should be understood that in order to simplify the disclosure and help to understand one or more of the various inventive aspects,
Above in the description of exemplary embodiment of the present invention, each feature of the invention is grouped together into single implementation sometimes
In example, figure or descriptions thereof.However, the disclosed method should not be interpreted as reflecting the following intention: i.e. required to protect
Shield the present invention claims features more more than feature expressly recited in each claim.More precisely, as following
Claims reflect as, inventive aspect is all features less than single embodiment disclosed above.Therefore,
Thus the claims for following specific embodiment are expressly incorporated in the specific embodiment, wherein each claim itself
All as a separate embodiment of the present invention.
Those skilled in the art will understand that can be carried out adaptively to the module in the equipment in embodiment
Change and they are arranged in one or more devices different from this embodiment.It can be the module or list in embodiment
Member or component are combined into a module or unit or component, and furthermore they can be divided into multiple submodule or subelement or
Sub-component.Other than such feature and/or at least some of process or unit exclude each other, it can use any
Combination is to all features disclosed in this specification (including adjoint claim, abstract and attached drawing) and so disclosed
All process or units of what method or apparatus are combined.Unless expressly stated otherwise, this specification is (including adjoint power
Benefit require, abstract and attached drawing) disclosed in each feature can carry out generation with an alternative feature that provides the same, equivalent, or similar purpose
It replaces.
In addition, it will be appreciated by those of skill in the art that although some embodiments described herein include other embodiments
In included certain features rather than other feature, but the combination of the feature of different embodiments mean it is of the invention
Within the scope of and form different embodiments.For example, in the following claims, embodiment claimed is appointed
Meaning one of can in any combination mode come using.
Various component embodiments of the invention can be implemented in hardware, or to run on one or more processors
Software module realize, or be implemented in a combination thereof.It will be understood by those of skill in the art that can be used in practice
Microprocessor or digital signal processor (DSP) realize that Distributed File System Data according to an embodiment of the present invention imports
The some or all functions of some or all components in device.The present invention is also implemented as being retouched here for executing
The some or all device or device programs (for example, computer program and computer program product) for the method stated.
It is such to realize that program of the invention can store on a computer-readable medium, or can have one or more signal
Form.Such signal can be downloaded from an internet website to obtain, be perhaps provided on the carrier signal or with it is any its
He provides form.
It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and ability
Field technique personnel can be designed alternative embodiment without departing from the scope of the appended claims.In the claims,
Any reference symbol between parentheses should not be configured to limitations on claims.Word "comprising" does not exclude the presence of not
Element or step listed in the claims.Word "a" or "an" located in front of the element does not exclude the presence of multiple such
Element.The present invention can be by means of including the hardware of several different elements and being come by means of properly programmed computer real
It is existing.In the unit claims listing several devices, several in these devices can be through the same hardware branch
To embody.The use of word first, second, and third does not indicate any sequence.These words can be explained and be run after fame
Claim.
Claims (10)
1. a kind of hardware reconstruction system characterized by comprising
Between each resource pool and the resource pool closed on, the multichannel interface based on remote PCI e crossbar switch is connected, in resource pool
Multichannel interface connection based on PCIe crossbar switch, remote PCI e crossbar switch and the PCIe crossbar switch in resource pool, pass through
Shared interface connects together, and forms the double-deck crossbar configuration chain based on PCIe crossbar switch and remote PCI e crossbar switch
Road；
Wherein, the resource pool includes computing resource pool and/or memory resource pool, and each processor passes through in resource pool in resource pool
The PCIe crossbar switch in portion is interconnected, and when being attached configuration, is configured the PCIe inside resource pool by configuration information and is handed over
Fork closes connection relationship, is calculating and storage resource inside the specified PCIe bus assignment resource pool of CPU, realizes computing resource
It is directly connected between pond, memory resource pool inner treater, supports computing resource and the distribution of storage resource dynamic on-demand；
The remote PCI e crossbar switch is interconnected by shared interface and each resource pool, realize the resource pool based on PCIe protocol it
Between point-to-point peer switch, when being attached configuration, by configuration information configure remote PCI e crossbar switch connection relationship,
For the processor resource in the specified PCIe bus assignment Adjacent resource pond of CPU, the calculating and storage resource carried out between resource pool is moved
State distribution.
2. system according to claim 1, which is characterized in that
The shared interface supports two kinds of interface modes of transparent bridge and non-transparent bridge, can be configured to master port or from port,
It is interconnected between realizing port by PCIe shared interface cable.
3. system according to claim 1, which is characterized in that
For PCIe crossbar switch in the resource pool with the realization of PCIe switching backplane, PCIe switching backplane includes multichannel PCIe bus
Slot and PCIe exchange chip.
4. system according to claim 1, which is characterized in that
The remote PCI e crossbar switch realized with PCIe switch, realizes the point-to-point exchanged form between resource pool, including with
It is one of lower or a variety of: packet switch, circuit switching and virtual channel exchange.
5. system according to claim 4, which is characterized in that
The virtual channel exchange is handed over for forming multiple virtual circuits for sharing the same physical channel by virtual channel
Connection is changed, and virtual circuit exchange connection can connect cooperation with packet switch connection and circuit switching to transmit flow data.
6. system according to claim 4, which is characterized in that further include compiler；
The compiler for being every known flow allocation of communications path according to known internuclear stream communication situation, and determines empty
Quasi- circuit switching connection, circuit switching connection are connected with packet switch, at runtime according to communication compiling as a result, the company by prestoring
It connects information and establishes each exchange connection, the communication between different resource pond is transmitted in corresponding exchange connection.
7. system according to claim 1, which is characterized in that
The remote PCI e crossbar switch includes multiple input units, and a crossbar switch crosses over unit, and path-calculating element is empty
Quasi- channel assignment unit, crossbar switch allocation unit and circuit configuration unit；
The input unit, for the virtual channel number after the PCIe device configuration output arbitration for connection, each input unit
It is described including n output virtual channel VC1-VCn, a bypass channel, a PS state storage and a VCS state storage
Input unit exchanges VCS signal with the input virtual channel of PCIe device and port input signal is connected, and the storage of PS state corresponds to
The virtual channel state of basic packet switch router, VCS state stores corresponding virtual circuit and exchanges connection status, when input is
When VCS signal, then the corresponding output virtual channel number of input virtual channel is directly found by the information in the storage of VCS state,
VCS signal is directly output to the corresponding PCIe device of output virtual channel number, and each input unit increases a bypass and leads to
Unit is crossed over to allow packet switched data piece to be directly inputted to the crossbar switch in road；
The path-calculating element is handed over for transmission in packet for establishing the port ID- routed path or address: Port routed path
The data slice for changing connection provides path arbitration result；
The virtual channel allocation unit is deposited for the path arbitration result according to the path-calculating element or according to PS state
Information is stored up, for input data piece distribution output virtual channel number；
The circuit configuration unit, for providing the crossbar configuration prestored letter in the data slice that circuit switching connects to transmit
Breath；
The crossbar switch allocation unit stores information for storing preset circuit configuration by circuit configuration, directly to friendship
Fork put capable configuration into, allow circuit switching connect data slice directly by by-pass switch enter the crossbar switch across
More unit；
Data packet is output to defeated across unit for the arbitration scheduling result according to the input unit by the crossbar switch
The corresponding PCIe device of virtual channel number out.
8. system according to claim 1, which is characterized in that
The computing resource pool includes one of following or a variety of: CPU, GPU, FPGA, IPU.
9. system according to claim 1, which is characterized in that
The memory resource pool includes one of following or a variety of: SSD, HDD.
10. a kind of hardware reconstruction method, which is characterized in that hardware reconstruction system of any of claims 1-9 is applied,
Include:
Step 1: PCIe bus being scanned by management node, acquisition is connected in PCIe multibus and pond on PCIe crossbar switch
PCIe device port information, wherein the management node is preset cpu node；
Step 2: the remote PCI e crossbar switch of PCIe crossbar switch shared interface connection in pond where management node obtains
PCIe device port information；
Step 3: the hardware such as CPU, GPU, FPGA, IPU, SSD, HDD for specifying PCIe bus to connect according to user requirements analysis are set
Standby type and quantity；
Step 4: the type and quantity of the hardware device according to needed for step 3 judge in local computing and memory resource pool
Whether resource is enough, and step 5 is transferred to if enough, not enough, is transferred to step 7；
Step 5: management node configures the configuration space of the PCIe crossbar switch in resource pool, according to depth-first search
Algorithm is that specified PCIe bus configuration distributes required processor, PCIe crossbar switch in configured pool, and is connected to PCIe in pond
Principal and subordinate's bus of device port, the information such as command register are managed everywhere in crossbar switch；
Step 6: PCIe data packet needed for constructing the present invention by the packet format of PCIe DMA or the PCIe link layer protocol of standard,
The equipment for being connected to specified PCIe bus is accessed, the configuration of PCIe hardware reconstruction is terminated；
Step 7: management node configures the configuration space of the PCIe crossbar switch in resource pool, for specified PCIe bus point
With available calculating and storage resource；
Step 8: management node configures remote PCI e crossbar switch, and it is logical to carry out empty exchange according to remote PCI e crossbar switch
Road, packet switch channel, circuit-switched channels configuration, support two kinds of connecting interfaces of transparent bridge and non-transparent bridge, adjacent needed for connection
Calculating and memory resource pool；
Step 9: management node is processing needed for specified PCIe bus assignment local resource pond according to Depth Priority Algorithm
Device, processor needed for selected adjacent resource pool, in configured pool/remote PCI e crossbar switch, and it is connected to PCIe crossbar switch
Everywhere in manage principal and subordinate's bus of device port, information such as command register, and be transferred to step 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811113981.5A CN109240832B (en) | 2018-09-25 | 2018-09-25 | Hardware reconfiguration system and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811113981.5A CN109240832B (en) | 2018-09-25 | 2018-09-25 | Hardware reconfiguration system and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109240832A true CN109240832A (en) | 2019-01-18 |
| CN109240832B CN109240832B (en) | 2022-04-19 |
Family
ID=65056108
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811113981.5A Active CN109240832B (en) | 2018-09-25 | 2018-09-25 | Hardware reconfiguration system and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109240832B (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111552562A (en) * | 2020-04-13 | 2020-08-18 | 中国电子科技集团公司电子科学研究院 | Reconstruction configuration method and device for heterogeneous server |
| CN111880911A (en) * | 2020-06-19 | 2020-11-03 | 浪潮电子信息产业股份有限公司 | Task load scheduling method, device and equipment and readable storage medium |
| CN112731823A (en) * | 2019-10-28 | 2021-04-30 | 深圳市国微电子有限公司 | FPGA interconnection line circuit and FPGA interconnection line delay reduction method |
| CN113395216A (en) * | 2020-03-11 | 2021-09-14 | 辉达公司 | Techniques to transfer data between hardware devices |
| CN113452731A (en) * | 2020-03-25 | 2021-09-28 | 阿里巴巴集团控股有限公司 | Resource allocation method, device, electronic equipment and computer readable storage medium |
| CN114445260A (en) * | 2022-01-17 | 2022-05-06 | 苏州浪潮智能科技有限公司 | Distributed GPU communication method and device based on FPGA |
| WO2023098295A1 (en) * | 2021-11-30 | 2023-06-08 | 中兴通讯股份有限公司 | Radio frequency chip, algorithm reconstruction method, and computer readable storage medium |
| CN116594785A (en) * | 2023-07-18 | 2023-08-15 | 四川华鲲振宇智能科技有限责任公司 | Hardware-based server paravirtualization method |
| CN117687956A (en) * | 2024-01-31 | 2024-03-12 | 苏州元脑智能科技有限公司 | Multi-acceleration-card heterogeneous server and resource link reconstruction method |
| WO2024088263A1 (en) * | 2022-10-25 | 2024-05-02 | 杭州阿里云飞天信息技术有限公司 | Heterogeneous server system and use method thereof |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5850395A (en) * | 1995-07-19 | 1998-12-15 | Fujitsu Network Communications, Inc. | Asynchronous transfer mode based service consolidation switch |
| US7181578B1 (en) * | 2002-09-12 | 2007-02-20 | Copan Systems, Inc. | Method and apparatus for efficient scalable storage management |
| US20080229326A1 (en) * | 2007-01-26 | 2008-09-18 | Objective Interface Systems, Inc. | Hardware communications infrastructure supporting location transparency and dynamic partial reconfiguration |
| CN101630305A (en) * | 2008-07-16 | 2010-01-20 | 中国人民解放军信息工程大学 | Flexible management method for reconfigurable components in high-efficiency computer |
| CN106897581A (en) * | 2017-01-25 | 2017-06-27 | 人和未来生物科技（长沙）有限公司 | A kind of restructural heterogeneous platform understood towards gene data |
| CN107786198A (en) * | 2016-08-25 | 2018-03-09 | 富士施乐株式会社 | Reconfigurable logic circuit |
-
2018
- 2018-09-25 CN CN201811113981.5A patent/CN109240832B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5850395A (en) * | 1995-07-19 | 1998-12-15 | Fujitsu Network Communications, Inc. | Asynchronous transfer mode based service consolidation switch |
| US7181578B1 (en) * | 2002-09-12 | 2007-02-20 | Copan Systems, Inc. | Method and apparatus for efficient scalable storage management |
| US20080229326A1 (en) * | 2007-01-26 | 2008-09-18 | Objective Interface Systems, Inc. | Hardware communications infrastructure supporting location transparency and dynamic partial reconfiguration |
| CN101711467A (en) * | 2007-01-26 | 2010-05-19 | 目标接口系统公司 | A hardware communications infrastructure supporting location transparency and dynamic partial reconfiguration |
| CN101630305A (en) * | 2008-07-16 | 2010-01-20 | 中国人民解放军信息工程大学 | Flexible management method for reconfigurable components in high-efficiency computer |
| CN107786198A (en) * | 2016-08-25 | 2018-03-09 | 富士施乐株式会社 | Reconfigurable logic circuit |
| CN106897581A (en) * | 2017-01-25 | 2017-06-27 | 人和未来生物科技（长沙）有限公司 | A kind of restructural heterogeneous platform understood towards gene data |
Non-Patent Citations (2)
| Title |
|---|
| 吴雄洲: "基于多层树形结构的PCIE总线配置技术研究", 《 航空计算技术》 * |
| 无: "Product Brief PEX8796. PLX Technology", 《HTTPS://HTML.ALLDATASHEET.COM/HTML-PDF/1079816/PLX/PEX8796/62/1/PEX8796.HTML》 * |
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112731823A (en) * | 2019-10-28 | 2021-04-30 | 深圳市国微电子有限公司 | FPGA interconnection line circuit and FPGA interconnection line delay reduction method |
| CN113395216B (en) * | 2020-03-11 | 2024-04-09 | 辉达公司 | Techniques for transferring data between hardware devices |
| CN113395216A (en) * | 2020-03-11 | 2021-09-14 | 辉达公司 | Techniques to transfer data between hardware devices |
| US11995023B2 (en) | 2020-03-11 | 2024-05-28 | NVIDIA Technologies, Inc. | Techniques to transfer data among hardware devices |
| CN113452731A (en) * | 2020-03-25 | 2021-09-28 | 阿里巴巴集团控股有限公司 | Resource allocation method, device, electronic equipment and computer readable storage medium |
| CN113452731B (en) * | 2020-03-25 | 2022-04-29 | 阿里巴巴集团控股有限公司 | Resource allocation method, device, electronic equipment and computer readable storage medium |
| CN111552562B (en) * | 2020-04-13 | 2022-10-28 | 中国电子科技集团公司电子科学研究院 | Reconstruction configuration method and device for heterogeneous server |
| CN111552562A (en) * | 2020-04-13 | 2020-08-18 | 中国电子科技集团公司电子科学研究院 | Reconstruction configuration method and device for heterogeneous server |
| CN111880911A (en) * | 2020-06-19 | 2020-11-03 | 浪潮电子信息产业股份有限公司 | Task load scheduling method, device and equipment and readable storage medium |
| WO2023098295A1 (en) * | 2021-11-30 | 2023-06-08 | 中兴通讯股份有限公司 | Radio frequency chip, algorithm reconstruction method, and computer readable storage medium |
| CN114445260B (en) * | 2022-01-17 | 2024-01-12 | 苏州浪潮智能科技有限公司 | Distributed GPU communication method and device based on FPGA |
| CN114445260A (en) * | 2022-01-17 | 2022-05-06 | 苏州浪潮智能科技有限公司 | Distributed GPU communication method and device based on FPGA |
| WO2024088263A1 (en) * | 2022-10-25 | 2024-05-02 | 杭州阿里云飞天信息技术有限公司 | Heterogeneous server system and use method thereof |
| CN116594785B (en) * | 2023-07-18 | 2023-09-15 | 四川华鲲振宇智能科技有限责任公司 | Hardware-based server paravirtualization method |
| CN116594785A (en) * | 2023-07-18 | 2023-08-15 | 四川华鲲振宇智能科技有限责任公司 | Hardware-based server paravirtualization method |
| CN117687956A (en) * | 2024-01-31 | 2024-03-12 | 苏州元脑智能科技有限公司 | Multi-acceleration-card heterogeneous server and resource link reconstruction method |
| CN117687956B (en) * | 2024-01-31 | 2024-05-07 | 苏州元脑智能科技有限公司 | Multi-acceleration-card heterogeneous server and resource link reconstruction method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109240832B (en) | 2022-04-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109240832A (en) | A kind of hardware reconstruction system and method | |
| CN105279133B (en) | VPX Parallel DSP Signal transacting board analysis based on SoC on-line reorganizations | |
| CN104247341B (en) | The dynamic optimization method of distribution switch and its multicast tree hierarchical structure | |
| CN103345461A (en) | Multi-core processor on-chip network system based on FPGA and provided with accelerator | |
| CN107111576A (en) | The interruption framework of issue | |
| US11269801B2 (en) | System decoder for training accelerators | |
| CN101739241A (en) | On-chip multi-core DSP cluster and application extension method | |
| CN107707491A (en) | Device and method for realizing multilevel on-chip interconnection | |
| CN104636301B (en) | A kind of extensive PLC High speed rear panels bus system based on PCI E interfaces | |
| CN106469127B (en) | A kind of data access device and method | |
| EP2641189A1 (en) | Unified network architecture for scalable super-calculus systems | |
| Saponara et al. | Design of an NoC interface macrocell with hardware support of advanced networking functionalities | |
| US10896476B2 (en) | Repository of integration description of hardware intellectual property for NoC construction and SoC integration | |
| US11714776B2 (en) | Enabling a multi-chip daisy chain topology using peripheral component interconnect express (PCIe) | |
| CN107851078A (en) | A kind of method and system of the polymerization friendly address distribution of PCIe device | |
| GB2502861A (en) | Network-on-chip comprising distributed reorder buffers | |
| CN109194578A (en) | A kind of activating method and device of private line service | |
| US8352695B2 (en) | Selectable access rates in a memory and memory communication system | |
| CN108874730A (en) | A kind of data processor and data processing method | |
| CN104834566B (en) | Adjust the method and relevant apparatus of the switching port of forward process thread | |
| Wiklund et al. | Design of a system-on-chip switched network and its design support | |
| CN207182023U (en) | The network control board and modular instrument for being controlled and being communicated based on network | |
| CN107451427A (en) | The computing system and accelerate platform that a kind of restructural gene compares | |
| Zitouni et al. | Communication architecture synthesis for multi-bus SoC | |
| CN107920035A (en) | It is designed to the processor of certainty switching Ethernet |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |