CN203377863U

CN203377863U - FPGA interconnection structure with optimized area

Info

Publication number: CN203377863U
Application number: CN201320357469.1U
Authority: CN
Inventors: 崔运东; 王潘丰; 刘成利
Original assignee: Capital Microelectronics Beijing Technology Co Ltd
Current assignee: Capital Microelectronics Beijing Technology Co Ltd
Priority date: 2013-06-21
Filing date: 2013-06-21
Publication date: 2014-01-01
Anticipated expiration: 2023-06-21

Abstract

The utility model brings forward an FPGA interconnection structure with an optimized area. The FPGA interconnection structure comprises a first-stage multiplexer and at least another-stage multiplexer; and the output signal of the first-stage multiplexer forms the input signal of the at least another-stage multiplexer. The at least another-stage multiplexer includes a plurality of multiplexer units having the same multi-digit first input signals. Multi-digit data pathways pass through the basically same winding paths and specifically, the time delays of all the pathways are basically identical, thereby ensuring normal data transmission; and the design area between the multiplexers with the same inputs is reduced.

Description

A kind of area-optimized FPGA interconnection structure

Technical field

The present invention relates to the FPGA interconnection structure, more particularly relate to area-optimized FPGA interconnection structure.

Background technology

There are many application requirements integrated circuits to there is internet able to programme or configurable.Such application is field programmable gate array (Field programmable gate array is called for short FPGA), and wherein, gate is connected to each other by configurable internet.As the FPGA that in individual chips or system, work in core, extensively be applied in a large amount of microelectronic devices.

In the middle of the basic structure of FPGA, it is very extensive that multiplexer (MUX) is applied.Multiplexer is the basic interconnection unit that forms FPGA, and FPGA has 80% area to be taken by interconnecting unit usually.Therefore the area that reduces the basic interconnection unit has very important meaning for the entire area that reduces fpga chip.

The structural representation that Fig. 1 is common FPGA interconnection structure 64 * 1 multiplexers that adopt in prior art.As shown in Figure 1, this structure adopts the two-stage multiplexer to realize, wherein the first order selects 1 multiplexer to form by 16 4, and in this first order, all 4 select 1 multiplexer to share identical configuration bit, and the second level selects 1 multiplexer to form by one 16.

The structural representation that Fig. 2 is common FPGA interconnection structure 64 * 4 multiplexers that adopt in prior art.As shown in Figure 2, this structure adopts four groups of FPGA interconnection structures, 64 * 1 multiplexers to form, and this structure has taken larger chip area.

The present invention, according to the layout design characteristics of multiplexer, has designed a kind of interconnection structure (xbar), can effectively reduce the area of interconnecting unit.

Summary of the invention

The purpose of this invention is to provide the FPGA interconnection structure that can overcome above problem.

The invention provides a kind of FPGA interconnection structure, comprise: first order multiplexer and another grade of multiplexer at least, wherein the output signal of first order multiplexer forms the input signal of described at least another grade of multiplexer; Described at least another grade of multiplexer comprises a plurality of multiplexers, and described a plurality of multiplexers have identical multidigit the first input signal.

First order multiplexer is organized secondary multiplexer by N and is formed, every group of secondary multiplexer configuration sharing position.Secondary multiplexer is comprised of M group multiplexer, and described M group multiplexer has identical multidigit the second input signal.

The accompanying drawing explanation

Fig. 1 is the structural representation of FPGA interconnection structure 64 * 1 multiplexers in prior art;

Fig. 2 is the structural representation of FPGA interconnection structure 64 * 4 multiplexers in prior art

Fig. 3 is the structural representation of FPGA interconnection structure 64 * 4 multiplexers of the embodiment of the present invention; ;

Fig. 4 is the structural representation of the second level multiplexer shown in Fig. 3;

Fig. 5 is the source that adopts in embodiment-leakage technology of sharing figure;

Fig. 6 be the multiplexer part of the second level shown in Fig. 4 design layout;

Fig. 7 is the structural representation of the first order multiplexer shown in Fig. 3;

Fig. 8 is the structural representation of FPGA interconnection structure 64 * 32 multiplexers of the embodiment of the present invention;

Embodiment

Below by drawings and Examples, technical scheme of the present invention is described in further detail.

Fig. 3 is the structural representation according to FPGA interconnection structure 64 * 4 multiplexers of the embodiment of the present invention.As shown in Figure 3, this structural system has 64 input signals and 4 output signals, the two-stage multiplexer, consists of.

64 signals of input are separated into four groups of 16 signals, and every group of 16 signals are separated into again the input signal of four groups of 4 signals as first order multiplexer.First order multiplexer comprises four groups of secondary multiplexers, and every group of secondary multiplexer comprise 44 and select 1 multiplexer configuration sharing position, and every group of secondary multiplexer inputted one group of 16 signal and exported one group of 4 signal.Four groups of 4 signals of first order multiplexer output form one group of 16 signal and as the input signal of second level multiplexer after stack.

Second level multiplexer selects 1 multiplexer to form by four 16, and each 16 selects 1 multiplexer to input one group of 16 signal and export four groups of 1 signals, and these four groups of 1 signals form the output signal of one group of 4 signal as system after stack.It is identical wherein being input to every group 16 and selecting 16 signals of 1 multiplexer.

Fig. 4 is the structural representation of the multiplexer of the second level shown in Fig. 3.As shown in Figure 4, have four groups of (OK) 4 of arranging from top to bottom to select 1 multiplexer, every group is comprised of multiplexer s0, multiplexer s1, multiplexer s2, multiplexer s3 and multiplexer s4.

In every group 4 is selected 1 multiplexer, multiplexer s0, multiplexer s1, multiplexer s2 and multiplexer s3 configuration sharing position.Multiplexer s0 receives input signal X0_0, X1_0, X2_0 and X3_0, output Y0_0; Multiplexer s1 receives input signal X0_1, X1_1, X2_1 and X3_1, output Y0_1; Multiplexer s2 receives input signal X0_2, X1_2, X2_2 and X3_2, output Y0_2; Multiplexer s3 receives input signal X0_3, X1_3, X2_3 and X3_3, output Y0_3.Under the control of identical configuration bit, multiplexer s0, multiplexer s1, multiplexer s2 and multiplexer s3 select the input signal of same position as output separately.Output signal Y0<0:3 > select 1 signal through multiplexer s4, realize that thus one 16 is selected 1 multiplexer.

As can be seen from Fig. 4, due to not on the same group but column position identical 4 select 1 multiplexer s0-s3 to adopt identical input signal, not on the same group 4 select 41 different signals of 1 multiplexer s4 output, each is organized 4 and selects 16 of the actual formation of 1 multiplexer to select 1 multiplexer to have identical 16 inputs and 1 different output.Therefore, 4 group 4 shown in Fig. 4 selects the second level 16 in the common pie graph 3 of 1 multiplexer to select 4 multiplexers.

Being different from prior art the input of each multiplexer in the multiplexer of the second level is different characteristics, not on the same group but the input signal of the identical multiplexer of column position is identical, the input signal that for example selects 1 multiplexer s0 for four 4 is identical in embodiments of the present invention.If replace to form these not on the same group but source electrode position and the drain locations of the adjacent transistor of the identical multiplexer of column position the transistorized same node point after replacing is shared, can reduce the minimum range between node, thereby effectively reduce not the minimum range between multiplexer on the same group, saved design area.

Fig. 5 is the source that adopts in embodiment-leakage technology of sharing figure.As shown in Fig. 6 A, be four group transistors (I II III IV), wherein A is source electrode, and B is drain electrode, and C is grid.Transistorized grid is equivalent to the configuration bit of multiplexer, for controlling the output signal of multiplexer; Transistorized source electrode and drain electrode are equivalent to input and the output of multiplexer, for input signal and output signal.For instance, the I group transistor can be corresponding to the 1st group of multiplexer s0-s3 in Fig. 5 respectively to the selection of X0_0-X3_0, X0_1-X3_1, X0_2-X3_2 and X0_3-X3_3.When transistorized input is different, essentially between the different node of adjacent transistor keep a minimum range.

Mention above not on the same group but the identical multiplexer s0-s3 of column position has identical input signal, this means, adjacent sets (for example I and II group) is if transistorized drain electrode B(selects B as input as) can there is identical signal.As shown in Figure 6B, in order to save area, source electrode and the drain electrode of the transistor of being separated by (II and IV or I and III) can be carried out to the position exchange, the transistorized adjacent node that the transistor AND gate after source electrode and drain locations exchange is adjusted is identical.As shown in Figure 6 C, because transistorized input is identical, therefore the same node point of adjacent transistor can be shared and formed area-optimized transistor arrangement, this structure has been avoided the minimum range between transistor node, can effectively save area.

Fig. 6 is the design layout of the multiplexer part of the second level shown in Fig. 4.Be illustrated in figure 6 two groups of multiplexer s0-s3 adjacent in the second level multiplexer of Fig. 4.Hereinafter take first group and second group of multiplexer is example.X representative input in the drawings, Xm_n means respectively organizing m input of n row multiplexer in Fig. 4; S represents output, and in Sp_q presentation graphs 4, p is listed as the output of q group multiplexer.

S0_1, X0_0 and between configuration bit form a transistor; S1_1, X0_1 and between configuration bit form a transistor; S2_1, X0_2 and between configuration bit form a transistor; S3_1, X0_3 and between configuration bit form a transistor.This first row transistors share configuration bit.

In like manner, X0_0 and S0_0, X0_1 and S1_0, X0_2 and S2_0, X0_3 and S3_0 form respectively a transistor.This second row transistors share configuration bit.

First row transistor and second row transistor have common input signal, so share identical input node.Thus, can reduce the minimum range between the different nodes of adjacent transistor, thereby effectively reduce not the design area between multiplexer on the same group.

Due to every group of multiplexer configuration sharing position, can effectively reduce the design area that provides the separate configurations position to increase for multiplexer when configuration bit is not identical.

Fig. 7 is the structural representation of the first order multiplexer shown in Fig. 3.Have as shown in Figure 7 four groups of (OK) 4 of arranging from top to bottom to select 1 multiplexer, every group is comprised of multiplexer z0, multiplexer z1, multiplexer z2 and multiplexer z3.

In every group 4 is selected 1 multiplexer, multiplexer z0, multiplexer z1, multiplexer z2 and multiplexer z3 configuration sharing position.Multiplexer z0 receives input signal I0_0, I1_0, I2_0 and I3_0, output X0_0; Multiplexer z1 receives input signal I0_1, I1_1, I2_1 and I3_1, output X0_1; Multiplexer z2 receives input signal I0_2, I1_2, I2_2 and I3_2, output X0_2; Multiplexer z3 receives input signal I0_3, I1_3, I2_3 and I3_3, output X0_3.Under the control of identical configuration bit, multiplexer s0, multiplexer s1, multiplexer s2 and multiplexer s3 select the input signal of same position as output separately.Output signal X0<0:3 >, realize that thus one 16 is selected 4 multiplexer.

As can be seen from Fig. 7, due to not on the same group but column position identical 4 select 1 multiplexer z0-z3 to adopt identical input signal, export 41 different signals, each is organized 4 and selects 16 of the actual formation of 1 multiplexer to select 4 multiplexers to have identical 16 inputs and 4 different outputs.Therefore, 4 group 4 shown in Fig. 7 selects the first order 16 in the common pie graph 3 of 1 multiplexer to select 4 multiplexers.

Although the first order multiplexer of the embodiment of the present invention can increase because of the difference of every assembly set certain design area with respect to the first order multiplexer of prior art, but 4 groups of 16 signals that the first order multiplexer that uses 4 groups of configuration sharing positions in the total input signal that 4 groups of 4 signals that produce due to this first order multiplexer are second level multiplexer rather than prior art produces are respectively as 4 group of 16 input signal that selects 1 multiplexer of second level multiplexer, therefore can reduce approximately the design area of 3/4ths first order multiplexer, thereby effectively reduced the global design area of FPGA interconnection structure.

Fig. 8 is the structural representation of FPGA interconnection structure 64 * 32 multiplexers of the embodiment of the present invention.

In a preferred example, the FPGA interconnection structure is 64 * 32 multiplexers.This structural system has 64 input signals and 32 output signals as shown in Figure 8, the two-stage multiplexer, consists of.

64 signals of input are separated into four groups of 16 signals, and every group of 16 signals are separated into again the input signal of four groups of 4 signals as first order multiplexer.First order multiplexer is comprised of four groups of secondary multiplexers, and every group of secondary multiplexer comprises again 8 groups, and each group selects 1 multiplexer to form and the configuration sharing position by 44.Each group of first order multiplexer exports one group of 4 signal, and every group of secondary multiplexer exported four groups of 4 signals altogether, and these four groups of 4 signals form the input signal of 16 signals as second level multiplexer after stack.

Second level multiplexer is comprised of 8 groups of multiplexers, and every group of multiplexer selects 1 multiplexer to form by 4 16.Each 16 selects 1 multiplexer to be chosen and export one group of 1 signal by 16 signals to the output of input first order multiplexer, four groups of 1 signals of every group of multiplexer output form the output signal of 4 signals as system after stack, and this second level multiplexer can produce eight groups of 4 signals altogether.Wherein being input to each, 16 to select 16 signals of 1 multiplexer be identical.

In another preferred example, the FPGA interconnection structure is 128 * 4 multiplexers.This structural system has 128 input signals and 4 output signals, three grades of multiplexers, consists of.

128 input signals of input are input to first order multiplexer, first order multiplexer by four groups separately the configuration sharing position 32 select 16 multiplexers to form, this 32 selects 16 multiplexers to choose 16 signals as output signal from one group of 32 signal of input, and four groups of 16 signals are as the input signal of second level multiplexer.

Second level multiplexer by four groups separately the configuration sharing position 16 select 4 multiplexers to form, this 16 selects 4 multiplexer to choose 4 signals as output signal from one group of 16 signal of input, and four groups of 4 signals of second level multiplexer output are the input signal as third level multiplexer through one group of 16 signal of stack aftershaping.Wherein being input to each, 16 to select 16 signals of 4 multiplexer be identical.

Third level multiplexer by four groups separately the configuration sharing position 16 select 1 multiplexer to form, this 16 selects 1 multiplexer to choose 1 signal as output signal from one group of 16 signal of input, third level multiplexer export altogether four groups of 1 signals through one group of 4 signal of stack aftershaping as output signal.Wherein being input to each, 16 to select 16 signals of 1 multiplexer be identical.

It is to be noted in another utmost point multiplexer at least, have at least the one-level multiplexer to adopt a plurality of multiplexers in the present invention to have the structure of identical input signal, preferred non-first order multiplexer can all adopt this structure to reduce design area.First order multiplexer adopts other interconnection structure also to reach identical technique effect, and preferred first order multiplexer can adopt a plurality of multiplexers in the present invention to have the structure of identical input signal to reduce design area.

Above-described embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the foregoing is only the specific embodiment of the present invention; the protection range be not intended to limit the present invention; within the spirit and principles in the present invention all, any modification of making, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.

Claims

1. a FPGA interconnection structure comprises: first order multiplexer and another grade of multiplexer at least, and wherein first order multiplexer is electrically connected to another grade of multiplexer at least; Described at least another grade of multiplexer comprises a plurality of multiplexers.

2. FPGA interconnection structure according to claim 1, is characterized in that described first order multiplexer organizes secondary multiplexer by N and form.

3. FPGA interconnection structure according to claim 2, is characterized in that described secondary multiplexer is comprised of M group multiplexer.