JP2008288559A - Semiconductor integrated circuit and method of laying out the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit which has little power consumption and small clock skew, and comprises a clock distribution circuit with small load capacities of a clock driving cell for supplying clock signal even in a large scale semiconductor integrated circuit. <P>SOLUTION: In the semiconductor integrated circuit, a function block 100 is divided into a plurality of regions, the semiconductor integrated circuit is provide with a clock main wiring (11, etc.) wired in a first direction in each of region, a clock branch wiring group (12, etc.) wired in a second direction normal to the first direction and comprising a plurality of clock branch wirings electrically connected to the clock main wiring, a clock driving cell (13, etc.) electrically connected to the clock main wiring, and a clock synchronous cell group (14, etc.) comprising a plurality of clock synchronous cells electrically connected to the clock main wiring or the clock branch wiring group. Each of clock branch wiring groups is electrically isolated each other, only the clock driving cell drives the clock main wring connected to it and the clock branch wring group connected to the clock main wring. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit using a clock distribution circuit that distributes a clock signal in a functional block configured using standard cells, and a layout method of the semiconductor integrated circuit.

  In recent years, with the increase in speed and functionality of digital circuits, the speed and integration of semiconductor integrated circuits have been increasing.

  As the speed of semiconductor integrated circuits has increased, it has become important to suppress variations in signal delay (clock skew) of clock signals that synchronize flip-flops in the semiconductor integrated circuit. The clock skew is a difference in arrival time of clock signals between synchronized flip-flops. If the clock skew is large, there is a problem that the operating frequency is lowered and further a malfunction of the circuit is caused.

  Further, in order to highly integrate a semiconductor integrated circuit, it is necessary to miniaturize the manufacturing process. For this reason, the signal wiring width used in the semiconductor integrated circuit is becoming narrower year by year, and the wiring delay is increased due to an increase in wiring resistance.

  Conventionally, since the wiring delay was small, clock skew due to variations in cell gate delay was dominant. However, in recent years, an increase in clock skew due to an increase in variation in wiring delay has become a problem, and it has become necessary to reduce variations in the wiring delay of clock signals.

  As a conventional clock wiring structure for reducing variation in clock signal wiring delay, for example, there are clock wiring techniques such as comb clock wiring, fishbone clock wiring, and mesh clock wiring (for example, Patent Document 1 and Patent Document 2). See).

Further, as a technique for reducing the clock signal wiring delay in the semiconductor integrated circuit, there is a technique described in Patent Document 3.
JP-A-9-283631 JP-A-10-199985 JP 2003-332430 A

  However, the comb-shaped clock wiring prevents the operation speed from decreasing by controlling the variation in wiring delay so that the circuit does not malfunction, but if the flip-flops on the signal output side and the reception side are one to one, Although variations in wiring delay can be controlled, a general circuit has a many-to-many relationship, so it is difficult to control variations in wiring delay for all the flip-flops.

  Fishbone clocks were effective when the chip size was small, but in large-scale semiconductor integrated circuits, the horizontal branch lines are long and the wiring resistance from the center to the end of the branch lines is very high. There is a problem that the clock skew increases at the center and the periphery of the chip due to variations in wiring delay. In addition, since a large number of clock synchronization cells are connected to the clock trunk wiring as loads, there is also a problem that the variation in the wiring delay of the clock trunk wiring portion becomes large.

  In addition, since the mesh type clock is wired in a grid pattern throughout the block, the wiring resistance is small and the variation in wiring delay is small, but the total clock length is long and the load of the clock driving cell that supplies the clock signal is large. There is a problem that the capacity increases and the power consumption increases.

In addition, the comb clock wiring, the fishbone clock wiring, and the mesh clock wiring both have a very large load capacity because the clock signal to the clock synchronous cell of the entire block is driven by one clock wiring.
Therefore, it is necessary to drive the entire clock wiring simultaneously with a plurality of clock driving cells. In this case, if there is a clock skew up to a plurality of clock driving cells, there is a problem that a through current flows between the clock driving cells through the fishbone type clock wiring or mesh wiring portion, resulting in an increase in power consumption.

  In addition, with the standard cell level delay calculation tools currently on the market, when one clock wiring is driven by multiple clock driving cells in this way, the delay calculation cannot be performed accurately. There is a problem that the influence of crosstalk cannot be considered.

  In addition, if you want to use an upper layer wiring with a high film pressure and low resistance to reduce the clock signal wiring delay, it is necessary to use a wider wiring due to manufacturing process restrictions, or connect the wiring layer to the upper layer wiring Since the signal wiring area is insufficient when used for the entire clock wiring due to the large contact to be made, it is difficult to use the upper layer wiring on the end side of the clock tree for driving a large number of clock driving cells or clock synchronous cells.

  The present invention has been made paying attention to the above-mentioned problems. The clock distribution has low power consumption and clock skew, and the load capacity of the clock driving cell for supplying the clock signal is small even in a large-scale semiconductor integrated circuit. It aims to provide a circuit.

In order to solve the above problems, one embodiment of the present invention provides:
A semiconductor integrated circuit using a clock distribution circuit that distributes a clock signal in a functional block configured using standard cells,
A first clock trunk wiring wired in a first direction;
A first clock branch wiring group comprising a plurality of clock branch wirings wired in a second direction orthogonal to the first direction and electrically connected to the first clock backbone wiring;
A first clock driving cell electrically connected to the first clock backbone wiring;
A first clock synchronization cell group comprising a plurality of clock synchronization cells electrically connected to the first clock backbone wiring or the first clock branch wiring group;
A second clock trunk wiring arranged in parallel with the first clock trunk wiring;
A second clock branch line group consisting of a plurality of clock branch lines wired in the second direction and electrically connected to the second clock backbone line;
A second clock driving cell electrically connected to the second clock backbone wiring;
A second clock synchronization cell group consisting of a plurality of clock synchronization cells electrically connected to the second clock backbone wiring or the second clock branch wiring group;
A clock source driver for supplying a clock signal to the first clock driving cell and the second clock driving cell;
The first clock branch line group and the second clock branch line group are electrically separated,
Driving the first clock trunk wiring and the first clock branch wiring group only by the first clock driving cell;
The clock distribution circuit is characterized in that the second clock trunk wiring and the second clock branch wiring group are driven only by the second clock driving cell.

  According to the present invention, power consumption and clock skew can be reduced, and the load capacity of a clock driving cell can be reduced even in a large-scale semiconductor integrated circuit.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description of each embodiment, components having the same functions as those described once are given the same reference numerals and description thereof is omitted.

Embodiment 1 of the Invention
FIG. 1 is a plan view showing a functional block 100 in which a clock distribution circuit according to the present invention is used. The functional block 100 includes a circuit using standard cells. In the standard cell, functions such as an inverter and NAND are implemented by combining a P-channel transistor and an N-channel transistor.

  The functional block 100 is divided into a first area 10 and a second area 20.

  The first region 10 is provided with a clock trunk wiring, a clock branch wiring, and a clock driving cell.

  Specifically, the first clock main wiring 11 is wired in the vertical direction of the center of the first region 10. From the first clock backbone wiring 11, a group of clock branch wirings are wired at equal intervals in the horizontal direction. Note that the center is not necessarily an accurate center. That is, it may be in a range that can be regarded as the center (hereinafter, the vicinity of the center). Here, this group of clock branch lines is referred to as a first clock branch line group 12. In each figure, one clock branch line in the first clock branch line group 12 is represented by a representative symbol.

  Further, an output terminal of a first clock driving cell 13 (described later) disposed near the center of the first region 10 is connected to the vicinity of the center of the first clock trunk wiring 11.

  In the first region 10, a first clock synchronization cell group 14 which is a group of clock synchronization cells (blocks within a dashed ellipse in the figure) is arranged.

  Each clock synchronization cell of the first clock synchronization cell group 14 is electrically connected to the first clock trunk line 11 or the first clock branch line group 12.

  The second region 20 is also provided with a clock trunk line, a clock branch line group, and a clock driving cell.

  Specifically, in the second region 20, a second clock trunk wiring 21 is wired in the vertical direction near the center, and a group of clock branch wirings (second clock branch wiring group) are routed from the second clock trunk wiring 21. 22) are wired at equal intervals in the horizontal direction. In each figure, one clock branch line in the second clock branch line group 22 is represented by a representative symbol.

  Further, the output terminal of the second clock driving cell 23 arranged near the center of the second region 20 is connected to the vicinity of the center of the second clock trunk wiring 21.

  Also in the second region 20, a second clock synchronization cell group 24 that is a group of clock synchronization cells (a block in a dashed ellipse in the drawing) is arranged. Each clock synchronization cell of the second clock synchronization cell group 24 is electrically connected to the second clock trunk line 21 or the second clock branch line group 22.

  The first clock driving cell 13 receives the clock signal output from the clock source driver 25 (described later) as an input, and passes through the first clock trunk line 11 and the first clock branch line group 12 to perform the first clock synchronization. The same clock signal is distributed to each clock synchronization cell of the cell group 14.

  The second clock driving cell 23 receives the clock signal output from the clock source driver 25 as an input, and passes through the second clock trunk line 21 and the second clock branch line group 22 to provide the second clock synchronization cell. The same clock signal is distributed to each clock synchronization cell of the group 24.

  Here, the first clock driving cell 13 to the second clock driving cell 23 are standard cells in which the function of a buffer or an inverter is mounted, and each clock synchronization cell controls the clock supply to the flip-flop at the subsequent stage. Clock control cell or flip-flop.

  The first clock branch line group 12 and the second clock branch line group 22 are electrically separated from each other.

  The clock source driver 25 receives a clock signal from outside the functional block 100 and supplies the clock signal to the first clock driving cell 13 and the second clock driving cell 23.

  As described above, according to the present embodiment, the first clock driving cell 13 includes the first clock trunk line 11, the first clock branch line group 12, and the first clock synchronization in the first region 10. Only the cell group 14 needs to be driven. Therefore, the driving load capacity can be reduced to about half compared to the case of driving the entire clock signal in the functional block. That is, all the first clock synchronization cell groups 14 in the first region 10 can be driven only by the first clock driving cell 13.

  In addition, the second clock driving cell 23 needs to drive only the second clock trunk line 21, the second clock branch line group 22, and the second clock synchronization cell group 24 in the second region 20. Therefore, it is possible to drive all the second clock synchronization cell groups 24 in the second region 20 with only the second clock driving cells 23.

  That is, according to the present embodiment, the number of clock synchronous cells driven by one clock driving cell can be reduced, and as a result, the total wiring length of the clock branch line is also shortened, so that one clock driving cell is driven. Load to be reduced. Therefore, it is possible to drive the clock backbone wiring, the clock branch wiring, and the clock synchronization cell in the region with one high-drive clock driving cell.

  In addition, since the clock wiring structure from the clock driving cell to the clock synchronous cell can be made uniform, variation in wiring delay is small.

  In addition, it is possible to perform delay calculation using a standard cell level delay calculation tool currently on the market. In other words, the standard cell level delay calculation tools that are currently available on the market have a problem that when one signal wiring is driven by a plurality of clock driving cells, the delay calculation cannot be performed correctly and the delay time error is large. is there. Therefore, it is necessary to perform delay calculation only for the comb-shaped clock wiring and mesh wiring using a transistor level simulator, which increases the man-hours required for guaranteeing the timing of the semiconductor integrated circuit, crosstalk, etc. There is a problem that the influence cannot be correctly reflected or the delay calculation accuracy is lowered. However, in this embodiment, since it is driven by one clock driving cell, such a problem can be solved.

  In addition, clock branch lines can be evenly distributed throughout the region, and variations in wiring delay can be reduced regardless of the arrangement of the clock synchronization cells.

  Since the functional block is divided into a plurality of areas, the clock tree can be optimized for each area.

  In the functional block 100, since the functional block is divided in the vertical direction, the first clock main wiring 11 to the second clock main wiring 21 are very long wirings. However, the wiring resistance of the clock trunk wiring can be reduced by wiring the first clock trunk wiring 11 to the second clock trunk wiring 21 using a thick upper layer wiring. Therefore, even when the wiring lengths of the first clock main wiring 11 to the second clock main wiring 21 are long, the clock skew at the center portion and the terminal end portion of the clock main wiring can be extremely reduced. In this case, the distance from the clock backbone wiring to the terminal end of the clock branch wiring is ¼ of the horizontal width of the functional block 100. Therefore, the wiring resistance to the terminal portion of the clock branch wiring is reduced, and the variation in wiring delay between the central portion and the terminal portion of the clock branch wiring can be reduced. That is, the clock skew of the clock trunk wiring and the clock branch wiring can be reduced. Further, when the resistance is small, a large number of clock synchronous cells can be driven at once by a high-drive clock driving cell, and the clock skew can be reduced.

  In addition, the clock trunk wiring is an upper wiring having a large film thickness and a wider wiring, so that the wiring resistance can be further reduced.

  FIG. 2 is a diagram illustrating a connection example of the second clock synchronization cell group 24 in the second region 20. In FIG. 2, the second clock synchronization cell group 24 is arranged in a region determined by the vertical direction of the second clock trunk wiring 21 and the horizontal direction of the second clock branch wiring group 22. The second clock synchronization cell group 24 in the vicinity of the second clock backbone wiring 21 is directly wired to the second clock backbone wiring 21, and the other second clock synchronization cell groups 24 are directed upward or downward. It is directly wired with the clock branch line at the shortest distance. Accordingly, since the wiring portion has a short wiring length from the clock branch wiring or the clock trunk wiring, the wiring delay can be reduced even when a lower-layer wiring having a small thickness is used.

  Further, as shown in FIGS. 1 and 2, it is preferable that the clock branch lines are wired at regular intervals. Thereby, even when the arrangement of the clock synchronization cells varies, the connection can be made in the shortest time.

  3 shows a connection portion between the second clock driving cell 23 and the second clock trunk wiring 21 and a connection portion between the second clock branch wiring group 22 and the second clock synchronization cell group 24 shown in FIG. It is the expanded top view. FIG. 4 is a cross-sectional view of a connection portion between the second clock driving cell 23 and the second clock trunk wiring 21.

  In the example shown in FIGS. 3 and 4, the wiring layer of the functional block 100 is configured by six-layer wiring from the first layer to the sixth layer. Further, contacts for connecting the wiring layers are arranged between the wiring layers.

  The wiring layers from the first layer to the fifth layer are configured to be thin. Therefore, the sheet resistance is large. On the other hand, the film thickness of the sixth wiring layer is more than five times that of the first to fifth layers, and the sheet resistance is 1/5. When the film thickness is increased, it is necessary to widen the wiring width due to restrictions on the manufacturing process. Therefore, the number of the sixth layer that can be used for wiring is reduced. However, it is possible to minimize the use of the upper layer wiring by limiting the use of the thick upper layer wiring only to the clock main wiring. In other words, this structure can limit the use location of the upper layer wiring for the clock signal.

  In the example of FIG. 3, the second clock driving cell 23 is a standard cell in which an inverter function is implemented by a P-channel transistor and an N-channel transistor. In this example, the fifth layer connected to the vicinity of the center of the second clock trunk wiring 21 wired in the sixth layer after being lifted through the contact from the output terminal of the second clock driving cell 23 to the fourth layer. Are connected by a fourth layer wiring.

  The second clock driving cell 23 needs to drive all clock synchronous cells in the second region 20. For this reason, the second clock driving cell 23 has a very high driving capability, current is concentrated from the second clock driving cell 23 to the second clock main wiring 21, and disconnection of wiring due to electromigration becomes a problem. Therefore, it is necessary to reduce the current density of the current flowing through the wiring and the contact from the second clock driving cell 23 to the second clock main wiring 21. For this purpose, the connection is preferably made with a wide wiring and a plurality of contacts. Thereby, the resistance from the clock driving cell to the clock trunk wiring can be reduced. Therefore, a large number of clock synchronous cells can be driven at once by a high-drive clock driving cell, and the clock skew can be reduced.

  In the example of FIG. 4, the second clock trunk wiring 21 includes the second clock branch wiring group 22 wired in the fifth wiring layer, and the second clock synchronous cell group 24 is connected to the clock branch wiring. Up to this point, the connection is made using the wiring from the fourth layer to the second layer. Therefore, since the wiring from the second clock branch wiring group 22 to the second clock synchronization cell group 24 has a short wiring length and a small load capacity connected to the first, it is configured with a wiring having a minimum width due to process restrictions. However, the wiring delay is small.

  In addition, a plurality of clock branch lines are wired from the clock trunk line, and current is distributed from the clock trunk line to the clock branch line. Therefore, the current density can be reduced for the clock branch wiring and the wiring from the clock branch wiring to the clock synchronous cell, and there is no problem with electromigration even with the minimum line width.

  The lower layer wiring has the advantage that a large number of wiring areas can be secured although the resistance is large, and the clock synchronous cell has many cells, so the upper layer wiring and the lower layer wiring use a wide wiring for the wiring from the clock branch line to the clock synchronous cell Then, the wiring area becomes insufficient. However, as described above, the clock drive cell to the upper layer clock trunk wiring are connected using a wide wiring and a plurality of contacts, and only the clock trunk wiring uses a thick upper layer wiring, from the clock branch wiring to the synchronous cell. By using the lower-layer wiring having the minimum width, the wiring resistance on the driver side, which is dominant due to the wiring delay, can be reduced, and both the reduction of clock skew and the securing of the wiring area can be achieved.

<< Embodiment 2 of the Invention >>
FIG. 5 is a plan view showing a functional block 200 according to Embodiment 2 of the present invention. As shown in FIG. 5, the functional block 200 includes four clock branch lines in the first clock branch line group 12 and six clock branch lines in the second clock branch line group 22. As described above, in the first clock branch line group 12, by deleting clock branch lines that do not have a clock synchronous cell in the vicinity, the wiring capacity can be deleted and the power consumption can be reduced.

  In the example of FIG. 5, the first clock driving cell 13 and the second clock driving cell 23 have different load capacitances to drive. Therefore, if the driving capabilities of the first clock driving cell 13 to the second clock driving cell 23 are the same, the signal transition times due to these differ, and the overall clock skew increases.

  Therefore, the driving capability of the clock driving cell may be determined according to the reduction rate of the load capacity driven by the clock driving cell. FIG. 6 is an example of a functional block in which the driving capabilities of the first clock driving cell 13 and the second clock driving cell 23 are different, and the smaller driving capability is shown smaller. In the example of FIG. 6, the driving capability of the first clock driving cell 13 is lowered according to the reduction ratio of the load capacity driven by the first clock driving cell 13. As a result, the power consumption can be reduced while keeping the signal transition times of the first clock driving cell 13 and the second clock driving cell 23 the same.

  Note that after the arrangement of the clock synchronization cells is determined, redundant wiring portions of the clock branch lines can be reduced by wiring the clock branch lines in accordance with the arrangement. As a result, the total wiring length of the clock branch line is also reduced, so that the reduced area can be used for normal signal wiring.

  Further, as shown in FIG. 7, it is preferable that the clock branch line is wired up to the place where the clock synchronization cell is arranged. That is, the first clock branch line group 12 and the second clock branch line group 22 are arranged asymmetrically with the first clock main line 11 and the second clock main line 21 as the center. By this. Wiring load capacity can be reduced and power consumption can be reduced.

  Further, as shown in FIG. 8, it is preferable to change the wiring width of the clock branch wiring in accordance with the wiring length. The wiring length to the clock synchronization cell located far from the clock backbone wiring is long, the wiring delay is increased, and the clock skew is increased. However, by making the clock branch wiring wider in proportion to the wiring length, it is possible to reduce the wiring resistance variation up to the clock synchronization cell, and as a result, to the clock synchronization cell located far from the clock backbone wiring. The clock skew in the clock branch line can be reduced. Conversely, the clock branch line wiring to the clock synchronous cell in the vicinity of the clock backbone wiring can reduce the wiring capacity by narrowing the wiring width.

  A method of wiring the clock branch lines will be described with reference to FIG.

  In FIG. 9, the first region 10 and the second region 20 are each further divided into eight regions. One clock branch line is wired for each area. In the clock branch line wiring, the position of the center of gravity of the clock synchronization cell group in the region is the wiring position in the horizontal direction. Then, a clock branch line is wired from the clock main line to the endmost clock synchronous cell in the area. Thereby, redundant wiring can be deleted and power consumption can be reduced.

<< Embodiment 3 of the Invention >>
In each of the above embodiments, each region (the first region 10 or the like) has the same size. In the third embodiment, an example in which a functional block is divided into regions having different sizes will be described.

  FIG. 10 is a plan view showing a functional block 300 according to Embodiment 3 of the present invention. As shown in FIG. 10, the functional block 300 is divided into a first area 10, a second area 20, and a third area 30.

  In the third region 30, a third clock trunk wiring 31 is wired in the vertical direction near the center. A group of clock branch lines (a third clock branch line group 32) is wired from the third clock main line 31 in the horizontal direction. Further, the output terminal of the third clock driving cell group 33 arranged in the vicinity of the center of the third region 30 is connected to the vicinity of the center of the third clock trunk wiring 31.

  The sizes of the first region 10, the second region 20, and the third region 30 are determined so that the number of clock synchronization cells in each region is the same.

  When the arrangement of the clock synchronization cell group is biased, if the area is divided evenly, an area with a large number of clock synchronization cells and an area with a small number of clock synchronization cells are formed, and the load capacity driven by the clock driving cell differs for each area. In this case, the signal transition times of the clock driving cells are different, and the overall clock skew is increased.

  However, as described above, the number of clock synchronization cells driven by the clock driving cell can be equalized by dividing the region so that the load is equal even when the clock synchronization cell arrangement is biased. . Therefore, even if the driving capabilities of the first clock driving cell 13, the second clock driving cell 23, and the third clock driving cell 33 are the same, the signal transition times are made equal to reduce the overall clock skew. Can do.

  In the example of FIG. 10, the area is divided so that the number of clock synchronization cells in the area is the same, but the sum of the input capacity of the clock synchronization cells and the wiring capacity of the clock wiring in each area is equal. It may be divided.

  FIG. 11 is a diagram illustrating an example of the division of the functional block 300. In the functional block 300, the second area 20 shown in FIG. 1 is further divided into two. This functional block includes a first area 10, a second area 20, and a third area 30 arranged above and below. In the example shown in FIG. 11, the third clock trunk wiring 31 is wired in the first direction below the second clock trunk wiring 21. Here, the lower part refers to the forward direction side or the reverse direction side of the second clock trunk wiring 21 in the first direction (see FIG. 2).

  In this example, the total area of the second region 20 and the third region 30 is equal to the area of the first region 10. The number of cells obtained by adding the number of clock synchronization cells in the second clock synchronization cell group 24 and the number of clock synchronization cells in the third clock synchronization cell group 34 is greater than the number of clock synchronization cells in the first clock synchronization cell group 14. There are also many.

  As described above, there is a bias in the arrangement of the clock synchronization cell group, and the area where the clock synchronization cells are densely arranged is further divided into a plurality of areas, and the clock drive cell provided for each area is divided. To drive.

  Therefore, in the above example, the load capacities driven by the second clock driving cell 23 and the third clock driving cell 33 are reduced, and the first clock driving cell 13, the second clock driving cell 23, the third The load capacity driven by the clock driving cell 33 can be equalized. Furthermore, if the arrangement of the second clock driving cell 23 and the third clock driving cell 33 is the same as the arrangement position of the first clock driving cell 13 in the vertical direction, the clock source driver 25 to the first clock driving cell 13, the wiring distance to the second clock driving cell 23 and the third clock driving cell 33 can be made equal.

  FIG. 12 is an example in which the above clock distribution circuit is applied to a non-rectangular functional block. In this example, the second region 20 is shorter in the vertical direction than the first region 10.

  In this case, the length in the vertical direction is reduced by matching the second clock trunk wiring 21 with the length in the vertical direction of the second region 20. In addition, the second area 20 has a smaller number of lines in the second clock branch line group 22 because the area is smaller. Therefore, the load capacity of the second clock driving cell 23 is reduced. That is, the second clock driving cell 23 can reduce the power consumption while reducing the clock skew by reducing the driving capability according to the load capacity.

  When the horizontal positions of the first clock driving cell 13 and the second clock driving cell 23 are matched, the arrangement of the second clock driving cell 23 is not the center of the second region 20, but the second The clock skew of the clock trunk wiring can be reduced by using a low-resistance upper layer wiring for the clock trunk wiring 21.

  In FIG. 12, the functional block having a non-rectangular shape is described. However, even if the shape is rectangular, the length of the clock trunk wiring may be shortened in the same manner for a portion where there is no clock synchronization cell to be connected. it can.

  Further, in FIG. 12, the case where each area is rectangular has been described, but each area may be non-rectangular. For example, in the example illustrated in FIG. 13, the first region 10 has a non-rectangular shape in which the lower side is longer than the upper side. In this example, the first clock branch line group 12 has a lower wiring length longer than the upper part in accordance with the shape of the first region 10. As a result, the first clock synchronization cell group 14 in the non-rectangular portion in the first region 10 can be connected to the first clock branch line group 12 in the shortest time.

<< Embodiment 4 of the Invention >>
In the fourth embodiment of the present invention, an example in which there is a hard macro such as SRAM (Static Random Access Memory) in the functional block will be described.

  FIG. 14 is a plan view showing a functional block 400 according to the fourth embodiment. The functional block 400 has a hard macro 35. The hard macro 35 is disposed across the first area 10 and the second area 20.

  As shown in FIG. 14, the hard macro 35 is arranged in the central portion of the second region 20. Therefore, in the functional block 400, the second clock driving cell 23 cannot be arranged near the center of the second region 20. Therefore, in the functional block 400, the second clock driving cell 23 is arranged below the second region 20 so as not to overlap with the hard macro 35. Thereby, the arrangement of the second clock driving cell 23 is not near the center of the second region 20. However, since the second clock trunk wiring 21 uses a low-resistance upper layer wiring, the second clock driving wiring 23 is arranged near the end of the second clock trunk wiring 21 and the second clock trunk wiring 21 is used. By connecting with 21 in the shortest time, the influence on the overall clock skew can be made sufficiently small.

  The first clock driving cell 13 is also moved in the vertical direction to the same position as the second clock driving cell 23. Thereby, the distance from the first clock driving cell 13 to the clock source driver 25 and the distance from the second clock driving cell 23 to the clock source driver 25 can be made equal. That is, the clock skew from the clock source driver 25 can be reduced.

  The hard macro 35 may have a plurality of clock connection pins. In the example of FIG. 14, one clock connection pin 35 a of the hard macro 35 is disposed in each of the first region 10 and the second region 20. Therefore, the clock connection pin 35 a in the first region 10 is connected to the first clock driving cell 13, and the clock connection pin 35 a in the second region 20 is connected to the second clock driving cell 23. Thereby, it is possible to connect from the clock branch line to the clock connection pin in the shortest time.

  When the input capacitance of the clock connection pin is large, the wiring delay to the clock connection pin becomes large, the load capacitance driven by the clock driving cell becomes very large, the slope of the signal waveform of the clock signal is reduced, and the clock skew is increased. growing. However, by dividing the clock connection pin into multiple parts as described above, each clock connection pin is driven by a different clock driving cell, or connected to a separate clock branch line, thereby connecting the clocks. The wiring delay to the pin can be reduced, and the load capacity driven by the clock driving cell can be reduced.

  Further, as shown in FIG. 15, the arrangement of the second clock driving cell 23 and the third clock driving cell 33 may be aligned with the horizontal position of the first clock driving cell 13. In the example of FIG. 15, the functional block is divided into a first area 10, a second area 20, and a third area 30. Further, the hard macro 35 is disposed across the second region 20 and the third region 30. Specifically, the hard macro 35 overlaps the central portions of the second region 20 and the third region 30, and the second clock driving cell is located near the center of the second region 20 and the third region 30. 23 and the third clock driving cell 33 cannot be arranged. Therefore, the second clock driving cell 23 and the third clock driving cell 33 are arranged by moving in the horizontal direction at a position where the arrangement does not overlap with the hard macro 35. In this case, the second clock backbone wiring 21 and the third clock backbone wiring 31 are moved to the same position as the second clock driving cell 23 and the third clock driving cell 33, so that the clock backbone from the clock driving cell. It is possible to reduce the wiring delay to the wiring and prevent the clock skew from deteriorating.

  In addition, by sandwiching the left and right of the hard macro with the clock main wiring, the clock supply to the hard macro can be performed from both the second clock main wiring 21 and the third clock main wiring 31. That is, this can reduce the wiring delay.

  The first clock driving cell 13 and the second clock driving cell 23 are arranged in a row as shown in FIG. 15, and the first clock driving cell 13 and the second clock driving cell from the clock source driver 25 are arranged. Up to 23 clock connection pins can also be configured by a multi-stage buffer tree in which each wiring length is equal to each other. Thereby, the wiring delay of each stage of the buffer tree can be made equal, and the clock skew from the clock source driver 25 can be reduced.

<< Embodiment 5 of the Invention >>
In the fifth embodiment of the present invention, an example in which the clock distribution circuit of the present invention is applied to a large-scale circuit will be described. FIG. 16 is a plan view showing a functional block 500 according to the fifth embodiment.

  As shown in FIG. 16, the functional block 500 is divided into four areas: a first area 10, a second area 20, a third area 30, and a fourth area 40. In this example, the third region 30 and the fourth region 40 are disposed below the first region 10 and the second region 20, respectively.

  In the fourth region 40, a fourth clock trunk line 41 is wired in the vertical direction near the center, and a group of clock branch lines (fourth clock branch line group 42) is connected from the fourth clock trunk line 41. Wired horizontally. In the vicinity of the center of the fourth clock trunk wiring 41, the output terminal of the fourth clock driving cell 43 arranged near the center of the fourth region 40 is connected.

  A fourth clock synchronization cell group 44 is arranged in the fourth area 40. The fourth clock synchronization cell group 44 is electrically connected to the fourth clock main line 41 or the fourth clock branch line group 42.

  In the first clock driving cell 13, the second clock driving cell 23, the third clock driving cell 33, and the fourth clock driving cell 43, the clock signal output from the same clock source driver 25 passes through the relay buffer. And the same clock signal is distributed. Here, from the clock source driver 25 to each relay buffer, and from the relay buffer to each clock driving cell are configured with equal length wirings, wiring delays at each stage can be made equal.

  In this manner, in the functional block 500, by dividing the region not only in the vertical direction but also in the horizontal direction, the length of the clock trunk wiring can be shortened and the wiring delay of the clock trunk wiring can be reduced. Furthermore, by reducing the number of clock synchronization cells in each region, the load capacity driven by each clock driving cell can be reduced. That is, it becomes possible to drive the clock trunk wiring, the clock branch wiring group, and the clock synchronous cell in the region by one clock driving cell.

  The function block can be divided into three or more in the vertical direction according to the size of the function block.

  In addition, the clock source driver 25 to the clock connection pins of the first clock driving cell 13 and the second clock driving cell 23 are constituted by a multi-stage buffer tree in which each wiring length is equal to each stage, Separately from the buffer tree, a plurality of stages in which the wiring length is equal to each other from the clock source driver 25 to the respective clock connection pins of the third clock driving cell 33 and the fourth clock driving cell 43. The buffer tree may be further configured. As a result, even when the functional block is long in the first direction, each clock backbone wiring can be shortened by dividing the region, and the number of clock synchronization cells driven by each clock driving cell can be reduced.

  However, a buffer tree from the clock source driver 25 to the first clock driving cell 13 and the second clock driving cell 23, and a buffer tree from the clock source driver 25 to the third clock driving cell 33 and the fourth clock driving cell 43, respectively. The buffer tree may be shared. By sharing, a part of the relay buffer and clock wiring used in the buffer tree can be shared, and the power consumption can be reduced.

  In the example shown in FIG. 17, the functional block is divided into a first area 10, a second area 20, a third area 30, and a fourth area 40 in the vertical direction. Also in this example, a clock trunk line, a clock branch line group, and a clock driving cell are arranged for each region. That is, if the area is divided into the optimum areas according to the size of the functional block, the load capacity of the clock in the area can be reduced to a load capacity value that can be driven by one clock driving cell.

  The functional block may be divided as shown in FIG.

  The functional block shown in FIG. 18 is divided into four areas: a first area 10, a second area 20, a third area 30, and a fourth area 40. The third region 30 and the fourth region 40 are disposed below the first region 10 and the second region 20.

  In addition, the first clock driving cell 13, the second clock driving cell 23, the third clock driving cell 33, and the fourth clock driving cell 43 use the same relay buffer for the clock signal output from the same clock source driver 25. And the same clock signal is distributed to each other. By arranging the clock driving cell at a position close to the relay buffer in this way, the relay buffer can be shared and the wiring length can be shortened. That is, power consumption can be reduced.

Embodiment 6 of the Invention
In the sixth embodiment of the present invention, an example in which the clock distribution circuit of the present invention is applied to a circuit having a plurality of clocks will be described. FIG. 19 is a plan view showing a functional block 600 according to the sixth embodiment.

  As shown in FIG. 19, the functional block 600 is divided into a first area 10, a second area 20, a third area 30, and a fourth area 40. In each region, a clock trunk line, a clock branch line group, and a clock driving cell are arranged. The first clock synchronization cell group 14, the second clock synchronization cell group 24, the third clock synchronization cell group 34, and the fourth clock synchronization cell group 44 are the first, second, third, and fourth, respectively. They are arranged in the region and are driven by the first clock driving cell 13, the second clock driving cell 23, the third clock driving cell 33, and the fourth clock driving cell 43, respectively.

  The first clock driving cell 13 and the second clock driving cell 23 are driven by the clock source driver 25, and the third clock driving cell 33 and the fourth clock driving cell 43 are driven by the clock source driver 60. Is done. That is, by inputting different clocks to the clock source driver 25 and the clock source driver 60, it is possible to use a plurality of clocks in the functional block.

  That is, in this example, the clock synchronization cells are arranged by dividing the area for each clock system, and the clock trunk line, the clock branch line group, and the clock driving cell are arranged in each area.

  Note that the areas may overlap in different clock systems. For example, in the example illustrated in FIG. 20, the second region 20 and the third region 30 partially overlap. Even in this case, the horizontal wiring positions may be shifted in the second clock branch line group 22 and the third clock branch line group 32. As a result, even when a plurality of clock synchronization cells are arranged in the same region, the clocks can be separately supplied using the configuration of the present invention.

<< Embodiment 7 of the Invention >>
In the seventh embodiment, an automated method for realizing the clock distribution circuit will be described. FIG. 21 is a flowchart of the clock layout automation method according to the seventh embodiment. This automated method includes an area dividing step S001, a basic wiring placement step S002, a branch wiring placement step S003, a drive cell placement and routing step S004, a clock connection step S005, and a buffer tree creation step S006. Processing in each process is as follows.

  First, in the area dividing step S001, the functional block is divided into a plurality of parts in the first direction (see FIG. 2).

  In the main wiring arrangement step S002, the clock main wiring is arranged at the center of each region using the upper layer wiring having a large film thickness along the first direction for each region.

  In the branch wiring arrangement step S003, a plurality of clock branch wirings are arranged in a second direction orthogonal to the first direction with the clock backbone wiring as the center.

  In the driving cell arrangement / wiring step S004, a clock driving cell for driving the clock trunk wiring and the clock branch wiring is arranged at the center of the region, and a wiring for connecting the clock driving cell and the clock trunk wiring is created.

  In the clock connection step S005, a wiring for connecting the clock synchronization cell in the area to the adjacent clock trunk wiring or clock branch wiring in the same area is created.

  In the buffer tree creation step S006, a buffer tree from the clock source driver to the clock driving cell is created.

  That is, the above-described clock layout automation method divides a region by a designated method by inputting a region dividing method and a buffer tree configuration. Next, a clock trunk line, a clock branch line group, and a clock driving cell are arranged for each region. Then, the connection is changed so that the clock synchronization cell in the region is connected to the clock driving cell in the region, and a wiring that connects to the adjacent clock trunk wiring or clock branch wiring is created. After that, the buffer tree is configured with the specified buffer tree configuration from the clock driver to the clock synchronous cell.

  The clock distribution circuit according to the present invention can reduce power consumption and clock skew, and can reduce the load capacity of a clock driving cell even in a large-scale semiconductor integrated circuit. A standard cell is used on the semiconductor integrated circuit. This is useful as a clock distribution circuit for distributing a clock signal in a functional block configured as described above.

2 is a plan view showing a functional block 100 according to Embodiment 1. FIG. FIG. 6 is a diagram showing a connection example of a second clock synchronization cell group 24 in the second region 20. 4 is an enlarged plan view of a connection portion between a second clock driving cell 23 and a second clock trunk wiring 21 and a connection portion between a second clock branch wiring group 22 and a second clock synchronization cell group 24. FIG. FIG. 3 is a connection partial cross-sectional view of a second clock driving cell 23 and a second clock trunk wiring 21. 6 is a plan view showing a functional block 200 according to Embodiment 2. FIG. It is a figure which shows the example of the functional block from which the drive capability of the 1st clock drive cell 13 and the 2nd clock drive cell 23 differs. It is a figure which shows the example of a wiring of a clock branch line wiring. It is a figure which shows the example of a wiring of a clock branch line wiring. It is a figure explaining the wiring method of clock branch line wiring. It is a top view which shows the functional block 300 which concerns on Embodiment 3. FIG. 3 is a diagram illustrating an example of division of a functional block 300. FIG. This is an example in which the clock distribution circuit according to the present invention is applied when the shape of the functional block is non-rectangular. This is an example in which the clock distribution circuit according to the present invention is applied when the shape of the functional block is non-rectangular. FIG. 10 is a plan view showing a functional block 400 according to Embodiment 4. FIG. 6 is a diagram illustrating an arrangement example of a second clock driving cell and a third clock driving cell 33. FIG. 10 is a plan view showing a functional block 500 according to a fifth embodiment. It is a figure which shows an example of the division | segmentation of the functional block 500. FIG. It is a figure which shows an example of the division | segmentation of the functional block 500. FIG. 10 is a plan view showing a functional block 600 according to Embodiment 6. FIG. It is a figure which shows the example of the functional block with which the area | region has overlapped between different clock systems. FIG. 10 is a flowchart of a clock layout automation method according to the seventh embodiment.

Explanation of symbols

10 First region
11 First clock trunk wiring
12 First clock branch wiring group
13 First clock drive cell
14 First clock synchronization cell group
20 Second area
21 Second clock trunk wiring
22 Second clock branch wiring group
23 Second clock drive cell
24 Second clock synchronization cell group
25 Clock source driver
30 third region
31 Third clock trunk wiring
32 Third clock branch wiring group
33 Third clock-driven cell
34 Third clock synchronous cell group
35 Hard Macro
35a Clock connection pin
40 Fourth area
41 Fourth clock trunk wiring
42 Fourth clock branch wiring group
43 Fourth clock drive cell
44 Fourth clock synchronization cell group
60 clock source driver 100 functional block 200 functional block 300 functional block 400 functional block 500 functional block 600 functional block

Claims (19)

A semiconductor integrated circuit using a clock distribution circuit that distributes a clock signal in a functional block configured using standard cells,
A first clock trunk wiring wired in a first direction;
A first clock branch wiring group comprising a plurality of clock branch wirings wired in a second direction orthogonal to the first direction and electrically connected to the first clock backbone wiring;
A first clock driving cell electrically connected to the first clock backbone wiring;
A first clock synchronization cell group comprising a plurality of clock synchronization cells electrically connected to the first clock backbone wiring or the first clock branch wiring group;
A second clock trunk wiring arranged in parallel with the first clock trunk wiring;
A second clock branch line group consisting of a plurality of clock branch lines wired in the second direction and electrically connected to the second clock backbone line;
A second clock driving cell electrically connected to the second clock backbone wiring;
A second clock synchronization cell group consisting of a plurality of clock synchronization cells electrically connected to the second clock backbone wiring or the second clock branch wiring group;
A clock source driver for supplying a clock signal to the first clock driving cell and the second clock driving cell;
The first clock branch line group and the second clock branch line group are electrically separated,
Driving the first clock trunk wiring and the first clock branch wiring group only by the first clock driving cell;
A semiconductor integrated circuit using a clock distribution circuit, wherein only the second clock driving cell drives the second clock trunk wiring and the second clock branch wiring group. A semiconductor integrated circuit using the clock distribution circuit according to claim 1,
The semiconductor integrated circuit is composed of a plurality of wiring layers with a thick upper layer film pressure and a lower layer film pressure,
The first clock backbone wiring and the second clock backbone wiring are formed using a thick upper layer wiring,
Each clock synchronization cell of the first clock synchronization cell group includes a first clock branch line group or a first clock line located at the shortest position in the forward or reverse direction with respect to the first direction from the respective arrangement position. Connected to the clock trunk wiring using a thin lower layer wiring,
Each of the clock synchronization cells of the second clock synchronization cell group is a second clock branch line group or a second clock line located at the shortest position in the forward direction or the reverse direction with respect to the first direction from the respective arrangement position. A semiconductor integrated circuit characterized in that it is connected to a clock trunk wiring using a lower-layer wiring having a small film thickness. A semiconductor integrated circuit using the clock distribution circuit according to claim 1,
The first direction range is determined by the first clock trunk wiring, the second direction range is determined by the first clock branch line group, and the first direction range is the second clock range. And the second region in which the range in the second direction is determined by the second clock branch line group is determined by the clock trunk wiring of
The first clock synchronization cell group is disposed in the first region,
The second clock synchronization cell group is disposed in the second region,
The first clock trunk wiring is disposed at the center of the first region;
2. The semiconductor integrated circuit according to claim 1, wherein the second clock trunk wiring is arranged at the center of the second region. A semiconductor integrated circuit using the clock distribution circuit according to claim 1,
The wiring path connecting the first clock driving cell and the first clock trunk wiring and the wiring path connecting the second clock driving cell and the second clock trunk wiring are constituted by a wide wiring and a plurality of contacts. A semiconductor integrated circuit. A semiconductor integrated circuit using the clock distribution circuit according to claim 1,
The clock branch lines of the first clock branch line group are arranged at equal intervals in the first direction and symmetrically about the first clock trunk line.
Each of the clock branch lines of the second clock branch line group is arranged at equal intervals in the first direction and symmetrically about the second clock main line. circuit. A semiconductor integrated circuit using the clock distribution circuit according to claim 1,
The number of clock branch lines in the first clock branch line group is different from the number of clock branch lines in the second clock branch line group. A semiconductor integrated circuit using the clock distribution circuit according to claim 1,
The first clock driving cell is disposed at the center of the first clock trunk wiring,
The second clock driving cell is disposed at the center of the second clock backbone wiring,
The semiconductor integrated circuit according to claim 1, wherein the first clock driving cell and the second clock driving cell have different driving capabilities. A semiconductor integrated circuit using the clock distribution circuit according to claim 1,
Each clock branch line of the first clock branch line group is asymmetric with respect to the first clock trunk line,
A semiconductor integrated circuit, wherein the first clock branch line group includes clock branch lines having different wiring lengths. A semiconductor integrated circuit using the clock distribution circuit according to claim 1,
Each clock branch line of the first clock branch line group is asymmetric with respect to the first clock trunk line,
A semiconductor integrated circuit, wherein the first clock branch line group includes clock branch lines having different wiring lengths and wiring widths. A semiconductor integrated circuit using the clock distribution circuit according to claim 1, further comprising:
A third clock trunk wiring wired in the first direction;
A third clock branch line group consisting of a plurality of clock branch lines wired in the second direction and electrically connected to the third clock backbone line;
A third clock driving cell electrically connected to the third clock trunk wiring and driving only the third clock trunk wiring and the third clock branch wiring group;
A third clock synchronization cell group consisting of a plurality of clock synchronization cells electrically connected to the third clock backbone wiring or the third clock branch wiring group;
With
The first clock backbone wiring, the second clock backbone wiring, and the third clock backbone wiring are arranged in this order in the second direction,
The wiring interval between the first clock backbone wiring and the second clock backbone wiring and the wiring spacing between the second clock backbone wiring and the third clock backbone wiring are different from each other,
The semiconductor integrated circuit, wherein the first clock branch line group, the second clock branch line group, and the third clock branch line group have different clock branch line lengths. A semiconductor integrated circuit using the clock distribution circuit according to claim 1,
A semiconductor integrated circuit, wherein the first clock trunk wiring and the second clock trunk wiring have different wiring lengths. A semiconductor integrated circuit using the clock distribution circuit according to claim 1, further comprising:
A third clock backbone wiring routed in the first direction on the forward or reverse side of the first direction of the second clock backbone wiring;
A third clock branch line group consisting of a plurality of clock branch lines wired in the second direction and electrically connected to the third clock backbone line;
A third clock driving cell electrically connected to the third clock trunk wiring and driving only the third clock trunk wiring and the third clock branch wiring group;
A third clock synchronization cell group consisting of a plurality of clock synchronization cells electrically connected to the third clock backbone wiring or the third clock branch wiring group;
With
The semiconductor integrated circuit according to claim 1, wherein a wiring length of the first clock backbone wiring is longer than a total value of a wiring length of the second clock backbone wiring and a wiring length of the third clock backbone wiring. A semiconductor integrated circuit using the clock distribution circuit according to claim 1,
A hard macro is further provided in a central portion of the first clock trunk wiring or the second clock trunk wiring,
The semiconductor integrated circuit according to claim 1, wherein the first clock driving cell and the second clock driving cell are arranged apart from each other in the first direction in a region where the hard macro and the arrangement do not overlap. A semiconductor integrated circuit using the clock distribution circuit according to claim 1,
A hard macro having a plurality of clock connection pins to which a clock signal is supplied;
The semiconductor integrated circuit is composed of a plurality of wiring layers with a thick upper layer film pressure and a lower layer film pressure,
Each clock connection pin includes a clock branch line of the first clock branch line group, a clock branch line of the second clock branch line group, the first clock trunk line, and the second clock trunk line. A semiconductor integrated circuit characterized in that it is connected to a wiring located in the shortest position in the forward direction or the reverse direction with respect to the first direction by using a lower layer wiring having a small film thickness. A semiconductor integrated circuit using the clock distribution circuit according to claim 1,
The first clock driving cell and the second clock driving cell each have a clock connection pin for supplying a clock signal;
The clock connection pins are arranged in a row,
From the clock source driver to the clock connection pins of the first clock driving cell and the second clock driving cell, each stage has a plurality of buffer trees each having the same wiring length. A semiconductor integrated circuit. A semiconductor integrated circuit using the clock distribution circuit according to claim 15, further comprising:
A third clock backbone wiring routed in the first direction on the forward or reverse side of the first direction of the first clock backbone wiring;
A third clock branch line group consisting of a plurality of clock branch lines wired in the second direction and electrically connected to the third clock backbone line;
A third clock driving cell electrically connected to the third clock trunk wiring and driving only the third clock trunk wiring and the third clock branch wiring group;
A third clock synchronization cell group consisting of a plurality of clock synchronization cells electrically connected to the third clock backbone wiring or the third clock branch wiring group;
A fourth clock trunk wiring routed in the first direction on the forward or reverse side of the first direction of the second clock trunk wiring;
A fourth clock branch wiring group composed of a plurality of clock branch wirings wired in the second direction and electrically connected to the fourth clock backbone wiring;
A fourth clock driving cell electrically connected to the fourth clock trunk wiring and driving only the fourth clock trunk wiring and the fourth clock synchronization cell group;
A fourth clock synchronization cell group consisting of a plurality of clock synchronization cells electrically connected to the fourth clock backbone wiring or the fourth clock branch wiring group;
With
The third clock driving cell and the fourth clock driving cell each have a clock connection pin for supplying a clock signal,
Separately from the buffer tree, a plurality of stages in which each wiring length is equal to each stage from the clock source driver to the clock connection pins of the third clock driving cell and the fourth clock driving cell. A semiconductor integrated circuit comprising a buffer tree. A semiconductor integrated circuit using the clock distribution circuit according to claim 15, further comprising:
A third clock backbone wiring routed in the first direction on the forward or reverse side of the first direction of the first clock backbone wiring;
A third clock branch line group consisting of a plurality of clock branch lines wired in the second direction and electrically connected to the third clock backbone line;
A third clock driving cell electrically connected to the third clock trunk wiring and driving only the third clock trunk wiring and the third clock branch wiring group;
A third clock synchronization cell group consisting of a plurality of clock synchronization cells electrically connected to the third clock backbone wiring or the third clock branch wiring group;
A fourth clock trunk wiring routed in the first direction on the forward or reverse side of the first direction of the second clock trunk wiring;
A fourth clock branch wiring group composed of a plurality of clock branch wirings wired in the second direction and electrically connected to the fourth clock backbone wiring;
A fourth clock driving cell electrically connected to the fourth clock trunk wiring and driving only the fourth clock trunk wiring and the fourth clock synchronization cell group;
A fourth clock synchronization cell group consisting of a plurality of clock synchronization cells electrically connected to the fourth clock backbone wiring or the fourth clock branch wiring group;
With
The third clock driving cell and the fourth clock driving cell each have a clock connection pin for supplying a clock signal,
The semiconductor integrated circuit, wherein the buffer tree is shared from the clock source driver to the clock connection pins of the third clock driving cell and the fourth clock driving cell. A semiconductor integrated circuit using the clock distribution circuit according to claim 1, further comprising:
A third clock trunk wiring wired in the first direction;
A third clock branch line group consisting of a plurality of clock branch lines wired in the second direction and electrically connected to the third clock backbone line;
A third clock driving cell electrically connected to the third clock trunk wiring and driving only the third clock trunk wiring and the third clock branch wiring group;
A third clock synchronization cell group consisting of a plurality of clock synchronization cells electrically connected to the third clock backbone wiring or the third clock branch wiring group;
A fourth clock trunk wiring wired in the first direction;
A fourth clock branch wiring group composed of a plurality of clock branch wirings wired in the second direction and electrically connected to the fourth clock backbone wiring;
A fourth clock driving cell electrically connected to the fourth clock trunk wiring and driving only the fourth clock trunk wiring and the fourth clock synchronization cell group;
A fourth clock synchronization cell group consisting of a plurality of clock synchronization cells electrically connected to the fourth clock backbone wiring or the fourth clock branch wiring group;
A clock source driver different from the clock source driver for supplying a clock signal to the third clock driving cell and the fourth clock driving cell;
With
The first clock trunk wiring, the second clock trunk wiring, the third clock trunk wiring, and the fourth clock trunk wiring are arranged in this order in the second direction,
A clock source driver that supplies a clock signal to the first clock driving cell and the second clock driving cell, and a clock source driver that supplies a clock signal to the third clock driving cell and the fourth clock driving cell, respectively A semiconductor integrated circuit, wherein another clock signal is input. A semiconductor integrated circuit layout method using a clock distribution circuit for distributing a clock signal,
An area dividing step of dividing the functional block provided with the clock distribution circuit into a plurality of areas in a first direction;
For each region, a main wiring arrangement step of arranging a clock main wiring in the center of the region using a thick upper layer wiring along the first direction;
A branch wiring arrangement step of arranging a plurality of clock branch wirings in a second direction orthogonal to the first direction around the clock trunk wiring;
A driving cell arrangement wiring step of arranging a clock driving cell for driving the clock trunk wiring and the clock branch wiring in the center of the region, and creating a wiring for connecting the clock driving cell and the clock trunk wiring;
A clock connection step of creating a wiring for connecting a clock synchronization cell in the region to an adjacent clock backbone wiring in the same region, or a clock branch wiring; and
A buffer tree creation process for creating a buffer tree from a clock source driver to a clock driving cell;
A method for laying out a semiconductor integrated circuit, comprising:

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