JP2010287768A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of wiring between cells disposed in different cell columns using a wiring layer used for wiring in a cell internally, without using a wiring layer used for wiring, and to provide a method of manufacturing the same. <P>SOLUTION: The semiconductor device includes cell columns where standard cells are disposed side by side, comprising a first and a second column arranged by touching in the side of direction of the columns extending in parallel mutually. A first I/O functional wiring of a first cell disposed in a first cell, which is one of an input wiring, an output wiring, and an I/O wiring disposed in the first cell column, is connected to a second I/O functional wiring of a second cell disposed in the second cell column on the same wiring layer. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. In particular, the present invention relates to placement and routing of a semiconductor device using standard cells.

  Conventionally, in a mask layout design of a semiconductor device, a standard cell system in which basic combinational circuits and sequential circuits required for layout design are prepared as standard standard cells and the design is performed using the standard cells. These semiconductor devices are widely used. Further, in the mask layout design using the standard cell, various ideas have been proposed in order to improve the design efficiency and the performance of the designed semiconductor device.

  In Patent Document 1, in designing a semiconductor integrated circuit using an automatic placement and routing tool, as a method for efficiently designing a semiconductor integrated circuit with a small wiring layout and a small layout area and wiring capacity, a predetermined standard cell is combined. A method for designing a semiconductor integrated circuit using a new standard cell is described.

  Further, in Patent Document 2, an adjacent placement constraint is provided for a plurality of cells based on the adjacent placement constraint described in the external instruction information file, and a plurality of cells for which the adjacent placement constraint is set are arranged at the time of layout. A logic automatic design support method is described in which the cells are arranged adjacent to each other and the cells are connected by a local interconnect.

JP 2006-139765 A JP 2001-338006 A

  The following analysis is given by the present invention. According to Patent Document 1, a specific combination of cells is found for a critical path or the like and a composite new cell is generated. Therefore, it is efficient to apply an arbitrary number of combinations of cells to a number of critical paths. Is expected to decrease. Further, even if the cells are arranged adjacently as in Patent Document 2, the wiring between the cells arranged adjacent to each other is not the lower layer wiring used for the wiring in the cell, but the upper layer wiring used for the wiring between the cells. Therefore, the upper layer wiring is also used for wiring between adjacent cells, thereby compressing the wiring path of wiring between other separated cells.

  According to the inventor's knowledge, a logic circuit having two or more systems of inputs and outputs can be arranged and wired efficiently by using a plurality of cell rows (cell shelves). Discloses only arranging adjacent cells in a single cell column.

  A semiconductor device according to one aspect of the present invention is a first and second cell row in which a plurality of standard cells are arranged side by side, and is arranged in contact with each other in a long side direction extending in parallel with each other. 1st and 2nd cell column, and one of the input wiring, the output wiring, and the input / output wiring of one of the plurality of first standard cells arranged in the first cell column. A first input / output function wiring includes a second input / output function wiring of at least one cell of the plurality of second standard cells arranged in the second cell column, and the first input / output function. They are connected in the same wiring layer as the functional wiring.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, wherein a plurality of standard cells are arranged in a matrix along a first direction and a second direction orthogonal to the first direction. Any one of the input wiring, output wiring, and input / output wiring of each of the plurality of standard cells between the first cell placement processing to be placed and the standard cells placed adjacent to each other along the first direction. A first wiring process connected using a wiring layer of the same layer as the input / output function wiring as a wiring, and at least one pair of standard cell pairs arranged adjacent to each other along the second direction And a second wiring process for connecting between them using the same wiring layer as the input / output function wiring.

  A data structure of a standard cell library for automatic placement and routing according to still another aspect of the present invention is a data structure of cells included in the standard cell library for automatic placement and routing, and each cell is arranged within a cell boundary. Layout data and virtual boundary wiring that is connected to an input / output function wiring that is one of input wiring, output wiring, and input / output wiring of the cell and is in contact with a cell boundary on a wiring grid, and the first cell boundary of the cell A plurality of recognition layers provided corresponding to each of the second cell boundaries orthogonal to the first cell boundary, and the recognition layer is connected to other cells arranged adjacent to each other. After the relative placement position is determined, when it comes into contact with a recognition layer or wiring of the same potential of another cell, it is converted to actual wiring data, and when it comes into contact with a recognition layer or wiring of a different potential of another cell , It is configured to be removed without being converted to the wiring.

  According to the present invention, since the cells are connected by the same wiring layer as the input / output function wiring of the standard cell, wiring can be performed with a small area without pressing the wiring path of the upper layer wiring.

(A) is a circuit diagram of a circuit to be placed and routed, (b) is a layout image diagram when placed and wired using a single cell row, and (c) is placed and routed using a plurality of cell rows. It is a layout image figure in the case. It is a flowchart which shows the arrangement | positioning wiring process in the manufacturing method of the semiconductor device by one Example of this invention. (A)-(c) is a top view of the inverter cell used for one Example of this invention, respectively. (A), (b) is a top view of the NAND cell used for one Example of this invention, respectively. (A), (b) is a top view of another NAND cell used for one Example of this invention, respectively. (A), (b) is a top view of the NOR cell used for one Example of this invention, respectively. (A), (b) is a top view of another NOR cell used for one Example of this invention, respectively. FIG. 2 is a layout diagram in which the circuit of FIG. 1A is arranged and wired according to an embodiment of the present invention. (A) of the inverter cell used for one Example of this invention is a top view before arrangement | positioning wiring, (b) is a top view after wiring to a 2nd metal wiring layer, (c) is to a 2nd metal wiring. It is CC 'sectional drawing after wiring.

  Before describing the details of the embodiments, the examination results and the outline of the present invention will be described. In the description of the outline, the drawings and the reference numerals of the drawings are shown as examples of the embodiments, and the variations of the embodiments according to the present invention are not limited thereby.

  FIG. 1A is an example of a circuit that is an object of automatic placement and routing. FIG. 1A is a circuit that is included in a critical path and requires a wiring length as short as possible. In FIG. 1A, the output signal netA of the inverter circuit A and the output signal netC of the NAND circuit B are input to the NOR circuit C, and the output signal netB of the NOR circuit is inverted by the inverter circuit D and output to the outside as the output signal OUTC. Output.

  FIG. 1B is an example in which the circuit of FIG. 1A is arranged and wired using a single cell column. Since there are two systems of input signals to the NOR circuit C, the inverter circuit A and the NAND circuit B are arranged in the preceding stage of the NOR circuit C, and the output signals NetA and NetC are connected to the NOR circuit C. However, since the NAND circuit B is arranged between the inverter circuit A and the NOR circuit C, the output signal NetA of the inverter circuit A is connected to the NOR circuit C unless it is wired across the NAND circuit B. Can not do it.

  On the other hand, if the cell row (cell shelf) in which the inverter circuit A and the NAND circuit B are arranged and the cell row in which the NOR circuit C and the inverter circuit D are arranged are separated as shown in FIG. Since it can be connected to the NOR circuit C without straddling, the wiring length can be shortened, the signal propagation time can be shortened, and the layout can be made compact. However, in general, the wiring between the cell columns cannot be connected unless the upper layer wiring is used, and if the upper layer wiring is used, the free wiring using the upper layer wiring of other wiring is restricted. It will be.

  In the semiconductor device of one embodiment of the present invention, for example, as shown in FIG. 8, a first cell column and a second cell column, which are cell columns in which standard cells are arranged side by side, are arranged in parallel to each other. Further, the first cell row and the second cell row are arranged in contact with each other at the side in the direction in which the cell row extends. For example, in FIG. 8, the cell row in which the inverter circuit A and the NAND circuit B are arranged, and the cell row in which the NOR circuit C and the inverter circuit D are arranged are arranged in parallel with each other, and are in contact with each other in the extending direction of the cell row. Are arranged. Further, the first input / output function wiring of the first cell arranged in the first cell column (for example, the output wiring of the inverter circuit A or the NAND circuit B) is arranged in the second cell column. The second input / output function wiring of the cell (input wiring of the NOR circuit C) is connected to the same wiring layer as the input / output function wiring (for example, netA connects OU14 and ILR54M of the same wiring layer as the input / output function wiring). Connected via). Therefore, cells arranged in different cell columns can be connected using only the lower layer wiring used for the wiring in the cell without using the upper layer wiring used for wiring between the separated cells. Further, the wiring connecting the cells is a wiring in the cell provided as cell data in advance, and is different from the conventional inter-cell wiring in which wiring originally not in the cell is wired as wiring between cells.

  In addition, the first and second cells (for example, A and C in FIG. 8 or B and C in FIG. 8) are arranged in contact with each cell boundary, and the corresponding input / output function wiring extends to the cell boundary and is wired. (For example, OU14 and ILR54M in FIG. 8 or OUR45 and ILR62M are connected). Since the first cell and the second cell are arranged in contact with each other at the cell boundary, they can be connected only by the intra-cell wiring.

  Further, the intra-cell wiring connecting the cells is a wiring in a wiring layer that is not used in the wiring between the cell columns. As shown in FIG. 9, wiring in the cell is performed using the first wiring layer M1, and power supply from the outside to the cell and wiring between the cells are performed using the upper wiring above the second wiring layer M2.

  The cells (A to D) including the first and second cells are intra-cell wirings connected to the input / output function wirings, and are virtual boundary wirings (OU14) that contact each cell boundary at a standardized position. , ILR54M, OUR45, ILR62M, etc.). Depending on the state after placement, if the virtual boundary wiring is in contact with a wiring with a different potential in another cell, it is deleted (the part indicated as “open” in FIG. 8), and it is in contact with the wiring with the same potential in another cell. In the case where the virtual boundary wiring is present, the virtual boundary wiring is converted into the wiring in the actual cell (the portion indicated as short). The virtual boundary wiring (or the recognition layer) is a wiring in a cell provided in the standard cell in advance, and whether or not the wiring is actually wired depends on the cells arranged in the periphery. Therefore, even in the same cell used in the same semiconductor integrated circuit, there may be a cell with an intra-cell wiring and a cell without an intra-cell wiring in the virtual boundary wiring region. It may be considered that each cell has a mask option that can be connected to an adjacent cell.

  In addition, referring to FIG. 2, the automatic placement and routing method for a semiconductor integrated circuit according to an embodiment of the present invention is connected to an input / output function wiring that is one of an input wiring, an output wiring, and an input / output wiring of a cell. A standard cell including a recognition layer (for example, IU13, IM11, IM12, IL14, OU13, OU14, OM13, OM12, OL15, OL16 in FIG. 3A) that is a virtual boundary wiring that contacts the boundary at a standardized position. Is an automatic placement and routing method for a semiconductor integrated circuit using an adjacent cell placement step S1 in which a plurality of cells are placed such that recognition layers connected to input / output function wires that need to be connected to each other are in contact with each other at a cell boundary. If the recognition layer connected to the input / output function wiring of the same potential is converted to the actual boundary wiring among the recognition layers that are in contact at the cell boundary, the cells are connected by the actual boundary wiring. Includes the boundary lines connecting deletion process S3 be removed without converting the recognition layer connected to the input and output functions wiring of a different potential to the actual boundary line, the. For example, in FIG. 8, in order to realize the circuit of FIG. 1A, the recognition layer described as short in FIG. 8 is converted into an actual boundary wiring, and the recognition layer described as open in FIG. 8 is deleted.

  The recognition layer is at least a recognition layer in contact with the cell boundary at a side parallel to the direction in which the cell row extends when the cells are arranged in the cell row (for example, in the case of FIG. 3A, OU13, OU14, IU13, OL15, OL16, IL14), and the adjacent cell arrangement step S1 arranges the recognition layers of the cells arranged in different cell rows so as to contact each other at the side. For example, the recognition layer OU14 of the inverter cell A in FIG. 8 is arranged so as to be in contact with the cell boundary (broken line in FIG. 8) at a side parallel to the direction in which the cell row extends and to be in contact with the recognition layer ILR54M of the NOR cell C on that side. To do.

  In addition, the data structure of the automatic placement and routing standard cell library according to an embodiment of the present invention is a cell data structure included in the automatic placement and routing standard cell library, and each cell is placed within the cell boundary. A recognition layer comprising real layout data and a recognition layer that is a virtual boundary wiring that is connected to an input / output function wiring that is one of an input wiring, an output wiring, and an input / output wiring of the cell and is in contact with a cell boundary on a wiring grid. After the relative arrangement position with other cells arranged adjacent to each other is contacted with a recognition layer or wiring of the same potential of another cell, it is converted into actual wiring data, and the other cell When the contact layer is in contact with a different potential recognition layer or wiring, it is deleted without being converted into an actual wiring. For example, the cell information data stored in the cell information 2 of FIG. 2 includes the data of the recognition layer (see FIGS. 3 to 8) in addition to the actual layout data arranged in the cell boundary. In the boundary wiring connection deletion step, the data of the recognition layer included in the cell information 2 is converted into actual wiring data in consideration of the relationship with other adjacent cells arranged or deleted. That is, by providing the recognition layer as the cell data structure, it is possible to connect to other cells using only the intra-cell wiring. Hereinafter, embodiments will be described in detail with reference to the drawings.

  FIG. 2 is a flowchart of the placement and routing process in the semiconductor device manufacturing method according to the first embodiment. The circuit information 1 is a file in which connection information of a circuit to be placed and routed is described. Cell information 2 is a file in which layout information of a cell library including cells used in the circuit is stored. The cell information 2 includes information on a recognition layer for connecting to an adjacent cell using intra-cell wiring, as will be described in detail later. For example, the cell adjacency information 3 is configured as shown in FIG. 1 (a) adjacent arrangement constraint F1, groups are grouped for each function, and the input / output wiring is shortest between the cells constituting the cell. It is a file that describes the restrictions for enabling connection. The adjacent arrangement restriction information F1 in FIG. 1A represents the adjacent arrangement restriction information of a part of circuits included in the cell adjacency information 3 as a circuit diagram. In the circuit of FIG. 1A, the adjacent arrangement constraint is set so that the length of the input / output wiring between the elements A to D is minimized.

  In the adjacent cell placement step of step S1, the circuit connection information of the circuit information 1 and the recognition layer position of the cell included in the cell information 2 and the recognition layer are connected to the circuit whose neighbor placement is specified by the cell neighbor information 3. In consideration of input / output function wiring, cell outer shape, etc., standard cells corresponding to circuits for which adjacent arrangement is designated are arranged in a matrix. Note that the cell used for placement and routing in the first embodiment includes a recognition layer that is in contact with the cell boundary, which is the boundary of the region occupied by the cell, on the wiring grid. The recognition layer is composed of wiring in the cell and is connected to the input / output function wiring of each cell. Therefore, if the recognition layer between the cells is placed in contact, the input / output function wiring of the cell is connected via the recognition layer. Can be connected only via the in-cell wiring. Therefore, in this process, adjacent cells are connected to the input / output function wiring connection information of each cell stored in the circuit information 1 and the input / output function wiring and input / output function wiring stored in the cell information 2. In consideration of the position of the recognition layer to be arranged, the arrangement is made so that they can be connected to each other using only the wiring in the cell as much as possible.

  In the cell placement step of step S2, the remaining cells that have not been placed in the adjacent cell placement step of step S1 are placed in a matrix with reference to circuit information 1 and cell information 2. In the boundary wiring connection deleting step in step S3, the circuit information 1 is referred to for the recognition layer of the cell arranged in contact with the recognition layer of another cell, and the input / output function wiring connected by the recognition layer has the same potential. Determine whether or not. If they are at the same potential, the attributes of the recognition layer are changed so that the recognition layer is handled in the same way as normal wiring in a cell. When the potential is different, the attribute of the recognition layer is changed so that the wiring is open. Specifically, in the boundary wiring connection deletion step in step S3, the input / output function wiring is the same for the recognition layer of the cell arranged in contact with the recognition layer of another cell in the direction along the cell row (first direction). The input / output function wiring has the same potential for the process of determining whether or not it is a potential and the recognition layer of a cell arranged in contact with the recognition layer of another cell in the direction (second direction) orthogonal to the cell row And processing for determining whether or not there is. In the layout wiring process of step S4, the wiring between the cells is performed based on the information of the circuit information 1 except for the wiring connected only by the intra-cell wiring using the recognition layer in step S3, thereby completing the mask layout. , Output as layout data 4. Further, based on the layout data 4, transistors and wirings are formed on the semiconductor substrate by a well-known method, thereby completing the manufacture of the semiconductor device.

  Next, the configuration of the layout cell used for the placement and routing of the semiconductor integrated circuit according to the first embodiment will be described with reference to FIGS. FIG. 3 is a plan view of the inverter cell. The inverter cell INV1 in FIG. 3A and the inverter cell INV2 in FIG. 3B show patterns in which the sizes of the channel widths W of the transistors are different from each other. Similarly, both inverter cells have a configuration in which an input / output wiring connected to any one of an input wiring, an output wiring, and an input / output wiring extends to the boundary portion of the cell. In FIG. 3, the cell boundary is indicated by a rectangular broken line surrounding the cell. The same applies to FIGS. 4 to 9. Each cell has a layout pattern in a broken line (in a cell boundary) surrounded by a rectangle. Further, the inverter cell INV3 in FIG. 3C is an example in which the cell area is reduced by bringing the input wiring I1 of the inverter cell INV1 to the center. However, in both inverter cells INV1 and INV2, the wiring of the input signal extends to the boundary in the vertical direction (IU13, IL14, IU23, IL24), and the input signal can be connected from the vertical direction as well, as shown in FIG. The input signal of the inverter cell INV3 in c) is different in that the input signal is connected from the lateral direction. Since the output extraction ports exist in both the horizontal direction and the vertical direction in the same manner as INV1 and INV2, INV3 in FIG. 3C is used to output a signal input from the horizontal direction in the vertical direction. By using it, it works advantageously in terms of area and wiring. Further, the connection area of the input signal is limited to the inverter cell INV2 as in the inverter cell INV3, and the cell area can be suppressed by changing the input wiring shape. In the present specification, in FIGS. 3 to 7, a frame indicated by a broken line for each cell is referred to as a cell boundary.

  The input wiring I1 of the cell INV1 in FIG. 3A includes recognition layers IM11, IM12, IU13, and IL14 defined by the same type of wiring layer as the input wiring I1 extending to the cell boundary. Similarly, the output wiring O1 includes recognition layers OM11, OM12, OU13, OU14, OL15, and OL16 defined by the same type of wiring layer as the output wiring O1 extended to the cell boundary. These recognition layers are arranged at predetermined positions so as to be in contact with the cell boundary on the wiring grid determined by each cell at the cell boundary. Note that these recognition layers are configured so that the attributes can be changed by determining whether the recognition layers have the same potential or different potentials as the recognition layers of other cells in contact with the boundary. Therefore, by changing the attribute of the recognition layer, if the recognition layer of another cell that is in contact with the recognition layer of the cell has the same potential signal, the recognition layer is set as the same wiring data as other wirings in the cell. It is connected to another cell by a wiring (wiring converted from the recognition layer) of the same layer as another wiring in the cell in which the attribute of the recognition layer is changed. On the other hand, when the recognition layer of another adjacent cell is a signal having a different potential, the recognition layer is deleted, and the other adjacent cell is not connected via the recognition layer. Similarly to the inverter cell INV1, the inverter cell INV2 and the inverter cell INV3 are connected to the respective input / output function wirings and include a recognition layer that is in contact with the cell boundary at a standardized position. Similar to the inverter cell INV1, the recognition layer is connected to another cell via the recognition layer or the recognition layer is deleted due to a difference in potential with the recognition layer of another cell adjacently disposed. is there.

  In FIG. 3B, the recognition layers IU23, IM21, IM22, and IL24 are connected to the cell input wiring I2, and the recognition layers OU23, OU24, OU25, OM21, OM22, OL26, OL27, and OL28 are cell output wirings. Connected to O2. In FIG. 3C, the recognition layers IM31 and IM32 are connected to the cell input wiring I3, and the recognition layers OU33, OU34, OM31, OM32, OL35, and OL36 are connected to the cell output wiring O3.

  In order to connect these inverter cells to the input / output function wiring of other cells using only the wiring in the cell, it is not possible to connect them through the recognition layer, but the upper inter-cell wiring is connected to the input wiring. By connecting to (I1, I2, I3) or the output wiring (O1, O2, O3), it is possible to connect to other cells without using a recognition layer. The same applies to the cells of FIGS. 4 to 7 described below.

  FIGS. 4A and 4B and FIGS. 5A and 5B are plan views of the NAND cell according to the first embodiment. Similar to the inverter cell of FIGS. 3A to 3C, a recognition layer connected to the input / output function wiring of the cell and in contact with the boundary of the cell on the wiring grid is provided. This recognition layer is a virtual wiring defined as a wiring layer of the same type as the wiring in the cell. In the NAND 1 in FIG. 4A, the recognition layer IMA11 and the recognition layer IMA12 are provided for the input wiring IA1, the recognition layer IMA21 is provided for the input wiring IA2, and the recognition layer OMA11, the recognition layer OUA12, and the recognition layer OUA13 are provided for the output wiring OA1. The recognition layer OUA14, the recognition layer OLA15, the recognition layer OLA16, and the recognition layer OLA17 are arranged to extend from each input / output wiring to the cell boundary. The attributes of these recognition layers can be changed depending on whether they are the same potential or different potentials with other recognition layers that are in contact with each other at the cell boundary portion. In addition, these recognition layers are configured such that the arrangement positions are set according to a predetermined rule at the boundary portion of the cell and can be arranged in contact with the recognition layers of other cells. FIG. 4B is a plan view of the NAND cell NAND2. In NAND1, the in-cell wiring (recognition layer) connected to the input wiring is arranged on the left and right sides of the cell boundary, whereas in NAND2, the in-cell wiring (recognition layer) connected to the input wiring is The recognition layer is arranged only on one side and connected to the output wiring on the other side. The recognition layer of NAND2 has the same specifications as NAND1. FIG. 5A is a plan view of the NAND cell NAND3 in which the recognition layer connected to the input wiring of the NAND 1 in FIG. 4A is arranged on a side other than the side in the horizontal direction, and FIG. FIG. 5 is a plan view of a NAND cell NAND4 in which recognition layers connected to the input wiring of the NAND2 of FIG. In contrast to the NAND cell of FIG. 4, the NAND cell of FIG. 5 has a recognition layer connected to the input wiring on the upper and lower sides so that it can be used for connection of input signals from other cells that are in contact with the upper and lower sides. The degree of freedom of connection between cells increases, but the area of the cells increases. Therefore, the placement and routing is optimized by using the NAND cell of FIG. 4 and the NAND cell of FIG.

  In the NAND cell NAND2 of FIG. 4B, the recognition layer IMA31 is connected to the first input wiring IA3 of the cell, the recognition layer IMA41 is connected to the second input wiring IA4 of the cell, and the recognition layers OUA23, OUA24. , OUA25, OMA21, OMA22, OLA26, OLA27, and OLA28 are connected to the cell output wiring OA2. In the NAND cell NAND3 of FIG. 5A, the recognition layers IUA53, IMA51, IMA52, and ILA54 are connected to the first input wiring IA5 of the cell, and the recognition layers IUA62 and IMA61 are connected to the second input wiring IA6 of the cell. The recognition layers OUA32, OUA33, OUA34, OMA31, OLA35, OLA36, OLA37 are connected to the cell output wiring OA3. Further, in the NAND cell NAND4 of FIG. 5B, the recognition layers IUA72 and IMA71 are connected to the first input wiring IA7 of the cell, and the recognition layers IMA81 and ILA82 are connected to the second input wiring IA8 of the cell and recognized. The layers OUA43, OUA44, OUA45, OMA41, OMA42, OLA46, OLA47, OLA48 are connected to the cell output wiring OA4.

  FIGS. 6A and 6B and FIGS. 7A and 7B are plan views of the NOR cell according to the first embodiment. Similar to the inverter cell of FIG. 3 and the NAND cell of FIGS. 4 and 5, a recognition layer is provided which is connected to the input / output function wiring of the cell and contacts the boundary of the cell on the wiring grid. This recognition layer is a virtual wiring defined as a wiring layer of the same type as the wiring in the cell. The connection attribute is changed depending on whether it is the same potential or different potential as the recognition layer of another cell that is in contact with the boundary of the cell, and it is connected to another cell as a wiring or deleted.

  The NOR cell NOR1 of FIG. 6A is provided with the input wiring IR1 on the right side and the input wiring IR2 on the left side, and the recognition layer IMR11, the recognition layer are connected to the right and left adjacent cells through the recognition layer, respectively. The IMR 12 and the recognition layer IMR21 are arranged. The NOR cell NOR2 in FIG. 6B is an example in which the recognition layer IMR31 and the recognition layer IMR41 are arranged so that both the input wiring IR3 and the input wiring IR4 can be connected on the right side. In addition, the NOR cell NOR3 in FIG. 7A is an example in which input wiring is added so that the input wiring of the NOR cell NOR1 in FIG. Further, NOR4 in FIG. 7B is an example in which input wiring is added so that the input wiring of the NOR cell NOR2 in FIG. Similar to the cell pattern of the NAND cell, the layout pattern of the NOR cell in FIGS. 7A and 7B increases the degree of freedom of connection between the cells compared to the layout pattern of the NOR cell in FIGS. 6A and 6B. However, the added input wiring and the cell area increase. By selectively using these cells in consideration of the cell arrangement of the layout and the state of wiring, the demerits of each cell can be alleviated.

  In the NOR cell NOR1 in FIG. 6A, the recognition layers IMR11 and IMR12 are connected to the first input wiring IR1 of the cell, the recognition layer IMR21 is connected to the second input wiring IR2 of the cell, and the recognition layer OUR12. , OUR13, OUR14, OMR11, OLR15, OLR16, OLR17 are connected to the cell output wiring OR1. In the NOR cell NOR2 of FIG. 6B, the recognition layer IMR31 is connected to the first input wiring IR3 of the cell, the recognition layer IMR41 is connected to the second input wiring IR4 of the cell, and the recognition layers OUR23, OUR24. , OUR25, OMR21, OMR22, OLR26, OLR27, OLR28 are connected to the cell output wiring OR2.

  Further, in the NOR cell NOR3 of FIG. 7A, the recognition layers IUR53, IMR51, IMR52, and ILR54 are connected to the first input wiring IR5 of the cell, and the recognition layers IMR61 and ILR62 are connected to the second input wiring IR6 of the cell. The recognition layers OUR32, OUR33, OUR34, OMR31, OLR35, OLR36, and OLR37 are connected to the cell output wiring OR3. In the NOR cell NOR4 of FIG. 7B, the recognition layers IUR72 and IMR71 are connected to the first input wiring IR7 of the cell, and the recognition layers IMR81 and ILR82 are connected to the second input wiring IR8 of the cell and recognized. The layers OUR43, OUR44, OUR45, OMR41, OMR42, OLR46, OLR47, OLR48 are connected to the cell output wiring OR4.

  In the standard cells of FIGS. 3 to 7 described above, the intra-cell wiring other than the recognition layer is wired inside the cell boundary at a certain distance from the cell boundary. Therefore, no matter how the cells are arranged adjacent to each other, the wiring other than the recognition layer does not contact the intra-cell wiring of other cells. Therefore, if the recognition layer of the different potential is deleted, even if the boundary portion of the cell and the boundary portion of the other cell are arranged in close contact with each other without placing a distance, the wiring of the different potential with the other cell is short-circuited. There is no.

  Each of the standard cells in FIGS. 3 to 7 is a combination cell standard cell having one or more input wirings and one or more output wirings. In addition, an input / output circuit connected to a bus, etc. A standard cell provided with one or a plurality of input / output wirings in addition to the input wiring or the output wiring may be provided. Each standard cell includes an input / output function wiring that is one of an input wiring, an output wiring, and an input / output wiring.

  Next, FIG. 8 shows the result of arranging and wiring the circuit in which the adjacent arrangement is designated by the adjacent arrangement restriction F1 shown in FIG. 1A using the standard cell shown in FIGS. 3 to 7 according to the flowchart of FIG. Shown in FIG. 8 shows a part of standard cells arranged in a matrix in the adjacent cell arrangement step of step S1 in FIG. 8 basically includes the inverter cell INV1 of FIG. 3A as the inverter circuit A, the inverter cell INV2 of FIG. 3B as the inverter circuit D, and the NAND of FIG. 5B as the NAND circuit B. The NOR cell NOR3 of FIG. 7A is used as the cell NAND4 and the NOR circuit C, respectively. However, the inverter cell A, NOR cell C, and inverter cell D use cells INV1M, NOR3M, and INV2M in which INV1, NOR3, and INV2 are mirrored so that the left and right sides are reversed, and further, inverter cell A (INV1M), NAND Each of the cells B (NAND4) is rotated 180 degrees upside down.

  In the adjacent cell placement step S1 in FIG. 2, input / output information and instance information of the inverter circuit A, NAND circuit B, NOR circuit C, and inverter D surrounded by the adjacent placement constraint F1 in FIG. These are arranged so that the cell boundaries are adjacent as much as possible when arranging the cells. At the time of arrangement, cells are arranged by giving priority to the arrangement in the order of signal flow from the input / output relationship. FIG. 8 shows the arrangement result, and the cells are arranged so that the boundaries of the cells are adjacent to each other by the adjacent arrangement constraint F1. Here, all the cells in the standard cell library may be preliminarily set as cells having a recognition layer between at least one of the input wiring and the output wiring and the upper and lower ends of the cell as described above. The cells in the library are configured in the same manner as the conventional standard cells, and only the cells used for the layout of the block surrounded by the adjacent layout constraint F1 are selectively selected before the cell placement, as described above. A cell in which a recognition layer is provided between at least one of the cells and the upper and lower ends of the cell may be used. In either case, when a cell in a block surrounded by the adjacent placement constraint F1 is placed, the cell has a recognition layer between at least one of the input wiring and the output wiring and the upper and lower ends of the cell. Just do it. At the cell boundary, the recognition layer standardized at a certain wiring pitch is in contact with the input / output wiring of each cell. In FIG. 8, since the recognition layer IM11 and the recognition layer IMA81 that are in contact with each other at the boundary between the cell A and the cell B have the same potential due to the input / output relationship of the cells, the attributes of each recognition layer are changed so that the wiring is short-circuited. Since the recognition layer IM12 and the recognition layer IMA71 that are in contact with each other at the boundary between the cell A and the cell B have different potentials in the input / output relationship of the cells, the attribute of each recognition layer is changed so that the wiring is not short-circuited. Similarly, the boundary between the cell A and the cell C, the boundary between the cell B and the cell C, the boundary between the cell B and the cell D, and the boundary between the cell C and the cell D are in contact with each other at each boundary. Change the attribute of the recognition layer to short or open according to the input / output relationship. As a result, as shown in FIG. 8, a wiring connection pattern is formed depending on whether the recognition layer in contact with each cell boundary is the same potential or different potential, and a series of input / output connections from the inputs INA and INB to the output OUTC. Is completed in the recognition layer prepared in the cell. That is, all the wirings that are short-circuited by the recognition layer are the recognition layers in the cell, and are data that existed in each cell before placing the cell. By arranging the recognition layers of other cells having the same potential in contact with each other, adjacent cells can be connected without using wiring between cells other than the cell data.

  Next, the wiring structure around the standard cell will be described with reference to FIGS. As shown in FIG. 8, power supply wiring extending along the direction in which each cell row extends is arranged around the standard cell. The power supply wiring includes ground wiring. Specifically, the power supply wiring M2 (VDD) of the second wiring layer and the ground wiring M2 (GND) of the second wiring layer are included. FIG. 9 is a drawing showing a three-dimensional structure of a semiconductor integrated circuit using the standard cell of the first embodiment. FIG. 9A is a plan view showing the structure below the first wiring layer for the inverter cell INV2 of FIG. 3B, and FIG. FIG. 9C is a plan view after wiring layers are wired, and FIG. 9C is a CC ′ sectional view thereof. In FIG. 9B, the second wiring layer is displayed semi-transparently so that the relative positions of the via V1 and the second wiring layer and the structure below the first wiring layer can be understood. In FIG. 9C, the interlayer insulating film and the gate wiring layer are omitted. As shown in FIG. 9, the power and ground are supplied to the standard cell from the second wiring layer M2. The power supply VDD is wired from the power supply wiring M2 (VDD) of the second wiring layer to the power supply wiring M1 (VDD) of the first wiring layer via the via V1, and further from there, the P-type diffusion layer P + serving as the source of the PMOS transistor Is supplied with power. The ground GND is wired from the ground wiring M2 (GND) of the second wiring layer to the ground wiring M1 (GND) of the first wiring layer via the via V1, and from there, the N-type diffusion that becomes the source of the NMOS transistor Power is supplied to layer N +. Further, M2-1 to M2-3 are wirings of the second wiring layer used for wiring between distant cells. In this embodiment, the first wiring layer is a tungsten wiring layer and is used for wiring in the cell. The second wiring layer is an aluminum wiring layer. Further, a wiring layer may be further provided on the second wiring layer, and it may be used for connection between distant cells or for strengthening a power supply or ground wiring. According to the above configuration, since the power supply to each standard cell is performed using the second wiring layer M2, the cells in the other cell columns arranged adjacent to each other can be connected to the wiring in the cell (the first wiring M1). ) Only. That is, even if the wiring in the cell (first wiring layer) is extended to the end of the cell boundary in the direction orthogonal to the direction in which the cell row extends (the left-right direction in FIG. 9), the power and ground are supplied to the cell. There is no hindrance.

  The automatic placement and routing method of the semiconductor integrated circuit according to the first embodiment can also be executed by a computer program that operates on a general-purpose computer such as an EWS or a personal computer. In the flowchart of FIG. 2, circuit information 1, cell information 2, and cell neighbor information 3 are stored as files in a computer storage device, and steps S1 to S4 are executed by a computer program based on the information stored in the storage device. The adjacent cell placement process, cell placement process, boundary wiring connection deletion process, and layout wiring process can be advanced. In addition, information in the middle of the layout in each process can be stored by using the layout data 4 or a temporary storage file (not shown) so that the processing can proceed. The computer program can be installed in the computer through a communication line such as the Internet, or can be installed in the computer via a storage medium such as a DVD, CD, or flash memory.

  The cell information 2 includes information on the position of the recognition layer at the cell boundary and the name of the input / output function wiring to which the recognition layer is connected. Using this information, in the adjacent cell placement step of step S1 The recognition layers connected to the input / output function wirings having the same potential in a plurality of cells can be arranged so as to be in contact with each other. In the cell information 2, a plurality of types of cells having different recognition layer positions and numbers are provided for cells having the same function, and in the adjacent cell placement step, cells are connected only by intra-cell wiring using the recognition layer. In view of this, an optimal cell may be selected from a plurality of types of cells having the same function. For example, in the case of an inverter circuit, it is possible to select whether to use INV1 in FIG. 3A, INV3 in FIG. 3C, or invert right and left of INV1 or INV2 and use a mirrored cell. May be. The same applies to the NOR circuit and NAND circuit.

  Further, in the boundary wiring connection deletion step in step S3, information on the position where the cell is arranged in step S1 or step S2, information on the position of the recognition layer included in the cell information and information on the input / output function wiring to which the recognition layer is connected Thus, it is possible to recognize cells and their input / output function wirings that are to be connected to each other via the recognition layer. If this matches the circuit connection information included in the circuit information 1, the attributes of the recognition layer are changed so that the cells are connected by intra-cell wiring by the recognition layer, and the data of the recognition layer is converted into actual wiring data. Thus, the input / output function wirings of adjacent cells are connected only by the wirings in the cells. On the other hand, if the connection relationship is not included in the circuit information 1, if the recognition layer is connected as it is, a signal with a different potential is short-circuited, and therefore the data in the recognition layer is not converted into actual wiring data. In this way, the recognition layer data is changed and the recognition layer data is deleted from the wiring data.

  Further, when the recognition layer is not originally included in the cell library information, in the adjacent cell placement step of step S1, the cells that need to be placed adjacent to each other are extracted with reference to the cell neighbor information 3 and the circuit information 1. For the cells that need to be adjacently arranged, cell information data with the recognition layer data added is generated from the cell information not including the recognition layer data, and the cell information with the recognition layer added is stored as cell information 2. Later processing can proceed.

  In the above-described embodiment, an example of a circuit in which the wiring becomes long when there are two or more input signals in FIG. In addition to this, when there are multiple systems of output signals and gates must be added to each of the branched signals, similarly, if they are arranged in a single cell row, the wiring may become long. is there. Even in such a case, the present invention can be used to wire-connect cells arranged in a plurality of cell rows using only the intra-cell wiring.

  In particular, in the present invention, even when cells are arranged in different cell columns, cell boundaries can be connected with lower wirings at the stage of cell arrangement, and the optimum cell arrangement considering the connection of adjacent wirings Can be made. Therefore, it is possible to reduce the number of necessary wirings to be connected by the upper wiring as much as possible, increase the degree of freedom of the wiring area of the upper wiring to be wired in the layout, and increase the wiring efficiency.

  Although the embodiments have been described above, the present invention is not limited only to the configurations of the above embodiments, and of course includes various modifications and corrections that can be made by those skilled in the art within the scope of the present invention. It is.

1: Circuit information 2: Cell information 3: Cell adjacency information 4: Layout data A, D: Inverter circuit B: NAND circuit C: NOR circuit netA, netB, netC: Output signal F1: Adjacent layout constraint IU13, IU23, IM11, IM12, IM21, IM22, IM31, IM32, IL14, IL24, OU13, OU14, OU23, OU24, OU25, OU33, OU34, OM11, OM12, OM21, OM22, OM31, OM32, OL15, OL16, OL26, OL27, OL28, OL35, OL36, IUA53, IUA62, IUA72, IMA11, IMA12, IMA21, IMA31, IMA41, IMA51, IMA52, IMA61, IMA71, IMA81, ILA54, ILA82, OUA12, UA13, OUA14, OUA23, OUA24, OUA25, OUA32, OUA33, OUA34, OUA43, OUA44, OUA45, OMA11, OMA21, OMA22, OMA31, OMA41, OMA42, OLA15, OLA16, OLA17, OLA26, OLA26, OLA26 OLA37, OLA46, OLA47, OLA48, IUR53, IUR72, IMR11, IMR12, IMR21, IMR31, IMR41, IMR51, IMR52, IMR61, IMR71, IMR81, ILR54, OUR12, OUR13, OUR14, OUR23, OUR23, OUR23, RUR24, UR24, UR24, OUR34, OUR43, OUR44, OUR45, OMR11, OMR 1, OMR22, OMR31, OMR41, OMR42, OLR15, OLR16, OLR17, OLR26, OLR27, OLR28, OLR35, OLR36, OLR37, OLR46, OLR47, OLR48, OLR62, OLR82: recognition layer (imaginary boundary line)
I1, I2, I3, IA1, IA2, IA3, IA4, IA5, IA6, IA7, IA8, IR1, IR2, IR3, IR4, IR5, IR6, IR7, IR8: input wiring O1, O2, O3, OA1, OA2, OA3, OA4, OR1, OR2, OR3, OR4: output wiring M1 (VDD): power wiring of the first wiring layer M1 (GND): ground wiring of the first wiring layer M2 (VDD): power wiring of the second wiring layer M2 (GND): ground wiring of the second wiring layer M2-1, M2-2, M2-3, M2-4: wiring of the second wiring layer V1: wiring of the first wiring layer and wiring of the second wiring layer Connecting via

Claims (19)

A first and second cell row each having a plurality of standard cells arranged side by side, the first and second cell rows arranged in contact with each other in the long side direction extending in parallel to each other;
A first input / output function wiring which is one of an input wiring, an output wiring and an input / output wiring of one of the plurality of first standard cells arranged in the first cell row; A second input / output function wiring of at least one cell of the plurality of second standard cells arranged in the second cell row is connected to the first input / output function wiring in the same wiring layer; A semiconductor device characterized by comprising:   The at least one cell of the plurality of first standard cells and the at least one cell of the plurality of second standard cells are in contact with each other at least a part of a cell boundary of each cell. The semiconductor device according to claim 1, wherein the semiconductor device is arranged.   3. The semiconductor according to claim 2, wherein the first input / output function wiring and the second input / output function wiring are extended to the cell boundary of a standard cell including each wiring. apparatus.   4. The semiconductor according to claim 1, wherein the first input / output function wiring and the second input / output function wiring are formed in a wiring layer below the power supply wiring. 5. apparatus.   At least one cell of the plurality of first standard cells includes at least one of the plurality of second standard cells not in contact with each cell and the same wiring layer as the power supply wiring or 5. The semiconductor device according to claim 1, wherein the semiconductor device is connected via an upper wiring layer than the power supply wiring. 6. A method for manufacturing a semiconductor device, comprising:
A first cell arrangement process for arranging a plurality of standard cells in a matrix along each of a first direction and a second direction orthogonal to the first direction;
The standard cells arranged adjacent to each other along the first direction are the same as the input / output function wiring that is one of the input wiring, output wiring, and input / output wiring of each of the plurality of standard cells. A first wiring process for connecting using the wiring layers of the layers;
A second wiring process for connecting at least one pair of standard cell pairs arranged adjacent to each other along the second direction using a wiring layer of the same layer as the input / output function wiring;
A method for manufacturing a semiconductor device, including a method for designing a semiconductor device.   The first cell arrangement process is a process of arranging the plurality of standard cells with reference to cell information including information of standard cells corresponding to each of a plurality of circuit elements included in the semiconductor device, The at least part of standard cells included in the information includes a recognition layer arranged between the input / output function wiring and a cell boundary and capable of setting whether or not to use the wiring as a wiring. The method described.   The said 1st cell arrangement | positioning process is provided with the process which arrange | positions so that the recognition layer of the standard cell arrange | positioned adjacent to each other among these standard cells may mutually contact. Method.   Whether or not to use each of the plurality of standard cells between the input / output function wiring and the cell boundary as a wiring between the first cell placement processing and the first wiring processing. The method according to claim 6, comprising the step of adding a configurable recognition layer.   The process of adding the recognition layer includes a process of adding the recognition layer so that recognition layers of standard cells arranged adjacent to each other among the plurality of standard cells are in contact with each other. 9. The method according to 9.   In the second wiring process, the recognition layer of each of at least one pair of cells of the standard cell pair is used as a wiring based on connection information that is information on connection between a plurality of circuit elements included in the semiconductor device. The method according to any one of claims 7 to 10, further comprising a process of setting whether or not to use.   The second wiring process uses the recognition layer as a wiring when the recognition layer in contact between at least one pair of cells of the standard cell pair has the same potential, and uses the recognition layer when the potential becomes different. The method according to claim 7, wherein the method is not used as wiring.   The first cell arrangement processing is a group including some circuit elements among the plurality of circuit elements included in the semiconductor device, and each of the plurality of connections between the some circuit elements is the shortest. The first standard cells corresponding to each of the partial circuit elements are arranged along the first direction and the second direction based on the adjacent information designating the group including the circuit elements arranged as described above. The method according to any one of claims 6 to 12, comprising a process of arranging in a matrix. A second cell arrangement process for arranging a second standard cell corresponding to each of the remaining circuit elements in the plurality of circuit elements between the first cell arrangement process and the first wiring process. With
After the second wiring process, a standard corresponding to the remaining connections among the connections between the plurality of circuit elements based on connection information that is information on connections between the plurality of circuit elements included in the semiconductor device. The method according to claim 13, further comprising a third wiring process for forming a connection between cells in a wiring layer different from the wiring layer in the standard cell.   Connection information, which is connection information between a plurality of circuit elements included in the semiconductor device, cell information including information on a standard cell corresponding to each of the plurality of circuit elements included in the semiconductor device, and the semiconductor device A group including a part of circuit elements included in the plurality of circuit elements included, and a group including the circuit elements arranged so that each of the plurality of connections between the part of the circuit elements is shortest is specified. 7. The adjacency information is input to a predetermined device, and the first cell placement processing, the first wiring processing, and the second wiring processing are automatically performed. Method. A cell data structure included in the standard cell library for automatic placement and routing,
Each cell has actual layout data placed within the cell boundary,
A virtual boundary wiring that is connected to an input / output function wiring that is one of an input wiring, an output wiring, and an input / output wiring of the cell and is in contact with a cell boundary on a wiring grid, and the first cell boundary of the cell and the first cell A plurality of recognition layers provided corresponding to each of the second cell boundaries orthogonal to the cell boundary;
With
The recognition layer is converted into actual wiring data when it is in contact with a recognition layer or wiring of the same potential of another cell after the relative arrangement position with other cells arranged adjacent to each other is determined. A data structure of a standard cell library for automatic placement and routing, which is configured to be deleted without being converted into an actual wiring when it is in contact with a different potential recognition layer or wiring of another cell.   Wiring data other than the recognition layer of the cell is wired away from a cell boundary by a certain distance or more, and the recognition layer is configured such that, among the wiring data, the wiring data connected to the input / output function wiring and the cell boundary 17. The automatic placement according to claim 16, wherein wiring data connected to the input / output wiring is extended to a cell boundary when the recognition layer is converted into an actual wiring. Data structure of standard cell library for wiring.   18. The data structure of a standard cell library for automatic placement and routing according to claim 16, wherein a plurality of types of cells are provided for cells having the same function depending on the arrangement position and number of recognition layers.   19. The recognition layer is configured not to be used for wiring between distant cells but to be converted into actual wiring data of a wiring layer used for wiring in a cell. A data structure of a standard cell library for automatic placement and routing according to any one of the preceding claims.

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