TWI704467B - Method of producing layout of semiconductor device, method of designing layout of semiconductor device, and method of fabricating semiconductor device - Google Patents

Abstract

Provided are a method of producing a layout of a semiconductor device, a method of designing a layout of a semiconductor device, and a method of fabricating a semiconductor device. The method of designing a layout of a semiconductor device includes preparing a standard cell layout including creating a preliminary pin pattern in at least one interconnection layout, performing a routing step to connect the preliminary pin pattern to a high-level interconnection layout, and generating a pin pattern in the interconnection layout, based on hitting information obtained at the completion of the routing step. The pin pattern is smaller than the preliminary pin pattern.

Description

Method for generating layout of semiconductor device and designing semiconductor device Layout method and method of manufacturing semiconductor device [Priority Statement]

This patent application claims the priority of Korean patent applications No. 10-2015-0108171 and No. 10-2015-0157565 filed at the Korea Intellectual Property Office on July 30, 2015 and November 10, 2015. The content of the Korean patent application is incorporated into this case for reference.

The concept of the present invention relates to the interconnection of active components of semiconductor devices, such as metal lines and contact windows. More specifically, the concept of the present invention relates to a method for designing the layout of a semiconductor device containing a field effect transistor and a method for manufacturing a semiconductor device using the same.

Due to its size, multi-function, and/or low-cost characteristics, semiconductor devices Favored in the electronics industry. Semiconductor devices can be classified into memory devices for storing data, logic devices for processing data, or hybrid devices including both memory devices and logic devices. In order to meet the increasing demand for high-speed operation and/or low power consumption electronic devices, it is necessary to produce semiconductor devices that provide high performance and/or have multiple functions and maintain high reliability. To meet these technical requirements, the complexity and/or integrated density of semiconductor devices is increasing.

According to the concept of the present invention, a method for generating a layout of a semiconductor device is provided, including: providing a standard cell layout, and providing the standard cell layout includes creating a preliminary pin pattern of the interconnection layout of the standard cell layout; Wiring step to generate a high-level interconnect layout in which the preliminary pin pattern is connected to a high-level interconnect pattern; and all the layouts in the standard cell based on the hit information obtained when the wiring step is completed A late pin pattern is generated in the area of the interconnection layout, and the late pin pattern is smaller than the preliminary pin pattern.

According to the concept of the present invention, a method for designing the layout of a semiconductor device is also provided, which may include: providing a first standard cell layout and a second standard cell layout in a cell library, providing the first standard cell layout and The second standard cell layout includes arranging a first preliminary pin pattern and a second preliminary pin pattern on the first standard cell layout and the second standard cell layout, respectively; and arranging the first standard Cell layout and the second standard cell layout; implementing a wiring step to connect the first preliminary pin pattern and the second preliminary pin pattern to a high-level interconnect layout; And using the first preliminary pin pattern and the second preliminary pin pattern to generate a first pin pattern and a second pin pattern based on hit information obtained after the wiring step. The first preliminary pin pattern and the second preliminary pin pattern may be the same as each other in size and arrangement, and the first pin pattern and the second pin pattern may be different from each other in size and arrangement .

According to the concept of the present invention, a method of manufacturing a semiconductor device is also provided, including: a process of generating a device layout of the semiconductor device; and manufacturing the semiconductor device using the device layout. The process of generating the device layout includes: obtaining a standard cell layout and an interconnection layout, the standard cell layout including the layout of active elements and/or regions of the semiconductor device, and the interconnection layout including preliminary pins A pattern, the preliminary pin pattern defining a region in the semiconductor device containing a position of a lower contact window that is to be electrically connected to at least one of the active element and/or region; performing a wiring step includes Overlay a high-level interconnect pattern and an upper contact window pattern on the standard cell layout, wherein the high-level interconnect pattern crosses the preliminary pin pattern and the high-level interconnect pattern represents the high-level interconnect of the semiconductor device , And the upper contact window pattern is placed at the intersection of the high-level interconnect pattern and the preliminary pin pattern and represents the position of the upper contact window of the semiconductor device; based on the wiring step, a The hit information of the position of the upper contact window; and using the hit information to generate a late pin pattern, the late pin pattern representing the semiconductor device including both the lower contact window and the upper contact window Area. Manufacturing the semiconductor device includes: forming active elements and/or regions laid out based on the standard cell layout at an upper portion of a substrate; And forming a contact window connecting the multilayer metal line to the active device, wherein the multilayer metal line includes a lower-level metal layer and an upper-level metal layer, the lower-level metal The layer includes a lower-level metal interconnection corresponding to the later pin pattern, and the upper-level metal layer includes an upper-level metal interconnection corresponding to the high-level interconnect, and the contact window includes a first A contact window and a second contact window, the first contact window corresponds to the lower contact window and is sandwiched between the lower level metal interconnection and at least one of the active element and the The lower level metal interconnection is electrically connected to the at least one of the active devices, and the second contact window corresponds to the upper contact window and is sandwiched between the lower level metal interconnection and the The upper-level metal interconnections are electrically connected to the lower-level metal interconnections and the upper-level metal interconnections.

10: Central processing unit

30: working memory

32: Layout design tools

34: Simulation tool

50: Input-output device

70: storage device

90: System Interconnect

100: substrate

110: The first interlayer insulating layer

120: second interlayer insulating layer

130: third interlayer insulating layer

140: fourth interlayer insulating layer

150: fifth interlayer insulating layer

A, B, C, D: standard cell layout

AF: Channel area

CA: source/drain contact

CB: gate contact

CP: top cover pattern

D1: First direction

D2: second direction

FN: Active pattern

GI: Gate insulation pattern

GP: Gate pattern

GS: Gate spacer

I-I’, II-II’, III-III’: Line

M11, M12: pin pattern

M13: Third pin pattern

M14: Fourth pin pattern

M21: First interconnection pattern

M22: Second interconnection pattern

M23: third interconnection pattern

M24: Fourth interconnection pattern

M31: First upper interconnection pattern

M32: The second upper interconnection pattern

M33: The third upper interconnection pattern

M41: The first lower metal wire

M42: The second lower metal wire

M51: The first upper metal wire

M52: The second upper metal wire

M61: First lower interconnection pattern

M62: The second lower interconnection pattern

M63: The third lower interconnection pattern

M71: The first pin pattern

M72: second pin pattern

M73: Third pin pattern

MA1, MA2: Ghost pattern

NR: NMOSFET area

PI: Pin area

PL1: First power pattern

PL2: second power pattern

PL3: First power cord

PL4: second power cord

PM11, PM12: preliminary pin pattern

PM13, PM23: The third preliminary pin pattern

PM14: Fourth preliminary pin pattern

PM21: First preliminary pin pattern

PM22: The second preliminary pin pattern

PR: PMOSFET area

RG1: District 1

RG2: District 2

S110, S120, S130, S140, S150, S121, S122, S123, S124: steps

SD: source/drain region

ST1: first device isolation layer

ST2: Second device isolation layer

STD1: The first standard cell layout

STD2: Second standard cell layout

V11: The first lower contact window pattern

V12: The second lower contact window pattern

V21, V31: the first upper contact window pattern

V22, V32: second upper contact window pattern

V23: The third upper contact window pattern

V24: The fourth upper contact window pattern

V33: The third upper contact window pattern

V41: The first lower contact window

V42: The second lower contact window

V51: The first upper contact window

V52: The second upper contact window

V61: First contact window pattern

V62: The second contact window pattern

V63: The third contact window pattern

The concept of the present invention will be understood more clearly by reading the following detailed description of the non-limiting examples of the concept of the present invention in conjunction with the accompanying drawings.

FIG. 1 is a block diagram illustrating a computer system used to implement a semiconductor design process according to some examples of the inventive concept.

2 is a flowchart illustrating a method of designing and manufacturing a semiconductor device according to some examples of the inventive concept.

FIG. 3 is a flowchart illustrating some steps of the layout design shown in FIG. 2.

4A, 4B, 5A, and 5B are plan views illustrating a method of laying out standard cells and establishing a wiring structure for them, for explaining the method according to the concept of the present invention Some advantages and benefits.

6A, 6B, and 6C are plan views illustrating a method of laying out standard cells and establishing a wiring structure for them according to some examples of the concept of the present invention.

7A, 7B, and 7C are cross-sectional views taken along line I-I', line II-II', and line III-III' shown in FIG. 6C, respectively, to illustrate semiconductors according to some examples of the concept of the present invention Device.

8A, 8B, and 8C are plan views illustrating a method of laying out standard cells and establishing a wiring structure for them according to some examples of the concept of the present invention.

9A, 9C, and 9D are plan views illustrating a method of laying out standard cells and establishing a wiring structure for them according to some examples of the concept of the present invention.

FIG. 9B is a plan view illustrating the layout of each standard cell whose interconnection layout is different from each other.

10A, FIG. 10B, and FIG. 10C are plan views illustrating a method of laying out a standard cell and establishing a wiring structure for it according to some examples of the concept of the present invention.

11A and 11B are plan views illustrating a method of laying out standard cells and establishing a wiring structure for them according to some examples of the concept of the present invention.

FIG. 1 is a block diagram of a computer system used to implement an example of a semiconductor design process according to the concept of the present invention. 1, the computer system may include a central processing unit (CPU) 10, a working memory 30, an input-output device (I/O device) 50 and a storage device 70. In some instances, the computer system may be a customized system for implementing the layout design process according to the concept of the present invention. System. In addition, the computer system may include a computing system for executing various design and inspection simulation programs.

The central processing unit 10 can be used to run various software, such as applications, operating systems, and device drivers. For example, the central processing unit 10 can be used to run an operating system (not shown in the figure) loaded on the working memory 30. In addition, the central processing unit 10 can be used to run various applications on the operating system. For example, the central processing unit 10 can be used to run the layout design tool 32 loaded on the working memory 30.

The operating system or application program can be loaded into the working memory 30. For example, when the computer system starts a booting operation, the operating system image (not shown in the figure) stored in the storage device 70 can be loaded onto the working memory 30 according to the boot sequence. In the computer system, the overall input/output operations can be managed by the operating system. Similarly, certain applications-which can be selected by the user or provided for basic services-can be loaded onto the working memory 30. According to some examples of the concept of the present invention, the layout design tool 32 prepared for the layout design process can be loaded from the storage device 70 onto the working memory 30.

The layout design tool 32 can provide a function for changing the biasing data for a specific layout pattern; for example, the layout design tool 32 can be used to make the specific layout pattern have a shape and position defined by the design rule. Different shapes and positions. The layout design tool 32 can be used to perform a design rule check (DRC) under the condition that the bias data is changed. The working memory 30 may include a volatile memory device (for example, static random access memory (static random access memory (SRAM) device or dynamic random access memory (DRAM) device) or non-volatile memory device (for example, phase change random access memory (PRAM) ), magnetic random access memory (magnetic random access memory, MRAM), resistive random access memory (resistive random access memory, ReRAM), ferroelectric random access memory (ferroelectric random access memory, FRAM) or reverse Or flash memory (NOR FLASH memory) device).

In addition, the simulation tool 34 can be loaded on the working memory 30 to perform optical proximity correction (OPC) operations on the designed layout data.

The input-output device 50 can be used to control user input operations and user output operations of the user interface device. For example, the input-output device 50 may include a keyboard or a monitor, so that the designer can input relevant information. By using the input-output device 50, the designer can receive the information of several regions or data paths of the semiconductor device to which the adjusted operating characteristics will be applied. The input-output device 50 can be used to display the process status or process result of the simulation tool 34.

The storage device 70 can serve as a storage medium of the computer system. The storage device 70 can be used to store application programs, operating system images, and various data. The storage device 70 may include a memory card (for example, a multimedia card (MMC), an embedded multimedia card (eMMC), a secure digital card (SD), a micro secure digital card) , MicroSD), etc.) or hard disk drive (HDD). The storage device 70 may include a NAND FLASH memory device with a large memory capacity. Alternatively, the storage device 70 may include at least one next-generation non-volatile memory device (for example, PRAM, MRAM, ReRAM, or FRAM) or a NOR FLASH memory device.

The system interconnect 90 can act as a system bus to enable the creation of a network in the computer system. The central processing unit 10, the working memory 30, the input-output device 50, and the storage device 70 can be electrically connected to each other through the system interconnect 90, and thus can exchange data therebetween. However, the system interconnect 90 may not be limited to only being composed of bus bars; to be precise, it may include additional components for improving the efficiency of data communication.

2 is a flowchart illustrating a method of designing and manufacturing a semiconductor device according to some examples of the inventive concept.

Referring to FIG. 2, the computer system described with reference to FIG. 1 can be used to implement the high-level design process of the semiconductor integrated circuit (step S110). For example, in the high-level design process, a high-level computer language (for example, C language) can be used to describe the integrated circuit to be designed. The circuit designed by the high-level design process can be described in more detail by coding or simulation by register transfer level (RTL). In addition, the code generated by the register transfer layer level writing code can be converted into a netlist, and the results can be combined with each other to generate a schematic diagram of all circuit systems of the semiconductor device. The schematic diagram (the operability or practicability represented) can be checked by a simulation tool (the reason for the semiconductor device). In some instances, the Check the result of the step and further implement the adjustment step.

The layout design process can be implemented to achieve a logically complete form of the semiconductor integrated circuit on the silicon wafer (step S120). For example, the layout design process can be implemented based on the schematic circuit or the corresponding netlist prepared in the high-level design process. The layout design process may include a wiring step, the wiring step includes laying out various standard cells provided from a cell library and various standard cells provided by the self-cell library based on predetermined design rules. Yuan to connect. In the layout design process according to some examples of the inventive concept, a pin pattern may be formed in each of the standard cells based on the hit information obtained after the wiring step.

The cell library may contain information about the operation, speed and power consumption of the cell. In some examples, a cell library that represents the layout of the circuit at the gate level may be provided in a layout design tool or defined by the layout design tool. Here, the layout can be prepared to define or describe the shape, position, or scale used to form the pattern of transistors and metal lines that will actually be formed on the silicon wafer. For example, in order to actually form an inverter circuit on a silicon wafer, it may be necessary to prepare or draw certain patterns (for example, P-channel metal oxide semiconductor (PMOS), N-channel metal oxide semiconductor (NMOS), N well (N -WELL), the layout of the gate electrode and the pattern of the metal line on it). For this, at least one of the inverters in the cell library can be selected. Thereafter, a wiring step to connect the selected cells to each other can be performed. These steps can be performed automatically or manually in the layout design tool. In some instances, you can use the Place & Routing tool to automatically implement the layout of standard cells and Its steps to establish a wiring structure.

After the wiring step, a verification step can be performed on the layout to check whether any part of the schematic circuit violates a given design rule. In some instances, the verification step may include evaluating verification items, such as design rule check (DRC), electrical rule check (ERC), and layout vs. shematic (LVS). Evaluation of design rule check items can be implemented to evaluate whether the layout meets the given design rules. The evaluation of electrical rule check items can be implemented to evaluate whether there is an electrical disconnection problem in the layout. The evaluation of the layout diagram to the schematic items can be carried out to evaluate whether the layout is prepared to conform to the gate level netlist.

The optical proximity correction (OPC) step may be implemented (step S130). The optical proximity correction step can be implemented to correct the optical proximity effect that may occur when a photolithography process is performed on a silicon wafer using a photomask manufactured based on the layout. The optical proximity effect may be an undesired optical effect (for example, refraction or diffraction) that may occur during an exposure process using a photomask manufactured based on the layout. In the optical proximity correction step, the layout can be modified to have a reduced shape difference between the designed pattern and the actually formed pattern, which would be caused by the optical proximity effect. As a result of the optical proximity correction step, the designed shape and position of the layout pattern can be slightly changed.

The photomask may be manufactured based on the layout modified by the optical proximity correction step (step S140). Generally speaking, the layout pattern data can be used by setting the glass The chromium layer on the substrate is patterned to manufacture the photomask.

The photomask can be used to manufacture a semiconductor device (step S150). In the actual manufacturing process, the exposure step and the etching step can be repeated, and therefore, the pattern defined in the layout design process can be sequentially formed on the semiconductor substrate.

FIG. 3 is a flowchart illustrating certain steps of the layout design process of the method shown in FIG. 2. 4A, 4B, 5A, and 5B are plan views illustrating a method of laying out standard cells and establishing a wiring structure for them.

3 and 4A, a layout design tool can be used to provide the original standard cell layout (step S121). The standard cell layout may include a logic layout representing the layout of logic transistors, and an interconnection layout. For example, the interconnect layout shown in FIG. 4A may correspond to the first metal layer to be disposed on the semiconductor substrate.

In more detail, providing the logical layout may include providing an active area layout. The active region may include a P channel metal oxide semiconductor field effect transistor (PMOSFET) region PR and an N channel metal oxide semiconductor field effect transistor (NMOSFET) region NR. The PMOSFET region PR and the NMOSFET region NR may be spaced apart from each other in the first direction D1.

Providing the logic layout may also include providing a layout that intersects the PMOSFET region PR and the NMOSFET region NR and extends in the first direction D1 of the gate pattern GP. The gate patterns GP may be spaced apart from each other in a second direction D2 intersecting the first direction D1. The PMOSFET region PR, the NMOSFET region NR and the gate pattern GP can constitute a logic transistor to be disposed on the semiconductor substrate. FIG. 4A also includes a third direction D3 perpendicular to the first direction D1 and the second direction D2.

Providing the interconnection layout may include providing the first power pattern PL1 and the second power pattern PL2 and the first pin pattern M11 and the second pin pattern M12. Each of the first power pattern PL1 and the second power pattern PL2 may be a linear pattern extending parallel to the second direction D2, and each of the first pin pattern M11 and the second pin pattern M12 may be A linear pattern extending parallel to the first direction D1. The first pin pattern M11 and the second pin pattern M12 may be spaced apart from each other in the second direction D2.

Each of the first pin pattern M11 and the second pin pattern M12 may include a pin area PI for wiring with a high-level interconnect layout, which will be explained below. For example, each of the first pin pattern M11 and the second pin pattern M12 may include five pin regions PI.

The standard cell layout can be saved in the cell library described with reference to FIG. 2. Next, the repeated multiple standard cell layouts stored in the cell library can be set on the positioning (step S122). Although a single standard cell layout is shown in FIG. 4A, a plurality of standard cell layouts may be set in alignment with each other in the second direction D2 (for example, see FIG. 11A).

Referring to FIG. 3 and FIG. 4B, a wiring step can be performed on the standard cell layout to connect the standard cell to the high-level interconnect layout (step S123). First, high-level interconnect layout can be provided. The high-level interconnect layout may correspond to the second metal layer to be formed on the semiconductor substrate. In some instances, although not shown in the figure, the high-level interconnect layout may correspond to a plurality of metal layers to be sequentially stacked on the semiconductor substrate.

Providing the high-level interconnection layout may include arranging the first interconnection pattern M21 and the second interconnection pattern M22 and arranging the first upper contact pattern V21 and the second upper part Contact window pattern V22. The connection between the first interconnection pattern M21 and the second interconnection pattern M22 and other standard cell layouts can be taken into account, and the first interconnection pattern M21 and the second interconnection pattern M22 can be automatically set in positioning, and in some In an example, layout design tools and/or placement & routing tools can be used to perform this step. Each of the first interconnection pattern M21 and the second interconnection pattern M22 may be a linear pattern extending parallel to the second direction D2.

The first upper contact window pattern V21 and the second upper contact may be performed at the same time when the first and second interconnect patterns M21 and M22 are laid out or after the first and second interconnect patterns M21 and M22 are laid out The layout of the window pattern V22. The first upper contact window pattern V21 may be provided on one of the pin regions PI of the first pin pattern M11 that overlaps the first interconnect pattern M21. The second upper contact window pattern V22 may be provided on one of the pin regions PI of the second pin pattern M12 that overlaps the second interconnection pattern M22. In other words, the interconnection layout of the standard cell layout can be connected to the interconnection pattern of the high-level interconnection layout through the first upper contact pattern V21 and the second upper contact pattern V22.

Since the wiring of the standard cell layout described with reference to FIGS. 4A and 4B is implemented using the first pin pattern M11 and the second pin pattern M12 respectively including the plurality of pin regions PI, wiring can be increased Degrees of freedom in the steps. For example, regardless of its position, each of the first interconnection pattern M21 and the second interconnection pattern M22 may overlap with at least one of the pin regions PI, and therefore, the first interconnection pattern Each of M21 and the second interconnection pattern M22 may be easily connected to the first pin pattern M11 and the second pin pattern M12. The following will explain which is provided with other shapes The wiring of the standard cell layout of the pin pattern.

3 and 5A, in different examples, (in step S121) a layout design tool can be used to provide the original standard cell layout. In more detail, an interconnect layout may be provided, and providing the interconnect layout may include laying out the first power pattern PL1 and the second power pattern PL2 and laying out the first pin pattern M11 and the second pin pattern M12. In this example, unlike those described with reference to FIGS. 4A and 4B, each of the first pin pattern M11 and the second pin pattern M12 may have two pin regions PI. In other words, each of the first pin pattern M11 and the second pin pattern M12 may be smaller than that described with reference to FIGS. 4A and 4B. Next, the repeated multiple standard cell layouts stored in the cell library can be positioned relative to each other (step S122).

Referring to FIG. 3 and FIG. 5B, a wiring step can be performed on the standard cell layout to connect the standard cell to the high-level interconnect layout (step S123). Providing the high-level interconnection layout may include laying out the first interconnection pattern M21 and laying out the first upper contact pattern V21. Unlike the one described with reference to FIG. 4B, the second interconnection pattern M22 is not provided. This is because the relatively small size of the second pin pattern M12 may make it difficult to overlap the second pin pattern M12 with the second interconnect pattern M22, and therefore, it is difficult to connect the second pin pattern M12 to the second interconnect pattern. With pattern M22.

Compared with what is shown and explained with reference to FIGS. 4A and 4B, the wiring of the standard cell layout explained with reference to FIGS. 5A and 5B has a lower degree of freedom. This is because the first pin pattern M11 and the second pin pattern M12 are smaller than those shown and described in FIGS. 4A and 4B.

Since the first pin pattern M11 and the second pin pattern M12 are relatively small Although it can have low parasitic capacitance, this makes it possible to achieve a semiconductor device with high operating speed characteristics and low power consumption characteristics. In contrast, the relatively large first pin pattern M11 and the second pin pattern M12 described with reference to FIGS. 4A and 4B have high parasitic capacitance, and this hinders the improvement of the operating speed of the semiconductor device and the reduction of the cost. The power consumption of the semiconductor device.

6A to 6C are plan views illustrating a method of laying out a standard cell and establishing a wiring structure for it according to some examples of the concept of the present invention. In the following description, similar or identical reference numbers may be used to identify the elements or steps previously described with reference to FIG. 4A, FIG. 4B, FIG. 5A, and FIG. 5B, so as to avoid redundant description.

3 and 6A, a layout design tool can be used to provide the original standard cell layout (step S121). In more detail, an interconnect layout may be provided, and providing the interconnect layout may include layout of the first power pattern PL1 and the second power pattern PL2 and layout of the first preliminary pin pattern PM11 and the second preliminary pin pattern PM12. In addition, providing the interconnection layout may include laying out the first lower contact window pattern V11 and the second lower contact window pattern V12 to connect the logic layout to the first preliminary pin pattern PM11 and the second preliminary pin pattern PM12, respectively .

Each of the first preliminary pin pattern PM11 and the second preliminary pin pattern PM12 may include a first ghost pattern MA1 and a second ghost pattern MA2. The first ghost pattern MA1 and the second ghost pattern MA2 can be used to define the position of the pin pattern to be established in the subsequent steps; that is, the first ghost pattern MA1 and the second ghost pattern MA2 can serve as markers.

The first ghost pattern MA1 and the second ghost pattern MA2 can be directly connected to each other Connect and form preliminary pin patterns PM11 and PM12. The first ghost pattern MA1 and the second ghost pattern MA2 may be different from or equal to each other in size. In some examples, the first ghost pattern MA1 may be smaller than the second ghost pattern MA2. Here, the first ghost pattern MA1 may have a process margin or a minimum feature size determined by technical limitation factors in a subsequent photolithography process and an etching process.

The standard cell layout can be saved in the cell library described with reference to FIG. 2. Next, the repeated multiple standard cell layouts stored in the cell library can be set on the positioning (step S122). Although a single standard cell layout is shown in FIG. 6A, a plurality of standard cell layouts may be set in alignment in the second direction D2 and parallel to each other in positioning (for example, see FIG. 11A).

Referring to FIG. 3 and FIG. 6B, a wiring step can be performed on the standard cell layout to connect the standard cell to the high-level interconnect layout (step S123). Providing the high-level interconnection layout may include arranging the first interconnection pattern M21 and the second interconnection pattern M22 and arranging the first upper contact pattern V21 and the second upper contact pattern V22. The first interconnection pattern M21 and the second interconnection pattern M22 and the first upper contact pattern V21 and the second upper contact pattern V22 can be automatically laid out in consideration of their interconnection with another standard cell layout.

The first upper contact pattern V21 may be respectively placed on the corresponding one of the overlapping regions of the first preliminary pin pattern PM11 and the second preliminary pin pattern PM12 and the first interconnect pattern M21 and the second interconnect pattern M22 And each of the second upper contact pattern V22. In more detail, the second ghost in the first preliminary pin pattern PM11 The first upper contact pattern V21 is placed on the shadow pattern MA2, and the second upper contact pattern V22 may be placed on the first ghost pattern MA1 of the second preliminary pin pattern PM12. The hit information generated when the wiring step is completed may include the position of the first upper contact pattern V21 and the position of the second upper contact pattern V22.

Referring to FIGS. 3 and 6C, (in step S124) the first pin pattern M11 and the second pin pattern M12 may be provided or generated in the interconnect layout based on the hit information. In more detail, the second ghost pattern MA2 of the first preliminary pin pattern PM11 can be converted into the first pin pattern M11, and the first ghost pattern MA1 of the second preliminary pin pattern PM12 can be converted into the first pin pattern. Two-pin pattern M12. In other words, one of the ghost patterns MA1 and MA2 can be converted into a pin pattern, and the other of the ghost patterns MA1 and MA2 can be removed.

The first lower contact window pattern V11 and the second lower contact window pattern V12 can be connected to the first upper contact window pattern V21 and the second upper contact window respectively by the first pin pattern M11 and the second pin pattern M12 Pattern V22. In other words, the first pin pattern M11 and the second pin pattern M12 can pass the input signal or output signal to be applied to the logic layout.

Although not shown in the figure, in another example according to the inventive concept, the second lower contact window pattern V12 is placed under the second ghost pattern MA2 of the second preliminary pin pattern PM12, and the first Both the ghost pattern MA1 and the second ghost pattern MA2 are converted into the second pin pattern M12 to connect the second lower contact pattern V12 to the second upper contact pattern V22.

According to the above wiring of the standard cell layout, please refer to Figure 4A and Figure 4B The degree of freedom in the wiring step is maximized, and the size of the pin pattern is minimized as described with reference to FIGS. 5A and 5B. This can make it possible to improve the performance characteristics and power consumption characteristics of the semiconductor device.

7A to 7C illustrate a semiconductor device manufactured according to the concept of the present invention. For example, the standard cell layout described previously with reference to FIG. 6C can be used to fabricate a semiconductor device, and FIGS. 7A to 7C illustrate examples of such a semiconductor device.

In the following description of FIGS. 7A to 7C, the same numbers will be used to denote elements corresponding to the elements of the above-mentioned standard cell layout. However, such elements constituting a semiconductor device may be formed on a semiconductor substrate using a photolithography process, and therefore, they may not be the same as corresponding patterns constituting a standard cell layout. In some instances, the semiconductor device is provided in the form of a system-on-chip.

Referring to FIGS. 6C and FIGS. 7A to 7C, the second device isolation layer ST2 can be disposed on the substrate 100 to define the PMOSFET region PR and the NMOSFET region NR. The second device isolation layer ST2 may be formed in the top portion of the substrate 100. The substrate 100 may be a silicon substrate, a germanium substrate, or a silicon-on-insulator (SOI) substrate.

The PMOSFET region PR and the NMOSFET region NR may be spaced apart from each other in the first direction D1 parallel to the top surface of the substrate 100 by the second device isolation layer ST2 interposed therebetween. In some examples, each of the PMOSFET region PR and the NMOSFET region NR is a single (adjacent) region, but each of the PMOSFET region PR and the NMOSFET region NR may instead include a second device isolation layer ST2 and multiple zones spaced apart from each other.

A plurality of active patterns FN may be linearly extended in a second direction D2 intersecting the first direction D1 at the upper portions of the PMOSFET region PR and the NMOSFET region NR. The active pattern FN may be a part of the substrate 100 or a pattern protruding from the substrate 100. The active patterns FN may be spaced apart from each other along the first direction D1. The first device isolation layer ST1 may be extended on both sides of each of the active patterns FN in the second direction D2. In some examples, each of the active patterns FN has a fin-shaped portion at the uppermost portion thereof. As an example, the fin-shaped portion may be a portion of the active pattern FN that protrudes in an upward direction above the level of the first device isolation layer ST1.

The first device isolation layer ST1 and the second device isolation layer ST2 may be connected to each other in a substantially continuous manner, thereby forming a single insulating layer. In some examples, the second device isolation layer ST2 may have a thickness greater than that of the first device isolation layer ST1. In this case, the first device isolation layer ST1 may be formed by a process different from that of the second device isolation layer ST2. In some examples, the first device isolation layer ST1 can be formed at the same time using the same process as that of the second device isolation layer ST2, thereby having substantially the same thickness as the thickness of the second device isolation layer ST2. The first device isolation layer ST1 and the second device isolation layer ST2 may be formed in the upper portion of the substrate 100. The first device isolation layer ST1 and the second device isolation layer ST2 may be composed of, for example, silicon oxide layers.

The gate pattern GP may be disposed on the active pattern FN and extend across the active pattern FN in the first direction D1 and be parallel to each other. The gate patterns GP may be spaced apart from each other in the second direction D2. More specifically, each of the gate patterns GP It can extend across the PMOSFET region PR, the second device isolation layer ST2 and the NMOSFET region NR and parallel to the first direction D1.

The gate insulating pattern GI may be disposed under each of the gate patterns GP, and the gate spacer GS may be disposed on both sides of each of the gate patterns GP. In addition, a capping pattern CP may be provided to cover the top surface of each of the gate patterns GP. However, in some examples, the capping pattern CP may be removed from a portion of the top surface of the gate pattern GP connected to the gate contact CB. The first to fifth interlayer insulating layers 110 to 150 may be provided to cover the gate patterns GP.

The gate pattern GP may be formed of at least one material selected from the group consisting of doped semiconductors, metals, and conductive metal nitrides, or include those selected from the group consisting of doped semiconductors, metals, and conductive metal nitrides. At least one material in the group. The gate insulating pattern GI may include at least one of a silicon oxide layer, a silicon oxynitride layer, and a high-k dielectric layer having a higher dielectric constant than the silicon oxide layer. Each of the capping pattern CP and the gate spacer GS may include at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. Each of the first interlayer insulating layer 110 to the fifth interlayer insulating layer 150 may be a silicon oxide layer or a silicon oxynitride layer.

The source/drain regions SD may be disposed in portions of the active pattern FN located on both sides of each of the gate patterns GP. The source/drain region SD in the PMOSFET region PR may be a p-type impurity region, and the source/drain region SD in the NMOSFET region NR may be an n-type impurity region. The fin-shaped part located under the gate pattern GP and overlapped by the gate pattern GP may serve as the channel area AF of the transistor.

The source/drain region SD may be an epitaxial pattern formed by a selective epitaxial growth process. Therefore, the source/drain region SD may have a top surface located at a level higher than that of the fin-shaped portion. The source/drain region SD may include a semiconductor element different from the semiconductor element of the substrate 100. As an example, the source/drain region SD may be formed of a semiconductor material having a lattice constant different from (e.g., greater or less than) the substrate 100, or include the crystal having a lattice constant different from (e.g., greater or less than) the substrate 100. A semiconductor material with a lattice constant. Therefore, the source/drain region SD can apply compressive stress or tensile stress to the channel region AF.

The gate pattern GP and the active pattern FN can form a plurality of logic transistors. For example, it may correspond to the logical layout explained with reference to FIG. 6A.

The source/drain contact CA may be disposed between the gate patterns GP. The source/drain contacts CA may be arranged in the second direction D2 along the active pattern FN. As an example, the source/drain contacts CA may be respectively disposed between the gate patterns GP on the PMOSFET region PR and the NMOSFET region NR, and may be arranged in the first direction D1 (for example, see FIG. 7C). The source/drain contact CA can be directly coupled to and electrically connected to the source/drain region SD. The source/drain contact CA may be disposed in the first interlayer insulating layer 110. The gate contact CB may be disposed on at least one of the gate patterns GP.

The first lower contact window V41 and the second lower contact window V42 may be disposed on the first interlayer insulating layer 110 and in the second interlayer insulating layer 120. The first metal layer may be disposed on the second interlayer insulating layer 120 and in the third interlayer insulating layer 130. First metal The layer may include a first power line PL3 and a second power line PL4, and a first lower metal line M41 and a second lower metal line M42. The first power line PL3 and the second power line PL4 may correspond to the first power pattern PL1 and the second power pattern PL2 described with reference to FIG. 6C, and the first lower metal line M41 and the second lower metal line M42 may correspond to Refer to the first pin pattern M11 and the second pin pattern M12 described with reference to FIG. 6C.

As an example, the first lower metal line M41 may be electrically connected to one of the source/drain contacts CA through the first lower contact window V41. The second lower metal line M42 can be electrically connected to the gate contact CB through the second lower contact window V42.

The first power line PL3 and the second power line PL4 may be respectively disposed outside the PMOSFET region PR and the NMOSFET region NR and adjacent to the PMOSFET region PR and the NMOSFET region NR. The first power line PL3 may be connected to the source/drain contact CA through the lower contact window, so that a drain voltage (Vdd) (for example, a power supply voltage) is applied to the PMOSFET region PR. The second power line PL4 may be connected to the source/drain contact CA through the lower contact window, so that the source voltage (Vss) (for example, the ground voltage) is applied to the NMOSFET region NR.

The first upper contact window V51 and the second upper contact window V52 may be disposed on the third interlayer insulating layer 130 and in the fourth interlayer insulating layer 140. The second metal layer may be disposed on the fourth interlayer insulating layer 140 and in the fifth interlayer insulating layer 150. The second metal layer may include a first upper metal line M51 and a second upper metal line M52. The first upper metal line M51 and the second upper metal line M52 may correspond to the first interconnection pattern M21 and the second interconnection pattern M22 explained with reference to FIG. 6C.

As an example, the first upper metal line M51 can be connected through the first upper contact window V51 is electrically connected to the first lower metal wire M41. The second upper metal line M52 can be electrically connected to the second lower metal line M42 through the second upper contact window V52.

The first metal layer and the second metal layer can be formed using the method of designing and manufacturing a semiconductor device as described with reference to FIG. 2. For example, a high-level design process and a layout design process of a semiconductor integrated circuit can be implemented to prepare the standard cell layout described with reference to FIG. 6C. Subsequently, optical proximity correction can be performed to prepare a modified metal layout, and a photomask can be manufactured based on the modified metal layout.

Forming the first metal layer may include forming a photoresist pattern on the third interlayer insulating layer 130, the pattern of the photoresist pattern being defined by an interconnect layout. For example, a photoresist layer may be formed on the third interlayer insulating layer 130. Next, a photomask manufactured based on the interconnect layout can be used to perform an exposure process on the photoresist layer, and then a development process can be performed on the photoresist layer to form the photoresist pattern. In some examples, the photoresist pattern may be formed to have openings defining metal wire holes.

Next, the photoresist pattern may be used as an etching mask to etch the third interlayer insulating layer 130, thereby forming interconnection holes. The first power line PL3 and the second power line PL4, and the first lower metal line M41 and the second lower metal line M42 can be formed by filling the interconnect hole with a conductive material. The conductive material may be formed of or include a metal material (for example, copper).

The second metal layer may be formed by a method similar to the method of forming the first metal layer.

8A to 8C are some examples according to the concept of the present invention, illustrating a A plan view of the method of laying out standard cells and establishing wiring structures for them. In the following description of this example, similar or identical reference numbers may be used to identify the elements or steps previously described with reference to FIGS. 6A to 6C, so as to avoid repetitive descriptions.

3 and 8A, a layout design tool can be used to prepare the original standard cell layout (step S121). In more detail, an interconnection layout may be provided, and providing the interconnection layout may include laying out the first power pattern PL1 and the second power pattern PL2, laying out the first preliminary pin pattern PM11 and the second preliminary pin pattern PM12, And layout the first lower contact window pattern V11 and the second lower contact window pattern V12. Each of the first preliminary pin pattern PM11 and the second preliminary pin pattern PM12 may correspond to the first pin pattern M11 and the second pin pattern M12 described with reference to FIG. 4A in terms of its shape and arrangement. One is essentially the same.

The standard cell layout can be saved in the cell library described with reference to FIG. 2. Next, the repeated multiple standard cell layouts stored in the cell library can be set on the positioning (step S122).

Referring to FIG. 3 and FIG. 8B, a wiring step may be performed on the standard cell layout to connect the standard cell to the high-level interconnect layout (step S123). Providing the high-level interconnection layout may include arranging the first interconnection pattern M21 and the second interconnection pattern M22 and arranging the first upper contact pattern V21 and the second upper contact pattern V22.

Each of the first upper contact window pattern V21 and the second upper contact window pattern V22 may be placed on the first preliminary pin pattern PM11 and the second preliminary pin pattern PM12 and the first interconnection pattern M21 and the second On a corresponding one of the overlapping regions of the interconnection pattern M22. For example, the first upper contact window pattern V21 can be placed It is placed on the first region RG1 of the first preliminary pin pattern PM11. The area of the first area RG1 on which the first upper contact window pattern V21 is placed may be referred to as a first hit area. The first lower contact window pattern V11 may be placed under the first region RG1. Another area of the first area RG1 on which the first lower contact window pattern V11 is placed may be referred to as a second hit area. The first preliminary pin pattern PM11 may be placed on the second region RG2 that does not overlap the first region RG1.

3 and 8C, the first pin pattern M11 and the second pin pattern M12 can be placed in the interconnect layout based on the hit information that can be obtained when the wiring step is completed (step S124). In more detail, the first preliminary pin pattern PM11 may be processed to retain the first area RG1 including the first hit area and the second hit area, but remove the second area RG2. The reserved portion of the first preliminary pin pattern PM11 (for example, the first region RG1) may serve as the first pin pattern M11. The second preliminary pin pattern M12 may be formed by processing the second preliminary pin pattern PM12 in the same manner as the first preliminary pin pattern PM11.

9A, 9C, and 9D are plan views illustrating a method of laying out standard cells and establishing a wiring structure for them according to some examples of the concept of the present invention. FIG. 9B is a plan view illustrating some examples of standard cell layouts having mutually different interconnection layouts. In the following description of this example, similar or identical reference numbers may be used to identify the elements or steps previously described with reference to FIGS. 6A to 6C, so as to avoid repetitive descriptions.

3 and 9A, (in step S121) a layout design tool can be used to provide the original standard cell layout. In more detail, interconnection layout can be provided, and The interconnection layout may include laying out the first power pattern PL1 and the second power pattern PL2, laying out the first preliminary pin pattern PM11 and the second preliminary pin pattern PM12, and laying out the first lower contact pattern V11 and the second 2. The lower contact window pattern V12. Each of the first preliminary pin pattern PM11 and the second preliminary pin pattern PM12 may correspond to the first pin pattern M11 and the second pin pattern M12 described with reference to FIG. 4A in terms of its shape and arrangement. One is essentially the same.

9B, the original standard cell layout shown in FIG. 9A can be modified to generate a first standard cell layout A, a second standard cell layout B, and a third standard cell layout that have mutually different interconnection layouts. Cell layout C and the fourth standard cell layout D. For example, each of the standard cell layouts A, B, C, and D shown in FIG. 9B may have the same logical layout as the original standard cell layout shown in FIG. 9A, but may have The original standard cell layout shown in 9A is a different interconnection layout.

For example, each of the first standard cell layout A, the second standard cell layout B, the third standard cell layout C, and the fourth standard cell layout D may include the first pin pattern M11 and the Two-pin pattern M12. In this example, the first pin pattern M11 and the second pin pattern M12 are different from each other in terms of their sizes; that is, the number of pin regions PI provided in the first pin pattern M11 is different from the number of pin regions PI provided in the second pin pattern M11. The number of pin areas PI in the foot pattern M12 may be different. In addition, the first pin pattern M11 and the second pin pattern M12 may be different from each other in their relative positions.

It should be noted that the first standard cell layout A, the second standard cell layout B, the third standard cell layout C, and the fourth standard cell layout D are only examples of possible modifications of the standard cell layout, that is, Based on the first preliminary pin pattern set in PM11 The standard cell layout is modified to provide a different set of standard layouts by setting the number of pin areas PI and the number of pin areas PI set in the second preliminary pin pattern PM12. For example, in a case where each of the first preliminary pin pattern PM11 and the second preliminary pin pattern PM12 has five pin areas PI, the standard cell layout can be modified to generate a Group up to 5 X 5 (ie, 25) standard cell layouts that are different from each other.

The original standard cell layout and the first standard cell layout A, the second standard cell layout B, the third standard cell layout C, and the fourth standard cell layout D provided by the above process can be saved in the reference to FIG. 2 In the illustrated cell library. Subsequently, the repeated multiple original standard cell layouts stored in the cell library can be set to the positioning (step S122).

Referring to FIG. 3 and FIG. 9C, (in step S123), a wiring step may be performed on the original standard cell layout to connect the original standard cell layout to the high-level interconnect layout. Providing the high-level interconnection layout may include arranging the first interconnection pattern M21 and the second interconnection pattern M22 and arranging the first upper contact pattern V21 and the second upper contact pattern V22.

Each of the first upper contact window pattern V21 and the second upper contact window pattern V22 may be placed on the first preliminary pin pattern PM11 and the second preliminary pin pattern PM12 and the first interconnection pattern M21 and the second On a corresponding one of the overlapping regions of the interconnection pattern M22. The positions where the first upper contact window pattern V21 and the second upper contact window pattern V22 will be disposed may constitute part of the hit information.

For example, when viewing in the first direction D1, The first upper contact pattern V21 is provided in the third pin area of the foot pattern PM11, and the second upper contact pattern V22 may be provided in the second pin area of the second preliminary pin pattern PM12.

Referring to FIGS. 3 and 9D, the first pin pattern M11 and the second pin pattern M12 may be placed in the interconnect layout based on the hit information (step S124). In more detail, based on the hit information, any one of the first standard cell layout A, the second standard cell layout B, the third standard cell layout C, and the fourth standard cell layout D can be substituted for any The original standard cell layout.

For example, the interconnection layout including the three pin areas of the first pin pattern M11 and the two pin areas of the second pin pattern M12 may be suitable to meet the technical requirements imposed by the hit information. In this case, referring to FIG. 9B, the second standard cell layout B, the third standard cell layout C, and the fourth standard cell layout D are suitable for satisfying this requirement. However, among the second standard cell layout B, the third standard cell layout C, and the fourth standard cell layout D, the second standard cell layout B can be the most expected because it has the smallest The pin patterns M11 and M12 and the devices made based on this layout will be in each device made based on the second standard cell layout B, the third standard cell layout C, and the fourth standard cell layout D Shows the lowest parasitic capacitance. Therefore, the original standard cell layout can be replaced by the second standard cell layout B.

10A to 10C are plan views illustrating a method of laying out standard cells and establishing a wiring structure for them according to some examples of the concept of the present invention. In the following description of this example, similar or identical reference numbers may be used to identify the elements or steps previously described with reference to FIGS. 6A to 6C, so as to avoid repetitive descriptions.

3 and 10A, a layout design tool can be used to provide the original standard cell layout (step S121). Providing the standard cell layout may include providing a first interconnection layout and a second interconnection layout. In some examples, the first interconnect layout may correspond to the first metal layer to be formed on the semiconductor substrate, and the second interconnect layout may correspond to the second metal layer to be formed on the semiconductor substrate. In other words, unlike the example shown in FIG. 6A, the standard cell layout may include a plurality of interconnection layouts, and the interconnection layout may be changed depending on the type of circuit constituting the standard cell layout.

Providing the first interconnection layout may include arranging the first power pattern PL1 and the second power pattern PL2, and arranging the first lower interconnection line pattern M61, the second lower interconnection line pattern M62, and the third lower interconnection line Pattern M63. Although not shown in the figure, the first lower interconnection pattern M61, the second lower interconnection pattern M62, and the third lower interconnection pattern M63 may be connected to the logic layout through the lower contact pattern.

Preparing the second interconnection layout may include laying out a first preliminary pin pattern PM21, a second preliminary pin pattern PM22, and a third preliminary pin pattern PM23, and laying out a first contact pattern V61 and a second contact pattern V62 And the third contact window pattern V63. Each of the first contact window pattern V61, the second contact window pattern V62, and the third contact window pattern V63 may be disposed in the first lower interconnection line pattern M61, the second lower interconnection line pattern M62, and the third The lower interconnection line pattern M63 and the corresponding pair of the first preliminary pin pattern PM21, the second preliminary pin pattern PM22, and the third preliminary pin pattern PM23 to connect the corresponding pair to each other.

The standard cell layout can be saved in the cell library described with reference to FIG. 2. Next, the repeated multiple standard cell layouts stored in the cell library can be set on the positioning (step S122).

Referring to FIG. 3 and FIG. 10B, a wiring step can be performed on the standard cell layout to connect the standard cell to the high-level interconnect layout (step S123). Providing the high-level interconnection layout may include arranging the first upper interconnection line pattern M31, the second upper interconnection line pattern M32, and the third upper interconnection line pattern M33, and the layout of the first upper contact window pattern V31 and the second upper part. The contact pattern V32 and the third upper contact pattern V33. Each of the first upper contact window pattern V31, the second upper contact window pattern V32, and the third upper contact window pattern V33 may be placed in the first preliminary pin pattern PM21, the second preliminary pin pattern PM22, and the second preliminary pin pattern PM21, respectively. The three preliminary pin patterns PM23 are on a corresponding one of the overlapping regions of the first upper interconnection line pattern M31, the second upper interconnection line pattern M32, and the third upper interconnection line pattern M33. When the wiring step is completed, hit information can be obtained.

3 and 10C, the first pin pattern M71, the second pin pattern M72, and the third pin pattern M73 may be provided or generated in the second interconnect layout based on the hit information (step S124). The formation of the first pin pattern M71, the second pin pattern M72, and the third pin pattern M73 may be performed using one of the methods previously described with reference to FIGS. 6C, 8C, and 9D. As a result, compared to the size of the corresponding one of the first preliminary pin pattern PM21, the second preliminary pin pattern PM22, and the third preliminary pin pattern PM23, the first pin pattern M71 and the second pin pattern PM23 The size of each of the foot pattern M72 and the third pin pattern M73 may be reduced.

With reference to Figure 6A to Figure 6C and Figure 10A to Figure 10C shown and explained The examples are different. The pin patterns of the standard cell layout are not limited to being arranged in the first metal layer and/or the second metal layer (on the substrate). Instead, as described above, the pin pattern may be laid out in a higher-order metal layer (for example, a third metal layer). In addition, the pin patterns can be provided in different metal layers; for example, multiple pin patterns can be laid out in each of the first metal layer and the second metal layer.

11A and 11B are plan views illustrating a method of laying out standard cells and establishing a wiring structure for them according to some examples of the concept of the present invention. In the following description of this example, similar or identical reference numbers may be used to identify the elements or steps previously described with reference to FIGS. 6A to 6C, so as to avoid repetitive descriptions.

Referring to FIG. 3 and FIG. 11A, the standard cell layout described with reference to FIG. 6A, FIG. 8A or FIG. 9A can be provided (step S121). The standard cell layout can be saved in the cell library described with reference to FIG. 2. Subsequently, the repeated multiple standard cell layouts stored in the cell library can be set in alignment in the second direction D2 and parallel to each other in positioning (step S122). A plurality of the same standard cell layout can be set on the positioning to form a first standard cell layout STD1 and a second standard cell layout STD2. The first standard cell layout STD1 and the second standard cell layout STD2 respectively include The same logic layout of the same circuit. As an example, the first standard cell layout STD1 and the second standard cell layout STD2 may represent inverters. The first standard cell layout STD1 may have a first interconnection layout including a first preliminary pin pattern PM11 and a second preliminary pin pattern PM12, and the second standard cell layout STD2 may have a third preliminary pin pattern PM13 And the second interconnect layout of the fourth preliminary pin pattern PM14. The first preliminary pin pattern PM11 and the second preliminary pin pattern PM12 and the third preliminary pin pattern PM13 and the fourth preliminary pin pattern PM14 may be the same as each other in size and position. Although not shown in the figure, other standard cell layouts may be additionally sandwiched between the first standard cell layout STD1 and the second standard cell layout STD2.

3 and 11B, the first standard cell layout STD1 and the second standard cell layout STD2 can be routed to connect the first standard cell layout STD1 and the second standard cell layout STD2 to the high-level interconnect Continuous layout (step S123). Although the first standard cell layout STD1 and the second standard cell layout STD2 are the same, the first standard cell layout STD1 and the second standard cell layout STD2 can be respectively connected to different standard cells in the wiring step, And therefore, the first standard cell layout STD1 and the second standard cell layout STD2 may have different hit information related to them. As an example, the first standard cell layout STD1 may be connected to the first interconnection pattern M21 and the second interconnection pattern M22 constituting the high-level interconnection layout. The second standard cell layout STD2 may be connected to the third interconnection pattern M23 and the fourth interconnection pattern M24 constituting the high-level interconnection layout.

Based on the hit information, (in step S124) the first pin pattern M11 and the second pin pattern M12 can be provided or generated in the first interconnect layout, and the second pin pattern M12 can be provided or generated in the second interconnect layout. The three-pin pattern M13 and the fourth pin pattern M14. One of the methods previously described with reference to FIGS. 6C, 8C, and 9D may be used to form the first pin pattern M11 and the second pin pattern M12 and/or the third pin pattern M13 and the fourth pin pattern M14. Therefore, the first pin pattern M11, the second pin pattern M12, and the third pin pattern can be provided in the same standard cell layouts (for example, the first standard cell layout STD1 and the second standard cell layout STD2) The sizes and arrangements of M13 and the fourth pin pattern M14, the first pin pattern M11 and the second pin pattern M12, and the third pin pattern M13 and the fourth pin pattern M14 are different from each other.

On the contrary, if the pin pattern is newly generated after the steps of laying out standard cells and establishing a wiring structure (for example, see FIG. 4B or FIG. 5B), the same standard cell layout can have the same The pin pattern (for example, having the same size and the same arrangement) regardless of whether there is a difference in the wiring step. In contrast, in the layout design method according to some examples of the concept of the present invention, although the standard cell layout is the same, the standard cell layouts can be introduced to be different in size and relative position. Foot pattern. This can enable a semiconductor device with optimized characteristics. In addition, in FIG. 11B, in addition to the first upper contact window pattern V21 and the second upper contact window pattern V22, a third upper contact window pattern V23 and a fourth upper contact window pattern V24 are further included.

According to some examples of the inventive concept, a method of designing the layout of a semiconductor device may include laying out pin patterns in an interconnection layout of a standard cell layout based on hit information obtained after a wiring step. Therefore, the degree of freedom in wiring can be maximized and a semiconductor device with high operating speed characteristics and low power consumption characteristics can be achieved.

Finally, although examples of the concept of the present invention have been specifically shown and explained, those with ordinary knowledge in the art should understand that changes in form and details can be made without departing from the scope of the attached patent application. The spirit and scope of the defined concept of the invention.

S121, S122, S123, S124: steps

Claims (25)

A method for generating a layout of a semiconductor device includes: providing a standard cell layout, and providing the standard cell layout includes creating a preliminary guide for an interconnection layout of the standard cell layout related to a lower metal layer of the semiconductor device Foot pattern; a wiring step is performed to generate a high-level interconnect layout in which the preliminary pin pattern is connected to a high-level interconnect pattern, the high-level interconnect layout representing the semiconductor device disposed on the lower metal layer The upper level metal interconnection; and based on the hit information obtained when the wiring step is completed, the preliminary pin pattern is converted into a later lead in the area of the interconnect layout of the standard cell layout A foot pattern, where the post-lead pattern represents a lower level metal interconnection of the lower metal layer of the semiconductor device, wherein the post-lead pattern is smaller than the preliminary pin pattern. The method for generating the layout of a semiconductor device as described in the first item of the scope of patent application, wherein the preliminary pin pattern is converted into the late pin pattern, and the late pin pattern is placed on the previous preliminary pin pattern. In the occupied area, the late-stage pin pattern and the preliminary pin pattern occupy an overlapping area in the method of generating the layout of the semiconductor device. The method for generating the layout of a semiconductor device as described in the first item of the scope of patent application, wherein providing the standard cell layout includes: providing a logic layout including logic transistors; and laying out a lower contact window pattern to align the logic layout Connect to the initial reference Foot pattern. The method for generating the layout of a semiconductor device as described in the scope of patent application 1, wherein creating the preliminary pin pattern includes laying out a ghost pattern containing pin information of the wiring step, and converting the preliminary lead pattern The foot pattern being the late lead pattern includes converting one of the ghost patterns hitting the high-level interconnect layout into the late lead pattern. The method for generating the layout of a semiconductor device as described in claim 4, wherein at least one of the ghost patterns has a minimum feature size determined by technical limitation factors in the photolithography process. The method for generating the layout of a semiconductor device as described in claim 1, wherein converting the preliminary pin pattern into the later pin pattern includes removing the second area of the preliminary pin pattern while retaining The first area of the preliminary pin pattern, and the first area includes a first hit area to be connected to the high-level interconnect layout. The method for generating the layout of a semiconductor device as described in the scope of patent application, wherein the first area further includes a second hit area to be connected to the logic layout of the standard cell layout. The method for generating the layout of a semiconductor device as described in the first item of the scope of patent application further includes providing a plurality of cell layouts, the plurality of cell layouts are respectively based on the standard cell layout, wherein the cell layout has Mutually different interconnection layouts, and Converting the preliminary pin pattern into the later pin pattern includes replacing the standard cell layout with one of the cell layouts based on the hit information. The method of generating the layout of a semiconductor device as described in the scope of patent application, wherein the interconnection layout of the cell layout includes corresponding pin patterns that are different from each other in size. The method for generating the layout of a semiconductor device as described in the first item of the scope of patent application further includes: prior to the wiring step, laying out a plurality of the standard cell layouts. The method for generating the layout of a semiconductor device as described in the scope of patent application 10, wherein each of the standard cell layouts includes the same logic layout as each of the rest of the standard cell layouts And generating the late pin patterns includes generating late pin patterns different in size from each other in the standard cell layout, respectively. A method for designing the layout of a semiconductor device includes: providing a first standard cell layout and a second standard cell layout in a cell library, and providing the first standard cell layout and the second standard cell layout includes A first preliminary pin pattern and a second preliminary pin pattern are respectively laid out on the first standard cell layout and the second standard cell layout, and each of the first preliminary pin pattern and the second Two preliminary pin patterns are associated with the lower metal layer of the semiconductor device; the first standard cell layout and the second standard cell layout are laid out; the wiring step is performed to connect the first preliminary pin The pattern and the second preliminary pin pattern are connected to a high-level interconnect layout, each of the high-level interconnect layouts represents a configuration The upper level metal interconnection of the semiconductor device on the lower metal layer; and based on the hit information obtained after the wiring step, the first preliminary pin pattern and the second The preliminary pin pattern is converted into a first pin pattern and a second pin pattern, and the first pin pattern and the second pin pattern represent the lower level metal interconnection of the lower metal layer of the semiconductor device. Connection, wherein the first preliminary pin pattern and the second preliminary pin pattern are the same in size and arrangement, and the first pin pattern and the second pin pattern are mutually the same in size and arrangement. different. The method for designing the layout of a semiconductor device as described in claim 12, wherein each of the first standard cell layout and the second standard cell layout includes the same logic layout with the same circuit. The method for designing the layout of a semiconductor device as described in claim 12, wherein each of the first pin pattern and the second pin pattern is smaller in size than the first preliminary introduction Each of the foot pattern and the second preliminary pin pattern. The method for designing the layout of a semiconductor device as described in claim 12, wherein the hit information on the first standard cell layout is different from the hit information on the second standard cell layout. The method for designing the layout of a semiconductor device as described in claim 12, wherein the first preliminary pin pattern and the second preliminary pin pattern are laid out Each of the cases includes laying out a ghost pattern containing pin information of the wiring step, and converting the first preliminary pin pattern and the second preliminary pin pattern to the first pin Each of the pattern and the second pin pattern includes when the first ghost pattern and the second ghost pattern in the ghost pattern hit the high-level interconnect layout, the ghost pattern The first ghost pattern and the second ghost pattern in are converted into the first pin pattern and the second pin pattern. The method for designing the layout of a semiconductor device according to claim 12, wherein the first preliminary pin pattern and the second preliminary pin pattern are converted into the first pin pattern and the second Each of the pin patterns includes: retaining the first area of each of the first preliminary pin pattern and the second preliminary pin pattern, and removing the first preliminary pin pattern and Each of the second preliminary pin patterns has a second area other than the first area, and the first area includes a hit area to be connected to the high-level interconnect layout. The method for designing the layout of a semiconductor device as described in claim 12, further includes: providing a plurality of first cell layouts, each of the plurality of first cell layouts corresponding to the first Standard cell layout; and providing a plurality of second cell layouts, each of the plurality of second cell layouts corresponds to the second standard cell layout, wherein the plurality of first cell layouts Respectively include different interconnection layouts, and the plurality of second cell layouts respectively include different interconnection layouts, Converting the first preliminary pin pattern to the first pin pattern includes replacing the first standard cell layout with one of the first cell layouts based on the hit information, and converting all The second preliminary pin pattern is that the second pin pattern includes replacing the second standard cell layout with one of the second cell layouts based on the hit information. A method of manufacturing a semiconductor device includes: a process of generating a device layout of the semiconductor device, wherein the process includes: obtaining a standard cell layout and an interconnection layout, the standard cell layout including the active type of the semiconductor device The layout of the device and/or area, the interconnection layout includes a preliminary pin pattern, the preliminary pin pattern defines at least the semiconductor device that is to be electrically connected to the active device and/or area In one of the areas of the lower contact window, the wiring step is performed, including covering the high-level interconnect pattern and the upper contact window pattern on the standard cell layout, wherein the high-level interconnect pattern and the preliminary pin pattern And the high-level interconnection pattern represents the high-level interconnection of the semiconductor device, and the upper contact window pattern is placed at the intersection of the high-level interconnection pattern and the preliminary pin pattern and represents the high-level interconnection of the semiconductor device The position of the upper contact window, based on the wiring step, generates hit information indicating the position of the upper contact window, and uses the hit information to generate a post-pin pattern, the post-pin pattern representing the semiconductor The device contains both the lower contact window and the upper contact window And manufacturing the semiconductor device using the device layout, wherein the manufacturing of the semiconductor device includes: forming active elements and/or regions laid out based on the standard cell layout at the upper portion of the substrate, in the Forming a multi-layer metal line superimposed on each other on the substrate and forming a contact window connecting the multi-layer metal line to the active device, wherein the multi-layer metal line includes a lower level metal layer and an upper level metal layer, The lower-level metal layer includes a lower-level metal interconnection corresponding to the later pin pattern, and the upper-level metal layer includes an upper-level metal interconnection corresponding to the high-level interconnection, and The contact window includes a first contact window and a second contact window, the first contact window corresponding to the lower contact window and sandwiched between at least one of the lower level metal interconnection and the active element And electrically connect the lower level metal interconnection to the at least one of the active devices, and the second contact window corresponds to the upper contact window and is sandwiched between the lower layer A level metal interconnection and the upper level metal interconnection are electrically connected to the lower level metal interconnection and the upper level metal interconnection. According to the method of manufacturing a semiconductor device according to item 19 of the scope of the patent application, the generating of the late-stage pin pattern in the process of generating the device layout includes: generating the late-stage pin pattern as the area determined by the preliminary The area represented by the pin pattern is a small area. The method for fabricating a semiconductor device according to the 19th patent application, wherein the layout of the preliminary pin pattern in the process of generating the device layout includes the layout of ghosts containing pin information of the wiring step Pattern, and generating the post-lead pattern includes converting the ghost pattern into the post-lead pattern. The method of manufacturing a semiconductor device according to the 19th patent application, wherein the generating of the post-pin pattern in the process of generating the device layout includes: removing the preliminary pin from the device layout While the second area of the pattern remains, the first area of the preliminary pin pattern in the device layout is retained, and the first area includes an area overlapped by the upper contact window pattern. The method for fabricating a semiconductor device as described in claim 22, wherein the first region further includes a region overlapping the lower contact pattern. The method for fabricating a semiconductor device as described in claim 19, wherein the process of generating the device layout of the semiconductor device further includes: accessing a database of a plurality of cell layouts, and the plurality of cell layouts Each of the cell layouts is based on the standard cell layout, and wherein each of the plurality of cell layouts includes a pin pattern that is different from each of the rest of the cell layout Size of the pin pattern, and generating the late pin pattern includes replacing the preliminary pin of the standard cell layout with the pin pattern of one of the multiple cell layouts in the database pattern. The method for fabricating a semiconductor device according to the 19th patent application, wherein the process of generating the device layout of the semiconductor device includes: laying out two of the standard cell layout side by side, and the wiring step Is implemented for each of the standard cell layouts, so that the corresponding ones of the high-level interconnect patterns and the corresponding ones of the upper contact window patterns are overlaid on each of the standard cell layouts And generate a corresponding late pin pattern for each of the standard cell layouts. Each of the late pin patterns represents that the semiconductor device contains a corresponding lower contact window and a corresponding Areas of both the upper contact window, and the late pin patterns are different from each other in their sizes.

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