CN111710354B - CMD (cross-talk) delay compensation method, device, equipment and medium for DDR3 - Google Patents
CMD (cross-talk) delay compensation method, device, equipment and medium for DDR3 Download PDFInfo
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- CN111710354B CN111710354B CN202010554326.4A CN202010554326A CN111710354B CN 111710354 B CN111710354 B CN 111710354B CN 202010554326 A CN202010554326 A CN 202010554326A CN 111710354 B CN111710354 B CN 111710354B
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Abstract
The application discloses a CMD delay compensation method of DDR3, which comprises the following steps: sending CMD to DDR3, and obtaining feedback information of DDR 3; and configuring the deskew value of the DDRPHY by utilizing the feedback information so as to perform delay compensation on the CMD. Obviously, compared with the prior art, because the method performs delay compensation on the CMD of the DDRPHY by using feedback information in the actual operating environment where the DDR3 is located, not only can delay compensation errors caused by simulating the DDR3 operating environment be avoided, but also influence and interference caused by human factors on the result of delay compensation of the CMD can be avoided, so that the accuracy of delay compensation on the CMD of the DDR3 can be significantly improved. Accordingly, the CMD delay compensation device, apparatus and medium for DDR3 provided by the present application also have the above-mentioned advantages.
Description
Technical Field
The invention relates to the technical field of power electronics, in particular to a CMD (cross-talk) delay compensation method, a device, equipment and a medium for DDR 3.
Background
When a Printed Circuit Board (PCB) is wired due to resource limitation, the length of each Command signal of the DDR3(Double Data Rate 3) is deviated, so that when a CMD (Command) is sent to the DDR3 by a DDR PHY (Double Data Rate Physical Interface), an effective Command window formed by combining each Command signal is narrowed due to the delay of each Command signal of the DDR3, in this case, the DDR3 cannot receive a correct CMD, and thus the DDR3 is caused to be abnormal. At present, the technical problem is solved by using SI simulation or oscilloscope to compensate the CMD delay of DDR 3.
When the delay compensation is performed on the CMD of the DDR3 by using SI simulation, firstly, the time difference between the transmission of each signal command to the DDR3 and the transmission of CK to the DDR3 needs to be calculated, and then, the time difference is compensated by using the Pre-bit-skew register, but since the method cannot truly simulate the actual operating environment of the DDR3, the delay compensation time of the CMD has a large deviation; when the oscilloscope is used to perform delay compensation on the CMD of the DDR3, the oscilloscope is first used to measure the time required by each signal command to reach the DDR3 during transmission to calculate the delay time of the CMD, and then the CMD is manually compensated according to the delay time of the CMD.
Therefore, how to improve the accuracy of delay compensation for the CMD of the DDR3 is a technical problem that needs to be solved by those skilled in the art.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a CMD delay compensation method, apparatus, device and medium for DDR3, so as to improve the accuracy of the CMD delay compensation for DDR 3. The specific scheme is as follows:
a CMD delay compensation method of DDR3 is applied to DDRPHY and comprises the following steps:
sending CMD to DDR3, and acquiring feedback information of DDR 3;
and configuring the deskew value of the DDRPHY by using the feedback information so as to perform delay compensation on the CMD.
Preferably, the configuring the deskew value of the DDRPHY using the feedback information includes:
and configuring the deskew value of the DDRPHY by utilizing the feedback information based on a state machine theory.
Preferably, the sending CMD to DDR3 and acquiring feedback information of DDR3 includes:
sending a first read command to the DDR3, and judging whether the DDR3 can feed back 1 period of DQS/DQSB in CL;
if yes, setting the deskew value of the CS # or CAS # in the DDRPHY as a first target value, and sending a second read command to the DDR 3; wherein the first target value is any one positive integer from 0 to 31;
judging whether the DDR3 can feed back 1 period of DQS/DQSB in the CL;
if so, marking the current value of the first target value to obtain a first target mark value, and acquiring the first target mark value.
Preferably, after the step of determining whether the DDR3 can feed back 1 cycle of DQS/DQSB in CL, the method further includes:
if not, the read rate of sending the first read command to the DDR3 is reduced to enable the DDR3 to feed back 1 cycle of DQS/DQSB within the CL.
Preferably, the configuring, by using the feedback information, the deskew value of the DDRPHY to perform delay compensation on the CMD includes:
and storing the first target mark value into a first preset storage area, and setting a deskew value of the CS # or the CAS # according to the maximum value and the minimum value stored in the first preset storage area so as to perform delay compensation on the CMD.
Preferably, the step of setting the deskew value of the CS # or the CAS # according to the maximum value and the minimum value stored in the first preset storage area to perform the delay compensation on the CMD includes:
and setting a middle value between the maximum value and the minimum value stored in the first preset storage area as a deskew value of the CS # or the CAS # to perform delay compensation on the CMD.
Preferably, the process of sending CMD to the DDR3 and acquiring feedback information of the DDR3 includes:
sending a first MRS command to the DDR3 to configure MR [1:0] as 2' b 00;
sending a third read command to the DDR3, and judging whether the DDR3 can feed back DQS/DQSB of 4 cycles in CL;
if so, sending a second MRS command to the DDR3 to configure MR [1:0] as 2' b 10;
sending a fourth read command to the DDR3, and determining whether the DDR3 can feed back 2 cycles of DQS/DQSB within the CL;
if yes, setting the deskew value of RAS # or WE # in the DDRPHY as a second target value; wherein the second target value is any one positive integer from 0 to 31;
sending a third MRS command to the DDR3 to configure MR [1:0] as 2' b 00;
sending a fifth read command to the DDR3, and determining whether the DDR3 can feed back DQS/DQSB of 4 cycles in the CL;
if so, marking the current value of the second target value to obtain a second target mark value, and acquiring the second target mark value;
correspondingly, the configuring the deskew value of the DDR3 with the feedback information to perform delay compensation on the CMD includes:
and storing the second target mark value into a second preset storage area, and setting a deskew value of the RAS # or the WE # according to the minimum value and the maximum value stored in the second preset storage area so as to perform delay compensation on the CMD.
Correspondingly, the invention also discloses a CMD delay compensation device of DDR3, which is applied to DDRPHY and comprises the following components:
the information feedback module is used for sending CMD to DDR3 and acquiring feedback information of DDR 3;
and the delay compensation module is used for configuring the deskew value of the DDRPHY by utilizing the feedback information so as to perform delay compensation on the CMD.
Correspondingly, the invention also discloses a CMD delay compensation device of DDR3, comprising:
a memory for storing a computer program;
a processor for implementing the steps of the CMD delay compensation method of DDR3 as disclosed above when executing the computer program.
Accordingly, the present invention also discloses a computer readable storage medium, on which a computer program is stored, which when executed by a processor implements the steps of a CMD delay compensation method for DDR3 as disclosed above.
It can be seen that, in the present invention, CMD is sent to DDR3, and feedback information fed back by DDR3 is obtained, and then the deskew value of DDRPHY is configured by using the feedback information fed back by DDR3, so as to perform delay compensation on CMD. Obviously, compared with the prior art, because the method performs delay compensation on the CMD of the DDR3 by using feedback information in the actual operating environment where the DDR3 is located, not only can delay compensation errors caused by simulating the operating environment of the DDR3 be avoided, but also influence and interference caused by human factors on the result of the delay compensation of the CMD can be avoided, and thus, the accuracy of delay compensation on the CMD of the DDR3 can be significantly improved. Correspondingly, the CMD delay compensation device, the equipment and the medium of the DDR3, which are provided by the invention, also have the beneficial effects.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a flowchart illustrating a CMD delay compensation method for DDR3 according to an embodiment of the present invention;
FIG. 2 is a diagram illustrating an actual timing diagram of CMD;
fig. 3 is a circuit diagram for delay compensation of the CMD of the DDR3 according to the embodiment of the present invention;
fig. 4 is a structural diagram of a CMD delay compensation apparatus for DDR3 according to an embodiment of the present invention;
fig. 5 is a structural diagram of a CMD delay compensation device of DDR3 according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a flowchart of a CMD delay compensation method for DDR3 according to an embodiment of the present invention, where the method includes:
step S11: sending CMD to DDR3, and acquiring feedback information of DDR 3;
step S12: and configuring the deskew value of the DDRPHY by using the feedback information to perform delay compensation on the CMD.
In the embodiment, a CMD delay compensation method of DDR3 is provided, by which the accuracy in performing delay compensation on the CMD of DDR3 can be significantly improved. It should be noted that the CMD delay compensation method for DDR3 provided in this embodiment is described with DDRPHY as an execution main body.
Referring to FIG. 2, FIG. 2 is a timing diagram of CMD. As shown in fig. 2, command signals issued by DDRPHY are all aligned in the center, so the command effective window is the largest, but with the change of ambient temperature, the influence of crosstalk and the interference of CK time jitter, delay inconsistency between the command signals and CK occurs, so that the effective command window reaching DDR3 is severely compressed, which may cause a command recognition error in DDR3 and thus cause system instability of DDR 3.
In this embodiment, in order to solve the above technical problem, CMD is first transmitted to the DDR3 using DDRPHY, and feedback information of the DDR3 is acquired. It can be understood that, because the feedback information of the DDR3 includes the delay information from the CMD to the DDR3, and the DDRPHY includes the per-bit-deskew register capable of configuring the delay of the command signal, the deskew value of the per-bit-deskew register in the DDRPHY can be configured by using the feedback information fed back by the DDR3, so that the clock received by the DDR3 can be aligned with the center of the command signal, and thus the effective command window received by the DDR3 can be maximized, and the purpose of performing delay compensation on the CMD can be achieved.
Obviously, the method is to utilize the feedback information in the actual operating environment of the DDR3 to perform delay compensation on the CMD of the DDR3, so that not only can delay compensation errors caused by simulating the operating environment of the DDR3 be avoided, but also influences and interferences caused by human factors on the CMD delay compensation result can be avoided, and thus, the accuracy of delay compensation on the CMD of the DDR3 can be remarkably improved.
In addition, because the method directly utilizes the feedback information of the DDR3 in the real operating environment to perform delay compensation on the CMD, the method can also improve the convenience of performing delay compensation on the CMD of the DDR3, and even if a PCB where the DDR3 is located is replaced, the configuration process of the deskew value of the DDR3 can be quickly completed in the DDR3 initialization stage, so that the method can also facilitate the field debugging of a worker on the DDR 3.
It can be seen that, in this embodiment, the CMD is sent to the DDR3, the feedback information fed back by the DDR3 is obtained, and then the skew value of the DDRPHY is configured by using the feedback information fed back by the DDR3 to perform delay compensation on the CMD. Obviously, compared with the prior art, because the method performs delay compensation on the CMD of the DDR3 by using feedback information in the actual operating environment where the DDR3 is located, not only can delay compensation errors caused by simulating the operating environment of the DDR3 be avoided, but also influence and interference caused by human factors on the result of the delay compensation of the CMD can be avoided, and thus, the accuracy of delay compensation on the CMD of the DDR3 can be significantly improved.
Based on the above embodiments, this embodiment further describes and optimizes the technical solution, and as a preferred implementation, the above steps: the process of configuring deskew value of DDRPHY by using feedback information comprises the following steps:
and configuring the deskew value of the DDRPHY by utilizing the feedback information based on the state machine theory.
Specifically, in this embodiment, the deskew value of the DDRPHY is configured based on a State Machine (FSM) theory and simultaneously in combination with a feedback signal, and because the State Machine is composed of a State Machine register and a combinational logic circuit, and can transition according to a control signal in a preset State, compared with configuring the deskew value of the DDRPHY by using an edit code, the deskew value of the DDRPHY is configured by using State transition, which not only can reduce a programming pressure of a worker, but also can relatively improve a configuration efficiency when configuring the deskew value of the DDRPHY.
Referring to fig. 3, fig. 3 is a circuit diagram for performing delay compensation on a CMD of a DDR3 according to an embodiment of the present invention. As shown in fig. 3, a state machine module and a DQS _ gate module are arranged in the DDRPHY, wherein the DQS _ gate module is configured to receive feedback information fed back by the DDR3 and send the feedback information to the state machine module, and the state machine module is configured to configure deskew values of deskew registers corresponding to CAS #, RAS #, WE # and CS # based on a state mechanism theory.
Based on the above embodiment, this embodiment further describes and optimizes the technical solution, and as a preferred implementation, the above steps: the process of sending CMD to the DDR3 and acquiring feedback information of the DDR3 includes:
sending a first read command to DDR3, and judging whether DDR3 can feed back 1 cycle of DQS/DQSB in CL;
if yes, the deskew value of CS # or CAS # in the DDRPHY is set as a first target value, and a second read command is sent to the DDR 3;
wherein the first target value is any one positive integer from 0 to 31;
judging whether DDR3 can feed back 1 period of DQS/DQSB in CL;
if so, marking the current value of the first target value to obtain a first target mark value, and acquiring the first target mark value.
In practical applications, when DDR3 operates at 2133Mbps, CK is clocked to 1066MHz, and CMD includes the command signals CAS #, RAS #, WE #, and CS #, in which case the command signals CAS #, RAS #, WE #, and CS # are active for only one cycle, i.e., the pull-down time is only 993 ns. In this context, in order to avoid the compression of the effective command window sent by DDRPHY to DDR3, it is necessary to synchronize the command signals CAS #, RAS #, WE # and CS # in CMD with CK as much as possible so that DDR3 obtains the largest command window.
Please refer to table 1, table 1 is a truth table of DDRPHY sending Read command and MRS command to DDR. As can be seen from table 1, when there are no other commands, CAS #, RAS #, WE # and CS # are all high level, and only one cycle is low level under the relevant command, each command signal can be scanned one by using the attribute characteristics of CAS #, RAS #, WE # and CS #, and the deskew value of the deskew register corresponding to each command signal CAS #, RAS #, WE # and CS # is configured according to the corresponding feedback information.
Table 1 shows truth table of DDRPHY in sending Read command and MRS command to DDR
| Truth table | CS# | RAS# | CAS# | WE# |
| Read command | L | H | L | H |
| MRS commands | L | L | L | L |
| Command-less | H | H | H | H |
The technical solution provided in this embodiment is to find the best deskew value of the deskew register corresponding to CS # or CAS # in a DDRPHY, so as to perform delay compensation on the CMD sent by the DDRPHY.
Specifically, in this embodiment, in order to obtain the optimal configuration value of the deskew value of CS # or CAS # in DDRPHY, first, a first read command is sent to DDR3, and it is determined whether DDR3 can feed back DQS/DQSB of 1 cycle in CL (CAS Latency); if so, it indicates that DDR3 can normally receive the read command sent by DDRPHY. At this time, the deskew value of CS # or CAS # is set as the first target value, and a second read command is sent to DDR3, and then it is determined whether DDR3 can feed back 1 cycle DQS/DQSB in CL, and if DDR3 can feed back 1 cycle DQS/DQSB in CL, it indicates that DDR3 can normally receive a read command sent by DDRPHY when the deskew value of CS # or CAS # is set as the first target value, that is, the current value of the first target value can be used to perform delay compensation on CS # or CAS #.
It should be noted that when a DDRPHY sends a CMD to the DDR3, a 32-level skew module is required, where each level corresponds to a unit delay according to different processes, and therefore, in this embodiment, the first target value is set to be any positive integer from 0 to 31. Obviously, by such an arrangement, it is equivalent to scanning the 32-level skew modules in the DDR3 one by one, and thus it can be determined which delay values the deskew value of CS # or CAS # is set to, and the DDR3 can receive the CS # or CAS # command signal transmitted by the DDRPHY, and in this case, the CMD can be delay-compensated by using these delay values.
In addition, in the present embodiment, since the first target value is set to any one positive integer from 0 to 31, in the actual operation process, the first target value may be set in such a manner that 1 is sequentially added from 0, or the first target value may be set in such a manner that 1 is sequentially subtracted from 31, or the first target value may be set in such a manner that a value is randomly taken, as long as the first target value can traverse all positive integers from 0 to 31, and the present embodiment is not particularly limited herein.
As a preferred embodiment, the above steps: after determining whether DDR3 can feed back 1 cycle DQS/DQSB in CL, the method further includes:
if not, the read rate at which the first read command is sent to DDR3 is reduced to enable DDR3 to feed back 1 cycle of DQS/DQSB within CL.
In practical operation, if the DDR3 cannot feed back 1 cycle of DQS/DQSB in the CL, it indicates that the DDR3 cannot normally receive the first read command sent by the DDRPHY, in this case, the DDRPHY needs to reduce the read rate of sending the first read command to the DDR3, so that the DDR3 can feed back 1 cycle of DQS/DQSB in the CL. It is contemplated that subsequent process steps may continue when the read rate at which the DDRPHY sends the first read command to the DDR3 is reduced to a rate that may enable the DDR3 to feed back 1 cycle of DQS/DQSB within the CL.
Obviously, the technical solution provided by this embodiment can further increase the integrity of the CMD delay compensation method for DDR3 provided by this application.
As a preferred embodiment, the above steps: the process of configuring deskew value of DDRPHY by using feedback information to perform delay compensation on CMD includes:
and storing the first target mark value into a first preset storage area, and setting a deskew value of the CS # or the CAS # according to the maximum value and the minimum value stored in the first preset storage area so as to perform delay compensation on the CMD.
It is understood that when the deskew value of CS # or CAS # in DDRPHY is set as the first target value, if the second read command is sent to DDR3, DDR3 can feed back 1 cycle DQS/DQSB within CL, which means that the current value of the first target value can make DDR3 normally receive the read command sent by DDRPHY. In this case, the current value of the first target value is marked to obtain a first target mark value, and the first target mark value is stored in the first preset storage area, which is equivalent to a data interval capable of performing delay compensation on CS # or CAS # stored in the first preset storage area.
Specifically, the steps are as follows: the process of setting the deskew value of CS # or CAS # according to the maximum value and the minimum value stored in the first preset storage area to perform delay compensation on CMD includes the following steps:
the middle value between the maximum value and the minimum value stored in the first preset memory area is set as the deskew value of the CS # or CAS # to perform delay compensation for the CMD.
In actual operation, the middle value between the minimum value and the maximum value stored in the first preset memory area may be set as the deskew value of RAS # or WE #. Wherein if the number between the minimum value and the maximum value is an odd number, one intermediate data between the minimum value and the maximum value is set as a deskew value of RAS # or WE #; if the number between the minimum value and the maximum value is an even number, two intermediate data between the minimum value and the maximum value are set as deskew values of RAS # or WE #.
Obviously, the accuracy of the deskew value configuration result of the CS # or CAS # can be further increased by the technical solution provided in this embodiment.
Based on the above embodiment, this embodiment further describes and optimizes the technical solution, and as a preferred implementation, the above steps: the process of sending CMD to DDR3 and obtaining feedback information of DDR3 includes:
sending a first MRS command to DDR3 to configure MR [1:0] as 2' b 00;
sending a third read command to the DDR3, and judging whether the DDR3 can feed back DQS/DQSB of 4 cycles in the CL;
if so, then a second MRS command is sent to DDR3 to configure MR [1:0] as 2' b 10;
sending a fourth read command to the DDR3, and judging whether the DDR3 can feed back 2 periods of DQS/DQSB in the CL;
if yes, setting the deskew value of RAS # or WE # in the DDRPHY as a second target value;
wherein the second target value is any one positive integer from 0 to 31;
sending a third MRS command to DDR3 to configure MR [1:0] to be 2' b 00;
sending a fifth read command to the DDR3, and judging whether the DDR3 can feed back DQS/DQSB of 4 cycles in the CL;
if so, marking the current value of the second target value to obtain a second target mark value, and acquiring the second target mark value;
correspondingly, the process of configuring the deskew value of the DDR3 with the feedback information to perform delay compensation on the CMD includes:
and storing the second target mark value into a second preset storage area, and setting the deskew value of RAS # or WE # according to the minimum value and the maximum value stored in the second preset storage area so as to perform delay compensation on the CMD.
As shown in Table 1, RAS # or WE # will be pulled down by one cycle during the MRS command and will be in a high state at other times, so the attribute feature of RAS # or WE # during the MRS command can be used to configure the deskew value corresponding to RAS # or WE # in DDR3, and thus delay compensation can be performed on CMD.
Specifically, DDRPHY first sends a first MRS command to DDR3 to configure MR [1:0] as 2' b00, and at this time, sends a third read command to DDR3, and determines whether DDR3 can feed back 4 cycles of DQS/DQSB in CL, and if DDR3 can feed back 4 cycles of DQS/DQSB in CL, it indicates that DDR3 is currently in BL8(fix) mode; then, DDRPHY sends a second MRS command to DDR3 to configure MR [1:0] as 2' b10, at which time, a fourth read command is sent to DDR3, and it is determined whether DDR3 can feed back 2 cycles of DQS/DQSB within CL, and if DDR3 can feed back 2 cycles of DQS/DQSB within CL, it indicates that DDR3 is currently in BL4(fix) mode. It is understood that if DDR3 can accurately feed back these two states, it indicates that DDR3 can normally recognize the MRS command sent by DDRPHY.
In this case, the deskew value of RAS # or WE # in DDRPHY may be set as a second target value, after the deskew value of RAS # or WE # is set as the second target value, a third MRS command is sent to DDR3 to configure MR [1:0] as 2' b00, and a fifth read command is sent to DDR3, and at the same time, it is determined whether DDR3 can feed back DQS/DQSB for 4 cycles in CL, if so, it is indicated that the current value of the second target value can perform delay compensation on the RAS # or WE # command, at this time, the current value of the second target value is marked to obtain a second target mark value, and a second target mark value is obtained.
And after the second target mark value is obtained, storing the second target mark value into a second preset storage area, setting the skew value of the RAS # or the WE # according to the minimum value and the maximum value stored in the second preset storage area, and performing delay compensation on the CMD.
It should be noted that, in this embodiment, the second target value is set to be any positive integer from 0 to 31, which may specifically refer to the reason for the value of the first target value, and is not described in detail herein. In addition, if the DDR3 cannot feed back 4 cycles of DQS/DQSB within CL after MR [1:0] is configured as 2' b00, it means that the current value of the second target value cannot compensate delay of RAS # or WE # command, and at this time, the current value of the second target value can be deleted.
In addition, in the actual operation process, when determining whether DDR3 can normally receive an MRS command sent by DDRPHY, MR [1:0] may be configured as 2' b10, and then a read command is sent to DDR3, if DDR3 can receive DQS/DQSB of 2 cycles in CL, it indicates that DDR3 is currently in BL4(fix) mode; then, MR [1:0] is configured to be 2' b00, and simultaneously a read command is sent to DDR3, if DDR3 can receive DQS/DQSB for 4 cycles in CL, it indicates that DDR3 is currently in BL8(fix) mode, so it can also be determined that DDR3 can normally receive MRs commands sent by DDRPHY.
In the process of configuring the deskew value of the deskew register corresponding to the RAS # or the WE # the second target mark value is stored in the second preset storage area, so that the second preset storage area is equivalent to a data area in which the delay compensation of the RAS # or the WE # can be performed, in this case, the maximum value and the minimum value stored in the second preset storage area are used for setting the deskew value of the RAS # or the SE # so as to perform the delay compensation of the CMD by using the set deskew value of the RAS # or the WE #. Specifically, in the actual operation process, the middle value between the maximum value and the minimum value stored in the second preset storage area may be set as the deskew value of RAS # or WE #, so as to further improve the accuracy of the delay compensation for the CMD.
Therefore, the technical scheme provided by the embodiment can enable the setting result of the deskew value of the RAS # or the WE # to be more accurate and reliable.
Referring to fig. 4, fig. 4 is a structural diagram of a CMD delay compensation apparatus for DDR3 according to an embodiment of the present invention, including:
the information feedback module 21 is configured to send a CMD to the DDR3, and acquire feedback information of the DDR 3;
and the delay compensation module 22 is configured to configure the deskew value of the DDRPHY by using the feedback information, so as to perform delay compensation on the CMD.
The CMD delay compensation device of the DDR3 provided by the embodiment of the invention has the beneficial effects of the CMD delay compensation method of the DDR3 disclosed above.
Referring to fig. 5, fig. 5 is a structural diagram of a CMD delay compensation device for DDR3 according to an embodiment of the present invention, where the CMD delay compensation device includes:
a memory 31 for storing a computer program;
the processor 32 is configured to implement the steps of the CMD delay compensation method of the DDR3 as disclosed above when executing the computer program.
The CMD delay compensation device of DDR3 provided by the embodiment of the invention has the beneficial effects of the CMD delay compensation method of DDR3 disclosed in the foregoing.
Accordingly, an embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the steps of the CMD delay compensation method for DDR3 as disclosed in the foregoing.
The computer-readable storage medium provided by the embodiment of the invention has the beneficial effects of the CMD delay compensation method for DDR3 disclosed in the foregoing.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. Finally, it should also be noted that, in this document, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The CMD delay compensation method, apparatus, device and medium for DDR3 provided by the present invention are described in detail above, and a specific example is applied herein to illustrate the principle and the implementation of the present invention, and the description of the above embodiment is only used to help understand the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (8)
1. A CMD delay compensation method of DDR3 is characterized in that, applied to DDRPHY, it includes:
sending CMD to DDR3, and obtaining feedback information of DDR 3;
configuring a deskew value of the DDRPHY by using the feedback information so as to perform delay compensation on the CMD;
the process of sending CMD to the DDR3 and acquiring feedback information of the DDR3 includes:
sending a first read command to the DDR3, and judging whether the DDR3 can feed back 1 cycle of DQS/DQSB in CL;
if yes, setting the deskew value of CS # or CAS # in the DDRPHY as a first target value, and sending a second read command to the DDR 3; wherein the first target value is any one positive integer from 0 to 31;
judging whether the DDR3 can feed back 1 period of DQS/DQSB in the CL;
if so, marking the current value of the first target value to obtain a first target mark value, and acquiring the first target mark value;
the configuring the deskew value of the DDRPHY by using the feedback information to perform delay compensation on the CMD includes:
and storing the first target mark value to a first preset storage area, and setting a deskew value of the CS # or the CAS # according to the maximum value and the minimum value stored in the first preset storage area so as to perform delay compensation on the CMD.
2. The CMD delay compensation method of claim 1, wherein the process of configuring deskew value of DDRPHY using the feedback information comprises:
and configuring the deskew value of the DDRPHY by utilizing the feedback information based on a state machine theory.
3. The CMD delay compensation method of claim 1, wherein after the determining whether DDR3 can feed back 1 cycle DQS/DQSB in CL, the method further comprises:
if not, the read rate of sending the first read command to the DDR3 is reduced to enable the DDR3 to feed back 1 cycle of DQS/DQSB within the CL.
4. The CMD delay compensation method of claim 1, wherein said setting the deskew value of CS # or CAS # according to the maximum and minimum values stored in said first predetermined memory area for delay compensation of the CMD comprises:
and setting the middle value between the maximum value and the minimum value stored in the first preset storage area as the deskew value of the CS # or the CAS # so as to perform delay compensation on the CMD.
5. The CMD delay compensation method of claim 1, wherein the process of sending CMD to DDR3 and obtaining feedback information of DDR3 comprises:
sending a first MRS command to the DDR3 to configure MR [1:0] as 2' b 00;
sending a third read command to the DDR3, and judging whether the DDR3 can feed back DQS/DQSB of 4 cycles in CL;
if so, sending a second MRS command to the DDR3 to configure MR [1:0] as 2' b 10;
sending a fourth read command to the DDR3, and determining whether the DDR3 can feed back 2 cycles of DQS/DQSB within the CL;
if yes, setting the deskew value of RAS # or WE # in the DDRPHY as a second target value; wherein the second target value is any one positive integer from 0 to 31;
sending a third MRS command to the DDR3 to configure MR [1:0] as 2' b 00;
sending a fifth read command to the DDR3, and determining whether the DDR3 can feed back DQS/DQSB of 4 cycles in the CL;
if so, marking the current value of the second target value to obtain a second target mark value, and acquiring the second target mark value;
correspondingly, the configuring the deskew value of the DDR3 with the feedback information to perform delay compensation on the CMD includes:
and storing the second target mark value into a second preset storage area, and setting the skew value of the RAS # or the WE # according to the minimum value and the maximum value stored in the second preset storage area so as to perform delay compensation on the CMD.
6. A CMD delay compensation device of DDR3, which is applied to DDRPHY, and comprises:
the information feedback module is used for sending CMD to DDR3 and acquiring feedback information of the DDR 3;
the delay compensation module is used for configuring the deskew value of the DDRPHY by utilizing the feedback information so as to perform delay compensation on the CMD;
the information feedback module is specifically configured to send a first read command to the DDR3, and determine whether the DDR3 can feed back 1 cycle of DQS/DQSB in CL;
if yes, setting the deskew value of the CS # or CAS # in the DDRPHY as a first target value, and sending a second read command to the DDR 3; wherein the first target value is any one positive integer from 0 to 31;
judging whether the DDR3 can feed back 1 period of DQS/DQSB in the CL;
if so, marking the current value of the first target value to obtain a first target mark value, and acquiring the first target mark value;
the delay compensation module is specifically configured to store the first target mark value in a first preset storage area, and set a deskew value of the CS # or the CAS # according to a maximum value and a minimum value stored in the first preset storage area, so as to perform delay compensation on the CMD.
7. A CMD delay compensation apparatus for DDR3, comprising:
a memory for storing a computer program;
a processor for implementing the steps of a CMD delay compensation method for DDR3 as recited in any one of claims 1 to 5 when said computer program is executed.
8. A computer-readable storage medium, having stored thereon a computer program which, when executed by a processor, implements the steps of a CMD delay compensation method for DDR3 as claimed in any one of claims 1 to 5.
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