CN116827330B - Strong anti-interference communication port circuit - Google Patents
Strong anti-interference communication port circuit Download PDFInfo
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- CN116827330B CN116827330B CN202211589749.5A CN202211589749A CN116827330B CN 116827330 B CN116827330 B CN 116827330B CN 202211589749 A CN202211589749 A CN 202211589749A CN 116827330 B CN116827330 B CN 116827330B
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Abstract
The invention relates to a communication port circuit, in particular to a strong anti-interference communication port circuit. It includes an input port and an output port. The input port is connected with the input end of the trigger device in an adapting way, the output end of the trigger device is connected with the filter shaping device in an adapting way, and the output end of the filter shaping device is connected with the output port in an adapting way. The filter shaping device is characterized in that the output end of the trigger device is connected with an inverter I NV4, the filter shaping device comprises a gate circuit AND2, an inverter I NV5, a resistor R2, a capacitor C1, an inverter I NV6, a gate circuit NOR2_1, a gate circuit NOR2_2 AND a gate circuit NOR2_3, AND the gate circuit AND2, the inverter I NV5, the resistor R2, the capacitor C1, the inverter I NV6, the gate circuit NOR2_1, the gate circuit NOR2_2 AND the gate circuit NOR2_3 form a loop. The communication port circuit can not narrow the pulse width of the effective signal, and ensures that the signal has better effectiveness.
Description
Technical Field
The invention relates to a communication port circuit, in particular to a strong anti-interference communication port circuit without reducing the effective width of a signal.
Background
Data communication is very commonly used in existing digital, digital-to-analog, and analog-to-digital circuits. When the working environment is severe, the anti-interference capability of the port must be improved, burrs must be suppressed, high-frequency signals must be filtered, and stability must be improved. This requires the use of an anti-interference communication port circuit.
At present, the traditional anti-interference communication port circuit structure is shown in fig. 1, wherein SMT1 and SMT2 are two Schmitt triggers, R1 is an input port protection resistor, R2 and C1 form RC filtering, SMT1 is used for generating an input hysteresis window, and signal jitter with smaller amplitude can be prevented from being identified as an effective signal; the filter formed by R2 and C1 can filter out the burr signal with large amplitude; SMT2 performs a reshaping function. However, when RC filtering is adopted in the structure, the pulse width of the effective signal is narrowed, and the effectiveness of the signal is affected.
Disclosure of Invention
The invention aims to solve the technical problem of providing a strong anti-interference communication port circuit, which can not narrow the pulse width of an effective signal and ensure better signal effectiveness.
In order to solve the problems, the following technical scheme is provided:
the strong anti-interference communication port circuit comprises an input port and an output port. The input port is connected with the input end of the trigger device in an adapting way, the trigger device forms an input hysteresis window, the output end of the trigger device is connected with the filter shaping device in an adapting way, and the output end of the filter shaping device is connected with the output port in an adapting way. The filter shaping device is characterized in that the output end of the trigger device is connected with an inverter INV4, the filter shaping device comprises a gate circuit AND2, an inverter INV5, a resistor R2, a capacitor C1, an inverter INV6, a gate circuit NOR2_1, a gate circuit NOR2_2 AND a gate circuit NOR2_3, AND the output end of the inverter INV4 is respectively connected with the first input end of the gate circuit AND2, the input end of the inverter INV5 AND the first input end of the gate circuit NOR 2_1. The output end of the gate circuit AND2 is connected with the first input end of the gate circuit NOR2_3, the output end of the inverter INV5 is connected with one end of the resistor R2, the other end of the resistor R2 is respectively connected with one end of the capacitor C1 AND the input end of the inverter INV6, the other end of the capacitor C1 is grounded, the output end of the inverter INV6 is respectively connected with the second input end of the gate circuit AND2 AND the second input end of the gate circuit NOR2_1, the output end of the gate circuit NOR2_1 is connected with the first input end of the gate circuit NOR2_2, the second input end of the gate circuit NOR2_2 is connected with the output end of the gate circuit NOR2_3, AND the output end of the gate circuit NOR2_2 is the output end of the filter shaping device.
Wherein the gate AND2 is a two-input AND gate or equivalent structure, AND the gates nor2_1, nor2_2 AND nor2_3 are two-input NOR gates or equivalent structures.
The trigger device comprises an inverter INV1, an inverter INV2, an inverter INV3, a gate circuit NAND2_1 and a gate circuit NAND2_2, wherein the input port is respectively and adaptively connected with the input end of the inverter INV1 and the input end of the inverter INV3, the output end of the inverter INV1 is connected with the input end of the inverter INV2, the output end of the inverter INV2 is connected with the first input end of the gate circuit NAND2_1, the output end of the gate circuit NAND2_1 is the output end of the trigger device, and the output end of the gate circuit NAND2_1 is connected with the first input end of the gate circuit NAND 2_2. The output end of the inverter INV3 is connected to the second input end of the gate circuit NAND2_2, and the output end of the gate circuit NAND2_2 is connected to the second input end of the gate circuit NAND 2_1.
The inverter INV1 is an inverter or equivalent structure with a low input turning level, and the inverter INV3 is an inverter or equivalent structure with a high input turning level. The gate circuits NAND2_1 and NAND2_2 are two-input NAND gates or equivalent structures.
The input port is connected with one end of a resistor R1, and the other end of the resistor R1 is connected with the trigger device.
The output end of the filter shaping device is connected with the input end of the buffer, and the output end of the buffer is connected with the output port.
The buffer comprises an inverter INV7 and an inverter INV8, wherein the output end of the filter shaping device is connected with the input end of the inverter INV7, the output end of the inverter INV7 is connected with the input end of the inverter INV8, and the output end of the inverter INV8 is connected with the output port.
By adopting the scheme, the method has the following advantages:
since the output end of the trigger device of the strong anti-interference communication port circuit of the present invention is connected to the inverter INV4, the filter shaping device comprises the gate circuit AND2, the inverter INV5 AND the gate circuit nor2_1, the output end of the inverter INV4 is connected to the first input end of the gate circuit AND2, the input end of the inverter INV5 is connected to the first input end of the gate circuit nor2_3, the output end of the inverter INV5 is connected to one end of the resistor R2, the other end of the resistor R2 is connected to one end of the capacitor C1 AND the input end of the inverter INV6, the other end of the capacitor C1 is grounded, the output end of the inverter INV6 is connected to the second input end of the gate circuit nor2_1, the output end of the gate circuit nor2_1 is connected to the first input end of the gate circuit nor2_2, the second input end of the gate circuit nor2_2 is connected to the output end of the gate circuit nor2_3, AND the output end of the gate circuit nor2_2_3 is connected to the filter shaping device. The loop formed by the inverter INV5, the inverter INV6, the gate circuit AND2, the gate circuit NOR2_1, the gate circuit NOR2_2, the gate circuit NOR2_3, the resistor R2 AND the capacitor C1 can filter out the signal with the high level pulse width lower than the time constant tau in the signal at the output end of the inverter INV4, AND the signal AND the inverter INV6 are compared, so that when the high level width of the signal is greater than the time constant tau, the output signal width is unchanged, namely the signal at the output end of the gate circuit NOR2_2 is consistent with the signal width at the output end of the INV4, so that the pulse width of the effective signal is not narrowed, AND the effectiveness of the signal is better.
Drawings
FIG. 1 is a schematic diagram of an anti-interference communication port circuit in the background art;
FIG. 2 is a schematic diagram of a strong anti-interference communication port circuit according to the present invention (implementation one);
fig. 3 is a schematic structural diagram of the strong anti-interference communication port circuit in two states.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples.
Example 1
As shown in fig. 2, the strong anti-interference communication port circuit of the present invention includes an input port and an output port. The input port is connected with one end of a resistor R1, the other end of the resistor R1 is connected with the input end of a trigger device in an adapting way, the trigger device forms an input hysteresis window, the output end of the trigger device is connected with a filter shaping device in an adapting way, and the output end of the filter shaping device is connected with the output port. The output end of the trigger device is connected with the inverter INV4, the filter shaping device comprises a gate circuit AND2, an inverter INV5, a resistor R2, a capacitor C1, an inverter INV6, a gate circuit nor2_1, a gate circuit nor2_2 AND a gate circuit nor2_3, AND the output end of the inverter INV4 is respectively connected with the first input end of the gate circuit AND2, the input end of the inverter INV5 AND the first input end of the gate circuit nor2_1. The output end of the gate circuit AND2 is connected with the first input end of the gate circuit NOR2_3, the output end of the inverter INV5 is connected with one end of the resistor R2, the other end of the resistor R2 is respectively connected with one end of the capacitor C1 AND the input end of the inverter INV6, AND the other end of the capacitor C1 is grounded. The resistor R2 and the capacitor C1 form a filter circuit with a time constant τ. The output end of the inverter INV6 is connected to the second input end of the AND circuit AND2 AND the second input end of the gate circuit nor2_1 respectively, the output end of the gate circuit nor2_1 is connected to the first input end of the gate circuit nor2_2, the second input end of the gate circuit nor2_2 is connected to the output end of the gate circuit nor2_3, the output end of the gate circuit nor2_2 is connected to the second input end of the gate circuit nor2_3, AND the output end of the gate circuit nor2_2 is the output end of the filter shaping device.
The gate AND2 is a two-input AND gate or equivalent structure, AND the gates nor2_1, nor2_2, AND nor2_3 are two-input NOR gates or equivalent structures. In the present embodiment, the gate AND2 is a two-input AND gate, AND the gates nor2_1, nor2_2, AND nor2_3 are two-input NOR gates. The trigger device is a schmitt trigger.
The schmitt trigger forms an input hysteresis window, thereby realizing the anti-interference capability of the whole circuit. Inverter INV4 is a logic transition that causes the filter shaper to filter out the high level glitch. The loop formed by the inverter INV5, the inverter INV6, the gate circuit AND2, the gate circuit nor2_1, the gate circuit nor2_2, the gate circuit nor2_3, the resistor R2 AND the capacitor C1 can filter out the signal with the high level pulse width lower than the time constant τ in the signal at the output end of the inverter INV4, AND the signal AND the inverter INV6 are compared, so that when the high level width of the signal is greater than the time constant τ, the output signal width is unchanged, namely the signal at the output end of the gate circuit nor2_2 is consistent with the signal width at the output end of the INV4, so that the pulse width of the effective signal is not narrowed, AND the signal effectiveness is better.
Example two
As shown in fig. 3, the strong anti-interference communication port circuit of the present invention includes an input port and an output port. The input port is connected with one end of a resistor R1, the other end of the resistor R1 is connected with the input end of a trigger device in an adapting way, the trigger device forms an input hysteresis window, the output end of the trigger device is connected with a filter shaping device in an adapting way, and the output end of the filter shaping device is connected with the output port. The trigger device comprises an inverter I NV1, an inverter I NV2, an inverter I NV3, a gate circuit NAND2_1 and a gate circuit NAND2_2, wherein the input port is respectively connected with the input end of the inverter I NV1 and the input end of the inverter I NV3 in an adapting way, the output end of the inverter I NV1 is connected with the input end of the inverter I NV2, the output end of the inverter I NV2 is connected with the first input end of the gate circuit NAND2_1, the output end of the gate circuit NAND2_1 is the output end of the trigger device, and the output end of the gate circuit NAND2_1 is connected with the first input end of the gate circuit NAND 2_2. The output of the inverter I NV3 is connected to the second input of the gate circuit NAND2_2 and the output of the gate circuit NAND2_2 is connected to the second input of the gate circuit NAND2_ 1. The gate circuits NAND2_1 and NAND2_2 constitute an RS flip-flop. The inverter I NV1, the inverter I NV2, the inverter I NV3, the gate circuit NAND2_1 and the gate circuit NAND2_2 constitute a structure with a large hysteresis window and a high speed.
The inverter I NV1 is an inverter or an equivalent structure with low input turning level, and the inverter I NV3 is an inverter or an equivalent structure with high input turning level. The gate circuits NAND2_1 and NAND2_2 are two-input NAND gates or equivalent structures. In this embodiment, the inverter I NV1 is an inverter with a low input transition level, and the inverter I NV3 is an inverter with a high input transition level. In this embodiment, at 5V, the input turning level of the inverter I NV1 is 2.5V, and the input turning level of the inverter I NV3 is 1.1V.
The output end of the trigger device is connected with the inverter I NV4, the filter shaping device comprises a gate circuit AND2, an inverter I NV5, a resistor R2, a capacitor C1, an inverter I NV6, a gate circuit NOR2_1, a gate circuit NOR2_2 AND a gate circuit NOR2_3, AND the output end of the inverter I NV4 is respectively connected with the first input end of the gate circuit AND2, the input end of the inverter I NV5 AND the first input end of the gate circuit NOR 2_1. The output end of the gate circuit AND2 is connected with the first input end of the gate circuit NOR2_3, the output end of the inverter I NV5 is connected with one end of the resistor R2, the other end of the resistor R2 is respectively connected with one end of the capacitor C1 AND the input end of the inverter I NV6, AND the other end of the capacitor C1 is grounded. The resistor R2 and the capacitor C1 form a filter circuit with a time constant τ. The output end of the inverter I NV6 is connected to the second input end of the AND circuit AND2 AND the second input end of the gate circuit nor2_1 respectively, the output end of the gate circuit nor2_1 is connected to the first input end of the gate circuit nor2_2, the second input end of the gate circuit nor2_2 is connected to the output end of the gate circuit nor2_3, the output end of the gate circuit nor2_2 is connected to the second input end of the gate circuit nor2_3, AND the output end of the gate circuit nor2_2 is the output end of the filter shaping device.
The gate AND2 is a two-input AND gate or equivalent structure, AND the gates nor2_1, nor2_2, AND nor2_3 are two-input NOR gates or equivalent structures. In the present embodiment, the gate AND2 is a two-input AND gate, AND the gates nor2_1, nor2_2, AND nor2_3 are two-input NOR gates.
The output end of the filter shaping device is connected with the input end of the buffer, and the output end of the buffer is connected with the output port. The buffer comprises an inverter I NV7 and an inverter I NV8, wherein the output end of the filter shaping device is connected with the input end of the inverter I NV7, the output end of the inverter I NV7 is connected with the input end of the inverter I NV8, and the output end of the inverter I NV8 is connected with the output port. The buffer formed by the INV7 and the inverter INV8 solves the defects of poor anti-interference performance, asymmetry and the like of an output port of the filter shaping device formed by the gate circuit.
The gate circuits NAND2_1 and NAND2_2 constitute an RS flip-flop in this embodiment. The inverter INV1, the inverter INV2, the inverter INV3, the gate circuit NAND2_1 and the gate circuit NAND2_2 form a structure with a large hysteresis window and a high speed, can realize the function of the schmitt trigger, and has a speed far higher than that of the schmitt trigger.
After the signal output by the inverter INV4 is divided into three paths AND output to the input ends of the gate circuit AND2, the inverter INV5 AND the gate circuit nor2_1, the signal output by the inverter INV4 can be filtered out by a loop formed by the inverter INV5, the inverter INV6, the gate circuit AND2, the gate circuit nor2_1, the gate circuit nor2_2, the gate circuit nor2_3, the resistor R2 AND the capacitor C1, but because the signal AND the signal are compared, when the high level width of the signal is larger than the time constant τ, the output signal width is unchanged, namely the signal width received by the input port of the inverter INV7 is consistent with the signal width of the output end of the inverter INV 4.
In summary, in the structure of the embodiment, the trigger device is a structure with a high-speed response and a larger input hysteresis window, so that jitter and ripple with smaller amplitude can be effectively filtered. Inverter INV4 is a logic transition that causes the filter shaper to filter out the high level glitch. The filter shaping device is a structure capable of effectively filtering out the pulse width smaller than the time constant tau, and the pulse width larger than the time constant tau does not affect the width.
Claims (6)
1. The strong anti-interference communication port circuit comprises an input port and an output port; the input port is connected with the input end of the trigger device in an adapting way, the trigger device forms an input hysteresis window, the output end of the trigger device is connected with the filter shaping device in an adapting way, and the output end of the filter shaping device is connected with the output port in an adapting way; the filter shaping device is characterized in that the output end of the trigger device is connected with an inverter INV4, the filter shaping device comprises a gate circuit AND2, an inverter INV5, a resistor R2, a capacitor C1, an inverter INV6, a gate circuit NOR2_1, a gate circuit NOR2_2 AND a gate circuit NOR2_3, AND the output end of the inverter INV4 is respectively connected with the first input end of the gate circuit AND2, the input end of the inverter INV5 AND the first input end of the gate circuit NOR 2_1; the output end of the gate circuit AND2 is connected with the first input end of the gate circuit NOR2_3, the output end of the inverter INV5 is connected with one end of the resistor R2, the other end of the resistor R2 is respectively connected with one end of the capacitor C1 AND the input end of the inverter INV6, the other end of the capacitor C1 is grounded, the output end of the inverter INV6 is respectively connected with the second input end of the gate circuit AND2 AND the second input end of the gate circuit NOR2_1, the output end of the gate circuit NOR2_1 is connected with the first input end of the gate circuit NOR2_2, the second input end of the gate circuit NOR2_2 is connected with the output end of the gate circuit NOR2_3, AND the output end of the gate circuit NOR2_2 is the output end of the filter shaping device; the trigger device comprises an inverter INV1, an inverter INV2, an inverter INV3, a gate circuit NAND2_1 and a gate circuit NAND2_2, wherein the input port is respectively and adaptively connected with the input end of the inverter INV1 and the input end of the inverter INV3, the output end of the inverter INV1 is connected with the input end of the inverter INV2, the output end of the inverter INV2 is connected with the first input end of the gate circuit NAND2_1, the output end of the gate circuit NAND2_1 is the output end of the trigger device, and the output end of the gate circuit NAND2_1 is connected with the first input end of the gate circuit NAND 2_2; the output end of the inverter INV3 is connected to the second input end of the gate circuit NAND2_2, and the output end of the gate circuit NAND2_2 is connected to the second input end of the gate circuit NAND 2_1.
2. The strong anti-interference communication port circuit according to claim 1, wherein the gate AND2 is a two-input AND gate or equivalent structure, AND the gates NOR2_1, NOR2_2 AND NOR2_3 are two-input NOR gates or equivalent structures.
3. The strong anti-interference communication port circuit as claimed in claim 1, wherein said inverter INV1 is an inverter or equivalent structure with a low input turning level, and said inverter INV3 is an inverter or equivalent structure with a high input turning level;
the gate circuits NAND2_1 and NAND2_2 are two-input NAND gates or equivalent structures.
4. The strong anti-interference communication port circuit as set forth in claim 1, wherein said input port is connected to one end of a resistor R1, and the other end of the resistor R1 is connected to said trigger device.
5. The strong anti-interference communication port circuit according to any of claims 1-4, wherein the output of the filter shaping device is connected to the input of a buffer, the output of the buffer being connected to the output.
6. The strong anti-interference communication port circuit of claim 5, wherein the buffer comprises an inverter INV7 and an inverter INV8, the output of the filter shaper is connected to the input of the inverter INV7, the output of the inverter INV7 is connected to the input of the inverter INV8, and the output of the inverter INV8 is connected to the output port.
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| CN202211589749.5A CN116827330B (en) | 2022-12-12 | 2022-12-12 | Strong anti-interference communication port circuit |
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| CN202211589749.5A CN116827330B (en) | 2022-12-12 | 2022-12-12 | Strong anti-interference communication port circuit |
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| 基于FPGA的自动增益控制系统的设计;王大迟;吴扬;贾义;;集成电路应用;20200908(第09期);全文 * |
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