CN217388680U - Signal tri-state hardware circuit - Google Patents
Signal tri-state hardware circuit Download PDFInfo
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- CN217388680U CN217388680U CN202220055720.8U CN202220055720U CN217388680U CN 217388680 U CN217388680 U CN 217388680U CN 202220055720 U CN202220055720 U CN 202220055720U CN 217388680 U CN217388680 U CN 217388680U
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Abstract
The utility model discloses a three state hardware circuit of signal, including input, drive end, collection end and isolation element, be equipped with isolation element between drive end and the input, the input is used for inputing 0 and 1 two kinds of digital signal or is in unsettled state, and the drive end corresponds output 0 or 1 two kinds of digital signal according to the input state, and the collection end shows corresponding state according to the input state. The utility model provides a signal tristate hardware circuit implementation method, for two state digital signal representation methods, signal tristate representation method can represent more signal status.
Description
Technical Field
The utility model belongs to the technical field of the electron, concretely relates to signal circuit.
Background
A single-bit digital signal usually has only two states, 0 and 1, and when N digital signals are used, only 2N states can be represented, and more than 2N states cannot be represented. By using a signal tri-state representation method, a one-bit digital signal can have three states of 0, 1 and Z, N digital signals can be used for representing 3N states, and the information represented by the same one-bit digital signal is far more abundant than that represented by a common digital signal.
SUMMERY OF THE UTILITY MODEL
To prior art's defect, the utility model aims to solve the technical problem that a signal tristate hardware circuit is just provided, conveniently realizes signal tristate.
In order to solve the technical problem, the utility model adopts the following technical scheme: the utility model provides a signal tristate hardware circuit, includes input end, drive end, gathers end and isolation element, be equipped with isolation element between drive end and the input end, the input end is used for inputing two kinds of digital signal of 0 and 1 or is in unsettled state, and the drive end corresponds output two kinds of digital signal of 0 or 1 according to the input end state, gathers the end and shows corresponding state according to the input end state.
Preferably, the isolation element is a resistor.
Preferably, the acquisition end and the input end are short-circuited or connected with a buffer.
The utility model discloses a signal tristate hardware circuit, which comprises a driving end, a collecting end and an input end; the driving end is separated from the input end, and the separated component can be a resistor; the acquisition end and the input end can be in short circuit, or a buffer is added; the driving end outputs two states of 0 and 1, and the level state of the acquisition end is read back; and judging whether the input end is in a 0 state, a 1 state or a suspended state by reading back the level state of the acquisition end. Therefore, a signal tri-state hardware circuit implementation method is provided, and compared with a two-state digital signal representation method, the signal tri-state representation method can represent more signal states.
The specific technical solution and the advantages of the present invention will be described in detail in the following detailed description with reference to the accompanying drawings.
Drawings
The invention will be further described with reference to the accompanying drawings and specific embodiments:
fig. 1 is a schematic circuit diagram of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
It will be appreciated by those skilled in the art that features from the examples and embodiments described below may be combined with each other without conflict.
Referring to fig. 1, a signal tri-state hardware circuit includes an input terminal, a driving terminal, a collecting terminal, and an isolation element, where the input terminal is used to input two digital signals, i.e., 0 and 1, or is in a floating state, the driving terminal correspondingly outputs two digital signals, i.e., 0 and 1, according to the state of the input terminal, and the collecting terminal shows a corresponding state according to the state of the input terminal.
The signal tri-state hardware circuit needs to output signals of 0 and 1 to the driving end and simultaneously acquire the signal state of the acquisition end.
When the state of the input end is 0 and the output of the driving end is 0, the state of the acquisition end is 0;
when the state of the input end is 0 and the output of the driving end is 1, the state of the acquisition end is 0;
when the state of the input end is 1, the output of the driving end is 0, then the state of the acquisition end is 1;
when the state of the input end is 1, the output of the driving end is 1, then the state of the acquisition end is 1;
when the state of the input end is suspended Z, the output of the driving end is 0, and then the state of the acquisition end is 0;
when the state of the input end is suspended Z and the output of the driving end is 1, the state of the acquisition end is 1;
the driving end outputs different signals and the acquisition end presents different states according to different input end states. The relationship of the driving end, the collecting end and the input end is shown in table 1.
Table 1: three-state signal truth table
Therefore, the driving end outputs two states of 0 and 1, and the input end is judged to be in three states of 0, 1 and suspended through reading back the level state of the acquisition end. The utility model discloses for two state digital signal representation methods, signal three state representation method can show more signal state.
It will be appreciated that the isolation element may be a resistor. The acquisition end and the input end are in short circuit or connected with a buffer.
The above description is only for the specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto, and those skilled in the art should understand that the present invention includes but is not limited to the contents described in the above specific embodiments. Any modification which does not depart from the functional and structural principles of the present invention is intended to be included within the scope of the claims.
Claims (3)
1. A signal tristate hardware circuit, characterized by: including input end, drive end, collection end and isolation element, be equipped with isolation element between drive end and the input, the input is used for inputing 0 and 1 two kinds of digital signal or is in unsettled state, and the drive end corresponds output 0 or 1 two kinds of digital signal according to the input state, and the collection end shows corresponding state according to the input state.
2. A signal tristate hardware circuit as claimed in claim 1 wherein: the isolation element is a resistor.
3. A signal tristate hardware circuit as claimed in claim 1 wherein: the acquisition end and the input end are in short circuit or connected with a buffer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220055720.8U CN217388680U (en) | 2022-01-06 | 2022-01-06 | Signal tri-state hardware circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220055720.8U CN217388680U (en) | 2022-01-06 | 2022-01-06 | Signal tri-state hardware circuit |
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| Publication Number | Publication Date |
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| CN217388680U true CN217388680U (en) | 2022-09-06 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202220055720.8U Active CN217388680U (en) | 2022-01-06 | 2022-01-06 | Signal tri-state hardware circuit |
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| CN (1) | CN217388680U (en) |
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2022
- 2022-01-06 CN CN202220055720.8U patent/CN217388680U/en active Active
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