KR100290960B1 - Glitch filter circuit for removing clock noise - Google Patents

Abstract

PURPOSE: A glitch filter circuit for removing the clock noise is provided to remove the clock noise so as to prevent the malfunction of a system. CONSTITUTION: The glitch filter circuit comprises a delay(210) delaying a specific time by receiving a first pulse signal and a latch(220) latching the previous state from the point that the first signal transits from the low state to the high state or from the high state to the low state by receiving the first and delayed first signal until the delayed pulse signal is transmitted, and generating a second pulse signal from the noise removed first pulse signal. The delay comprises a plurality of inverters in a serially connected structure and the capacitors respectively connected between an output and earth terminal, and the first invert receives the first pulse signal.

Description

Glitch Filter Circuit to Eliminate Clock Noise

1 is a conventional clock generation circuit without using a glitch filter circuit,

2 is a configuration diagram of an embodiment of a clock generation circuit using a glitch filter circuit according to the present invention;

3 is a configuration diagram of an embodiment of a glitch filter circuit for removing clock noise according to the present invention;

4 is a waveform diagram of the glitch filter circuit of FIG.

The present invention relates to a glitch filter circuit, and more particularly, to a glitch filter circuit for removing clock noise of an oscillator.

Glitch filters are used in computer systems and electronic circuits to remove noise signals when unwanted noise signals are applied to electrical signals.

In particular, when the oscillator is used to generate a clock by using an external crystal, noise from the outside may affect the clock, causing a system malfunction.

Accordingly, it is an object of the present invention to provide a glitch filter circuit in a clock generation circuit so as to eliminate the clock noise to prevent malfunction of the system.

In order to achieve the above object, the glitch filter circuit according to the present invention receives a first pulse signal to delay a predetermined time and receives the first pulse signal and a delayed first pulse signal to receive the first pulse signal in a low state. Latching means for latching the previous state until the delayed first pulse signal transitions at the time when the state transitions from the high state to the low state and generates a second pulse signal from which the glitch of the first pulse signal is removed Characterized in that consisting of.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a conventional clock generation circuit that does not use a glitch filter circuit, and an external crystal oscillator drives the clock oscillator 10 to generate a clock of the system.

Therefore, when noise occurs in the external crystal oscillator, the first pulse signal, which is the output of the clock oscillator 10, is affected by the noise, and as a result, glitch due to noise may occur in the system clock, which is the output of the clock generator 20, thereby causing Malfunctions occur.

2 is a diagram of a specific embodiment of a clock generation circuit using a glitch filter circuit for implementing the present invention, wherein an external glitch filter circuit 200 is inserted between the clock oscillator 110 and the clock generation circuit 120 to generate an external clock that may occur in a conventional clock generation circuit. The first pulse signal to which the noise signal is added generates a second pulse signal from which the glitch has been removed by the glitch filter circuit. Therefore, the system clock, which is the output of the clock generation circuit, is generated by the noise because the glitch is not generated. This prevents any malfunction of the system.

3 is a diagram of a specific embodiment for carrying out the present invention. The glitch filter circuit 200 includes delay means 210 and latch means 220 for delaying a first pulse signal for a predetermined time or more.

The delay means 210 is composed of four series inverters and four MOS transistors. A first pulse signal is applied to an input of the first inverter 211, and an output of the first inverter is connected to an input of the second inverter 212 and a gate of the first MOS transistor C1, and an output of the second inverter 212 is connected to the third inverter 213. Is connected to the input of the gate and the gate of the second MOS transistor C2, the output of the third inverter 213 is connected to the input of the fourth inverter 214 and the gate of the third MOS transistor C3 and the output of the fourth inverter 214 is latch means 220 The input of is connected to the gate of the fourth MOS transistor C4.

The drains and sources of the first, second, third and fourth MOS transistors are all connected to the ground voltage VSS.

In the embodiment of the present invention, the delay means includes four inverters and four MOS transistors. A plurality of inverters and morph transistors can be adjusted to delay the first pulse for a desired period of time or more.

The latch means 220 is composed of an end gate 221 and three Noah gates 222, 223, and 224.

The input terminals of the AND gate 221 and the NOA gate 222 are connected to the first pulse signal-D which is the output of the first pulse signal and the delay means, respectively, and the first input of the NOA gate 223 is connected to the output of the AND gate 221. The second input is connected to the output of Noah gate 224, the second pulse signal, which is the output of Noah gate 223, is input to the clock generator and is connected to the first input of Noah gate 224, and the second input of Noah gate 224 is Noah. It is connected to the output of gate 222.

Based on the configuration of FIG. 3 described above, the present invention will be described in detail with reference to the operation waveform diagram of FIG.

First, the first pulse signal and the first pulse signal-D, which are delayed from the clock oscillator and the first pulse signal by a predetermined time or more, are inputted to the AND gate 221 and the NOA gate 222 of the latch means 220, and thus the first pulse signal and the first pulse. When the signal-D has the same logic value, the second pulse signal, which is the output of the latching means, inverts the first pulse signal and outputs the same.

That is, since the first pulse signal and the first pulse signal-D have a low logic value during t1 time, the second pulse signal, which is an output of latch latch, outputs a high logic value. Maintain high logic value. During the time t2 to t3, since the first pulse signal and the first pulse signal-D have a high logic value, the second pulse signal outputs a low logic value.

Therefore, even when the first pulse signal is glitch due to external noise (section t3 to t4 or section t7 to t8), the low logic value is maintained for the state value before the second pulse signal, which is the output of the latch means, that is, for the region t3 to t4. In the period t7 to t8, the high logic value is maintained and the second pulse signal has the previous state value even in the period between the glitch period t1 of the first pulse signal-D, t5, t6, and t9, t10, so that the second pulse signal is noisy. The glitches are removed so that the system clock does not glitches and the system will operate normally.

The delay means 210 may delay the first pulse signal for a predetermined time by using a plurality of inverters and MOS transistors, and may use conventional capacitors instead of MOS transistors. However, using a MOS transistor rather than a capacitor is advantageous in terms of chip layout.

The delay time of the first pulse signal may be adjusted to a desired value by adjusting the number of inverters and MOS transistors. However, the first pulse signal should be delayed for a longer time than the maximum pulse width of the glitch due to noise. Otherwise, the second pulse signal, which is the output of the latch means, is affected by the noise, which may cause a malfunction of the system.

The first pulse signal D, which is the output of the delay means, should select one of the outputs of the even-numbered inverters of the inverters of the plurality of series connection configurations.

Claims (6)

A glitch filter circuit comprising: delay means for receiving a first pulse signal and delaying a predetermined time; And receiving the first pulse signal and the delayed first pulse signal until the delayed first pulse signal transitions at a time when the first pulse signal transitions from the low state to the high state or from the high state to the low state. And a latch means for latching a previous state and generating a second pulse signal from which the glitch of said first pulse signal has been removed. 2. The glitch filter circuit according to claim 1, further comprising clock oscillator means for generating said first pulse signal. The method of claim 1, wherein the delay means comprises a plurality of series-connected inverters and capacitors connected between the output terminal and the ground terminal of the inverters, respectively, and the first stage inverter is configured to receive the first pulse signal. Glitch filter circuit, characterized in that. 4. The glitch filter circuit according to claim 3, wherein the delayed first pulse signal, which is the output of the delay means, is output from an even-numbered inverter. 4. The glitch of claim 3, wherein the plurality of capacitors have a gate, a first drain / source, and a second drain / source, and each of the capacitors includes transistors having respective gates connected to output terminals of the respective inverters. Filter circuit. 2. The apparatus of claim 1, wherein the latching means comprises: a first end gate and a first noar gate for receiving the first pulse signal and the delayed first pulse signal; A second NOR gate having a first input coupled to the output of the first AND gate; And having a first input connected to the output of the first noah gate and a second input connected to the output of the second noah gate, the output comprising a third noah gate connected to the second input of the second noah gate. Glitch filter circuit, characterized in that.