JPH05259837A - Glitch elimination circuit for logic circuit - Google Patents

Abstract

PURPOSE:To provide the glitch elimination circuit for a logic circuit by which glitch is eliminated without use of a clock signal of the logic circuit. CONSTITUTION:A glitch is invaded in a correct logic signal as an output signal Y of a logic circuit 100. The signal Y is given to a latch circuit 410 via delay elements 211, 212. A signal DY1 after delay and a signal Y before delay are compared by an XOR circuit 221 and a signal GY1 resulting from detecting a change in a logic value of the signal Y is generated. A gate pulse generating section 300 forms a one-shot multivibrator triggered by the signal GY1 and generates a gate pulse having a prescribed pulse width synchronously with the signal GY1. A latch circuit 410 passes through the signal DY2 as it is usually and while a gate pulse is given to a terminal GT, a just preceding logic output is kept and passing of glitch is blocked.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a glitch removing circuit for a logic circuit, and more particularly to a circuit for removing a glitch without using a clock signal of the logic circuit.

[0002]

2. Description of the Related Art When a combinational logic circuit is realized by actual elements, theoretically impossible pulses may occur. Such a pulse is generated due to variations in the operating time of each logic element, and is usually a pulse with a very short pulse width, and is generally called a glitch. This glitch causes a malfunction of another logic circuit connected in the subsequent stage, and thus it must be removed. For example, in Japanese Patent Laid-Open No. 63-276913,
A technique for preventing malfunction due to a clock pulse delay is disclosed.

[0003]

The conventional glitch removing circuit uses the clock signal of the logic circuit to remove the glitch. However, this method of using a clock signal has a problem that the logic output is delayed by one clock cycle, and that it cannot sufficiently cope with a logic circuit using a plurality of clock signals.

Therefore, an object of the present invention is to provide a glitch removing circuit for a logic circuit which can remove the glitch without using a clock signal for the logic circuit.

[0005]

According to the present invention, in a circuit for eliminating a glitch generated in a logic circuit, a change detection means for detecting a change in an output logic state of the logic circuit and a logic signal used in the logic circuit. Gate pulse generating means for generating a gate pulse having a width smaller than the logic operation period and larger than the width of the glitch to be removed, and rising when the change detecting means detects the change, and the gate pulse generating means. Logic maintaining means for maintaining the output logic state of the logic circuit as it was before the gate pulse was generated.

[0006]

[Operation] The change in the logic state in the logic circuit is detected by the change detecting means. Then, a gate pulse is generated when this change is detected. The logic maintaining means maintains the output logic state of the logic circuit as it is while the gate pulse is generated. The pulse width of this gate pulse is set larger than the width of the glitch to be removed. Therefore, when the change detecting means detects a glitch, the glitch is blocked and is not output. On the other hand, the width of the gate pulse is set smaller than the logic operation cycle of the logic signal used in the logic circuit. Therefore, when the change detecting means detects a logic signal, this logic signal is output after the disappearance of the gate pulse. Thus, only the logic signal is output and the glitch is removed.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below based on illustrated embodiments. First, for reference, the configuration of a conventional general glitch removing circuit will be described. FIG. 1 is a circuit diagram showing an example of a conventional glitch removing circuit. Logic circuit 100
Is composed of three input terminals 11, 12, and 13, D-type flip-flops 20 and 30, and an OR circuit 40. The glitch generated in the logic circuit 100 is generated by the D-type flip-flop 50. The removed glitch-free logic signal is obtained at the output terminal 99. In the logic circuit 100, the input signal A given to the input terminal 11 is inputted to the input terminal D of the flip-flop 20, and the input signal B given to the input terminal 12 is inputted to the input terminal D of the flip-flop 30. , Clock terminal CK of each flip-flop 20, 30
The clock signal CLK supplied to the input terminal 13 is input to the. Then, the logical output QA obtained at the output terminal Q of the flip-flop 20 and the flip-flop 3
The logic output QB obtained at the output terminal Q of 0 is given to the OR circuit 40, and the output signal Y of this OR circuit 40 becomes the logic output of this logic circuit 100.

Since flip-flops 20 and 30 operate in synchronization with the same clock signal CLK, theoretically, no glitch occurs in this logic circuit 100. However, in practice, a glitch occurs between the flip-flops 20 and 30 due to a difference in operation time. The principle of this glitch occurrence will be shown in the time chart of FIG. Now, consider the operation of logic circuit 100 when input signals A and B and clock signal CLK as shown in FIG. 2 are applied. Clock signal CLK is applied to flip-flops 20 and 30 at time t1. Thereby, each flip-flop performs a predetermined logic operation and outputs the logic outputs QA and QB. However, if there is a difference in operation time between the flip-flops, for example, the logic output QA is inverted at time t2, The logic output QB will be inverted at time t3, which is slightly later than that. Therefore, this time t2
A glitch G having a time width corresponding to the delay time of t3 is generated, and the glitch G appears in the output signal Y of the OR circuit 40 at time t2 '. Then, when the second clock is applied at time t4, the logic output QB is inverted with a slight delay, and the output signal Y is inverted at a further delayed time t5. When the third clock is applied at time t6, the logic output QA is inverted with a slight delay, and at time t7, the output signal Y is delayed.
Is reversed. In this case, the logic inversion at time t5 and the logic inversion at time t7 appearing in the output signal Y are theoretically correct logic operations, but the glitch G at time t2 ′ is not a correct logic operation. Therefore, if the output signal Y is applied to the subsequent logic circuit as it is, the correct logic operation cannot be performed.

The flip-flop 50 has a function of removing the glitch G generated in this way. That is, the output signal Y of the logic circuit 100 is transferred to the flip-flop 5
0 to the input terminal D and the clock signal CLK to the clock terminal CK of the flip-flop 50. As described above, if the flip-flop 50 is connected to the subsequent stage of the logic circuit 100, the output signal Z shown in FIG. 2 is obtained at the output terminal 99. In this output signal Z, the glitch G is removed, but the logical output that should have been originally obtained at time t5 actually results at time t7, and the logical output is delayed by one cycle of the clock signal CLK. It will be.

A circuit for eliminating such a delay is shown in FIG. The circuit of FIG. 3 is obtained by adding a delay element 52 to the circuit of FIG. The clock signal provided to the clock terminal CK of the flip-flop 50 by the delay element 52 becomes the delayed clock signal DCLK as shown in the timing chart of FIG. The clock signal CLK rises at times t1, t4, and t6, while the delayed clock signal DCLK has rises at times t1d and t4, respectively.
It will rise at d and t6d. When the flip-flop 50 is operated with such a delay clock DCLK, the output signal Z obtained at the output terminal 99 becomes a signal shown in the bottom column of FIG. That is, originally at time t5
The logical output that should be obtained in step 1 is actually obtained at time t5d, and the delay is considerably eliminated as compared with the output signal Z shown in the bottom column of FIG.

However, such a conventional glitch removing circuit cannot be applied to a logic circuit using a plurality of systems of clocks as shown in FIG. 5 is the same as the logic circuit 100 shown in FIG. 1 or FIG.
The clock input terminals 13A and 13B are provided, and the flip-flop 20 has the first clock signal CLK.
-A, and the second flip-flop 30
The clock signal CLK-B of FIG. As described above, in the logic circuit using the clocks of a plurality of systems, the glitch removal cannot be performed by the conventional method. Further, even in the case of a logic circuit which uses one system of clock, when the two circuits are physically separated from each other due to the necessity of the bus configuration, a delay occurs in the clock signal. It becomes difficult to remove glitches by the method.

In the glitch removing circuit according to the present invention, the glitch can be removed without using the clock signal of the logic circuit. Therefore, the above case can be sufficiently dealt with. FIG. 6 is a block diagram showing the basic configuration of the glitch removing circuit according to the present invention. This glitch removing circuit is used by being connected to the subsequent stage of the logic circuit 100, similarly to the conventional circuit. That is, the change detection unit 200 that detects a change in the output logic state of the logic circuit 100 is connected to the subsequent stage of the logic circuit 100. The detection signal from the change detection unit 200 is given to the gate pulse generation unit 300, and here, a gate pulse is generated based on the change detection signal. On the other hand, the logic signal that has passed through the change detection unit 200 is further output to the output terminal 99 through the logic maintenance unit 400. At this time, the logic maintaining unit 400 has a function of maintaining the logic signal in the state before the gate pulse is generated while the gate pulse is generated. The pulse width of the generated gate pulse is set to be smaller than the logic operation cycle of the logic signal used in the logic circuit 100 and larger than the width of the glitch to be removed.

According to such a configuration, the logic circuit 100
When a change in the logical value occurs within the change, the change is detected by the change detection unit 2
00, and a gate pulse is generated in the gate pulse generator 300 based on this detection signal.
If the change in the logic value in the logic circuit 100 is due to the glitch, the pulse width of this glitch is smaller than the pulse width of the gate pulse, so the glitch is the logic maintaining unit 400.
It is blocked by and is not output to the output terminal 99. On the other hand, if the logic value change in the logic circuit 100 is due to a correct logic operation, the logic operation cycle due to this correct logic operation is larger than the pulse width of the gate pulse, and therefore this logic value change is caused by the logic maintaining unit. 400
It is output to the output terminal 99 without being blocked by.

In this embodiment, the change detecting section 200 is provided with a delay element 21 for delaying the output of the logic circuit 100 for a predetermined period.
0, and a comparison circuit 220 for comparing the logic state after the delay by the delay element 210 with the logic state before the delay. According to such a configuration, the comparison circuit 2
20 detects the difference between both inputs, the logic circuit 10
It is possible to detect that the output signal from 0 has changed.

FIG. 7 is a circuit diagram showing a more specific embodiment of the glitch removing circuit according to the present invention. In this embodiment, the logic circuit 100 is the same circuit as the conventional example described in FIG. 1 or FIG. 3, and the change detection unit 200, the gate pulse generation unit 300, and the logic maintenance unit 400 are provided in the subsequent stages.
Are connected. The change detector 200 includes the delay element 21.
1 and 212 and an XOR circuit 221. The gate pulse generator 300 is composed of a one-shot multivibrator including a D-type flip-flop circuit 310 and a delay element 320.
Further, the logic maintaining unit 400 is composed of a latch circuit 410. The output signal Y of the logic circuit 100 passes through the delay elements 211 and 212, is applied to the input terminal D of the latch circuit 410, and is output to the output terminal 99 as the logic output Q. The latch circuit 410 is normally (gate terminal G
When the logic of T is "1"), the signal given to the input terminal D is output as it is as the logic output Q, but when the gate pulse is given to the gate terminal GT (when the logic is "0"), It has a function of maintaining the logic output Q just before that. In other words, when the gate pulse is applied, the logic output Q is frozen as it is, and when the gate pulse disappears, the operation is released.

The gate pulse applied to the latch circuit 410 is generated as follows. First, the change detection unit 200 detects a change in the output signal Y of the logic circuit 100. That is, by the XOR circuit 221,
The signal DY1 delayed by the delay element 211 is compared with the signal Y before the delay, and the comparison output GY1 becomes the logic “1” only when the logic values of the two are different. The delay time of the delay element 211 is preferably set to be slightly longer than the time when the glitch is contained. The comparison output GY1 thus obtained is shaped in the gate pulse generator 300. The gate pulse generator 300, as described above,
This is a one-shot multivibrator including a D-type flip-flop circuit 310 and a delay element 320, and a comparison output GY1 has a logic "1" for a gate pulse having a predetermined pulse width set by the delay time of the delay element 320. It occurs when it becomes ". The change detection unit 20
The delay element 212 at 0 is the gate pulse generator 30
The logic signal DY1 is further delayed to obtain the logic signal DY2 in order to match the timing with the gate pulse generated by 0.

Next, the operation of the circuit shown in FIG. 7 will be described with reference to the timing chart shown in FIG. Now, consider the operation of logic circuit 100 when input signals A and B and clock signal CLK as shown in FIG. 8 are applied. Clock signals CLK rising at times t10, t20, and t30 are applied to flip-flops 20 and 30. As a result, each flip-flop performs a predetermined logical operation and outputs logical outputs QA and QB. Here, when the falling part of the input signal A is called edge J, the rising part is called edge K, the rising part of the input signal B is called edge L, and the falling part is called edge M, the clock signal given at time t10 is given. Due to the operation of both flip-flops based on CLK, the edge JA of the logic output QA and the edge LB of the logic output QB should be logically located at the same time. However, in reality, since there is a difference in operation time between both flip-flops, for example, the edge LB is slightly behind the edge JA. Therefore, in the output signal Y of the logic circuit 100, a glitch G0 having a time width corresponding to this delay time is generated. Further, the flip-flop 3 based on the clock signal CLK given at time t20
The operation of 0 forms the edge MB corresponding to the edge M in the logic output QB, and the operation of the flip-flop 20 based on the clock signal CLK given at time t30 causes the edge corresponding to the edge K in the logic output QA. KA is formed. Therefore, the output signal Y of the logic circuit 100 follows the glitch G0 as shown in FIG.
The signal has an edge M0 and an edge K0. Here, since the edge M0 and the edge K0 are edges that form a correct logic signal, the edges M0 and K0 may be output as they are, but the glitch G0 is not a correct logic signal and thus needs to be removed.

This glitch removal is performed by the circuit shown in the lower stage of the circuit diagram of FIG. First, the signal DY1 passed through the delay element 211 in the change detection unit 200 is the output signal Y of the logic circuit 100 delayed by a predetermined time, and the signal DY2 passed through the delay element 212 is the signal DY1.
Was delayed even further. Therefore, as shown in FIG. 8, the signal DY1 follows the glitch G1 and then the edge M1.
And the signal DY2 becomes a signal having an edge M2 and an edge K2 after the glitch G2. On the other hand, the output signal GY1 of the XOR circuit 221 is the exclusive OR of the signal Y and the signal DY1, and becomes a signal having glitches G0 'and G1' and pulses P2 and P3. Glitch G0 ', G
1'corresponds to the glitches G0 and G1, respectively, and the pulses P2 and P3 respectively correspond to the edges M0 and M1 and the edges K0 and K1 (both have a slight delay time). The one-shot multivibrator formed in the gate pulse generator 300 has a function of shaping the waveform of the signal GY1, and the waveform after shaping is the signal GY2.
And GY3. The signal GY3 is a signal including the gate pulses GP1 to GP3, and the latch circuit 410
Is applied to the gate terminal GT of. Gate pulse GP1
Is obtained by fusing and shaping the glitches G0 ′ and G1 ′, and the gate pulses GP2 and GP3 are obtained by shaping the pulses P2 and P3, respectively. As described above, these gate pulses GP1 to GP3 are
Pulse width is greater than the width of the glitch to be removed,
It is set to be shorter than the logic operation cycle of the logic signal used in the logic circuit 100. This will be specifically described with reference to the time chart of FIG. 8. The pulse widths of the gate pulses GP1 to GP3 may be set to be larger than the glitch G0 and smaller than the distance between the edges LM and the edges MK. This pulse width can be set by the delay time in the delay element 320. That is, the pulse widths of the gate pulses GP1 to GP3 can be controlled by the positions of the rising edges of the delay pulses D1, D2 and D3 on the delay signal GY4.

In the present specification, the leading edge (edge marked with an arrow in FIG. 8) of the gate pulses GP1 to GP3 thus obtained is called a rising edge, and the trailing edge is called a falling edge. That is, the rising edge and the falling edge of the “signal GY3” and the rising edge and the falling edge of the “gate pulses GP1 to GP3” are
It's just the opposite. With this definition, the function of the latch circuit 410 is "gate pulses GP1 to GP3.
The output signal Q is frozen to the logic state as it is at the rising time of the above, and the frozen state of the output signal Q is released at the falling time of the gate pulses GP1 to GP3. " In other words, the latch circuit 410 normally outputs the input signal DY2 as it is, but blocks the signal DY2 only while the gate pulse is being applied, and maintains the logic state immediately before the gate pulse is applied. Will be done. The hatched portion in the column labeled GATE in FIG. 8 corresponds to the just blocked period (there is a slight delay time with respect to the gate pulse). Therefore, the output signal Z output from the latch circuit 410 to the output terminal 99 has a waveform as shown in FIG. Since the glitch GZ is located in the block period, it is removed from the output signal Z, and the edge MZ corresponding to the original edge M and the edge KZ corresponding to the original edge K are respectively in the block period. It appears immediately after. Thus, only the edges MZ and KZ associated with the correct logic operation are valid in the output signal Z.

The present invention has been described above based on the illustrated embodiment, but the present invention is not limited to this embodiment and can be implemented in various modes other than this. For example, although the logic circuit 100 in the above-described embodiment uses the single clock signal CLK, the glitch removing apparatus according to the present invention does not need to use the clock of the logic circuit 100, so that a plurality of clock systems are used. It can also be applied to the existing logic circuit. Further, in the above-described embodiment, the circuit for removing the glitch generated based on the two signals having the time difference has been described, but the present invention can also remove the glitch generated based on the three or more signals. If the delay time of the delay element is set appropriately, the same can be applied.

[0021]

As described above, according to the glitch removing circuit of the logic circuit according to the present invention, the gate pulse is generated based on the change of the logic output of the logic circuit, and the gate pulse blocks the logic output for a predetermined period. Therefore, the glitch can be removed without using the clock signal.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an example of a conventional glitch removing circuit.

FIG. 2 is a time chart explaining the operation of the circuit shown in FIG.

FIG. 3 is a circuit diagram showing another example of a conventional glitch removing circuit.

FIG. 4 is a time chart explaining the operation of the circuit shown in FIG.

FIG. 5 is a circuit diagram showing an example of a logic circuit which cannot be handled by a conventional glitch removing circuit.

FIG. 6 is a block diagram showing a basic configuration of a glitch removing circuit according to the present invention.

FIG. 7 is a circuit diagram showing a more specific embodiment of the glitch removing circuit according to the present invention.

FIG. 8 is a time chart explaining the operation of the circuit shown in FIG.

[Explanation of symbols]

 11 to 13 ... Input terminals 20, 30 ... D-type flip-flop 40 ... OR circuit 50 ... D-type flip-flop 99 ... Output terminal 100 ... Logic circuit 200 ... Change detection unit 210 ... Delay element 211, 212 ... Delay element 220 ... Comparison Circuit 221 ... XOR circuit 300 ... Gate pulse generator 310 ... D-type flip-flop 320 ... Delay element 400 ... Logic maintaining unit 410 ... Latch circuit

Claims (3)

[Claims] 1. A circuit for removing glitches generated in a logic circuit, comprising: change detecting means for detecting a change in an output logic state of the logic circuit; and a period smaller than a logic operation cycle of a logic signal used in the logic circuit. A gate pulse generating means having a width larger than that of a glitch to be removed, and generating a rising gate pulse when the change detecting means detects a change, and while the gate pulse is generated, A glitch removing circuit for a logic circuit, comprising: a logic maintaining unit that maintains the output logic state of the logic circuit as it was before the gate pulse was generated. 2. The glitch elimination circuit according to claim 1, wherein the change detecting means delays the output of the logic circuit for a predetermined period, and the delay state and the logic state before and after the delay means. A glitch removing circuit of a logic circuit, characterized by comprising: 3. A glitch removing circuit for a logic circuit according to claim 1, wherein the gate pulse generating means is constituted by a one-shot multivibrator including a flip-flop circuit and a delay element.