CN106849914A - One kind keeps the accurate new structure of sequential logical circuit sequential - Google Patents
One kind keeps the accurate new structure of sequential logical circuit sequential Download PDFInfo
- Publication number
- CN106849914A CN106849914A CN201710148562.4A CN201710148562A CN106849914A CN 106849914 A CN106849914 A CN 106849914A CN 201710148562 A CN201710148562 A CN 201710148562A CN 106849914 A CN106849914 A CN 106849914A
- Authority
- CN
- China
- Prior art keywords
- sequential
- clock
- dff
- logical circuit
- new structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001934 delay Effects 0.000 claims description 3
- 102100038026 DNA fragmentation factor subunit alpha Human genes 0.000 description 24
- 101000950906 Homo sapiens DNA fragmentation factor subunit alpha Proteins 0.000 description 24
- 102100038023 DNA fragmentation factor subunit beta Human genes 0.000 description 11
- 101100277639 Homo sapiens DFFB gene Proteins 0.000 description 11
- 238000010586 diagram Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000001419 dependent effect Effects 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/037—Bistable circuits
Landscapes
- Logic Circuits (AREA)
Abstract
A kind of accurate new structure of sequential that can keep sequential logical circuit, it includes two and two or more d type flip flop, data input signal DATA is accessed from first data input pin of d type flip flop, and clock input signal CLOCK is accessed since last d type flip flop.Clock input signal enters line delay before each d type flip flop is entered with delayer or phase inverter.
Description
Technical field
The present invention relates to a kind of new structure of the sequential accuracy of holding sequential logical circuit, more particularly to a kind of D
The new structure of the sequential accuracy of the sequential logical circuit of trigger (DFF), belongs to integrated circuit fields.
Background technology
As shown in figure 1, sequential logical circuit, is mainly made up of storage circuit and combinational logic circuit two parts.Combination is patrolled
The characteristics of collecting circuit is the change that the change being input into directly reflects output, and state of its output is only dependent upon the current of input
State, the reset condition with input, output is unrelated.And sequential logical circuit is that a kind of output is not only relevant with current input,
And it is relevant with the reset condition of its output state, it is defeated that it adds a feedback equivalent to the input in combinational logic circuit
Enter, there is a storage circuit in its circuit, it can maintain the state of output.
The sequential disorder problem of sequential logical circuit can hereafter be made clear for convenience, existing state is first introduced herein
(Present state) and the concept of next state (Next state).
DFF is a kind of basic logic unit of common sequential logical circuit, using very wide, can be used as data signal and posts
Deposit, shift LD, frequency dividing and waveform generator etc., it has two stable states, i.e. " 0 " and " 1 ", makees in certain outer signals
Under, another stable state can be turned to from a stable state.
As shown in Fig. 2 being the sequential logical circuit for including (n+2) individual DFF.When the circuit works in the ideal situation
When, in the rising edge of clock input signal, the output signal in DFF0 enters into DFF1, and the output signal in DFF1 is entered into
DFF2, by that analogy, the output signal in DFFn is entered into DFF (n+1), and last DFF (n+1) could be exported correctly
Signal.But need to keep the accuracy of the sequence circuit, it is in fact extremely difficult, it is necessary to be known a priori by each single DFF
Data retention over time, clock input signal CLOCK reach time delay of each single DFF, so could reasonable arrangement
Circuit.But want reasonable arrangement circuit, be but it is extremely difficult, especially DFF it is a fairly large number of in the case of.Actual feelings
During condition, L0-Ln+1Distance certainly be more than L0-LnOr L0-Ln-1Distance, so may result in clock input signal CLOCK and arrive first
It is last so as to cause so as to the output signal for causing previous DFF cannot in time be input to next DFF up to previous DFF
One DFF (n+1) cannot export correct signal, and referred to as this phenomenon is the disorder of sequential logical circuit generation timing sequence here.
Of the same trade other people are more clearly understood that the sequential disorder problem that the present invention is referred to for convenience, herein with containing
2 sequential logical circuits of DFF illustrate difficulty of the invention.During existing state, the output state of DFF0 is " 0 ", and DFF1's is defeated
It is " 1 " to do well, and under theoretical case, during next state, the output state " 0 " of DFF0 is entered into DFF1.During actual conditions, due to
L0-L1The distance between it is more long, then clock input signal CLOCK first reaches L0, L is reached afterwards1.In the upper of clock input signal
Rise along when, due to clock input signal CLOCK reach DFF1 have delay, can cause DFF0 output state " 0 " have little time into
Enter DFF1, then data " 0 " in DFF0 can only be remained in DFF0, it is impossible to exported, and the input of the data input pin of DFF0 is believed
Number " 1 " then cannot be introduced into DFF0, can only be in being directly inputted to DFF1 after DFF0, so as to the DFF1 signals that result in final are defeated
Make mistake.
The online patent of Application No. CN201511026477.8 provides a kind of measurement electricity of data hold time of DFF
Road, its data input signal is passed through to be obtained after a phase inverter is reverse by clock input signal, and in the data input pin access of DFF
Delayer, it is different from the problem to be solved in the present invention, and delayer in the circuit has strict requirements, therefore the first patent should
When not influenceing novelty of the invention.
In order to solve the sequential disorder problem of sequential logical circuit of the above containing DFF, when the present invention provides a kind of holding
The accurate structure of sequential of sequence logic circuit.Using structure of the invention, during without the delay for being known a priori by each DFF in circuit
Between, without especially taking notice of that clock input signal enters into the time delay of each DFF, but but can guarantee that sequential logical circuit
Sequential it is normal, can never be disorderly.
The content of the invention
The present invention relates to a kind of accurate new structure of sequential of holding sequential logical circuit.
A kind of accurate new structure of sequential for keeping sequential logical circuit, it includes n DFF, it is each described in DFF when
Clock input connection clock input signal CLOCK, described clock input signal CLOCK are accessed since last DFF.
Further, data input signal DATA is connected with first DFF input.
Further, the reset clear terminal of each described DFF all connects reset reset signal.
Further, containing most (n-1) individual logic circuits 101 between n described DFF, n is >=2 natural number, most
Contain a logic circuit 101 less.
Further, described clock input signal CLOCK is existing in the absence of time delay from after last DFF accesses
As.
Further, described clock input signal CLOCK is from after last DFF accesses, if existence time postpones,
Clock signal CLOCK will be introduced into DFF (n-1), subsequently into DFF (n-2), subsequently into DFF (n-3), by that analogy, most
Enter DFF0 eventually.
Further, in order to ensure there is time delay phenomenon between each DFF, described kth is entered in clock input signal
Increase by least one delayer 102 before individual DFF；Further, k be 1 to (n-1) in any one value；Further,
K includes all values in 1 to (n-1).
Further, each delayer 102 can have identical time delay, it is possible to have different time delays.
Further, the time delay of each delayer>0, without considered critical scope.
Further, in order to ensure there is time delay phenomenon between each DFF, enter in clock input signal CLOCK
Increase p phase inverter 103 before k-th described DFF, further, p is 2 integral multiple；Further, k is 1 to (n-
1) any one in or several values；Further, k includes all values in 1 to (n-1).
Further, described phase inverter 103 causes that clock input signal occurs 180 degree reversion.
Further, described phase inverter 103 has certain time-lag action.
In order that those skilled in the art is better understood from present disclosure, come below with reference to specific implementation case
Illustrate thought of the invention.It should be understood that the specific embodiments described herein are merely illustrative of the present invention, it is not used to
Limit interest field of the invention.All any modifications made within the spirit and principles in the present invention, equal replacement and improvement
Deng being all contained within protection scope of the present invention.
Brief description of the drawings：
Fig. 1 is sequential logical circuit structure chart.
Fig. 2 is to contain the n common sequential logical circuit structure chart of DFF.
Fig. 3 is to contain 2 common sequential logical circuit structure charts of DFF.
Fig. 4 is a kind of schematic diagram of the accurate new structure of sequential of holding sequential logical circuit of the invention.
Fig. 5 is clock signal CLOCK by the signal output schematic diagram after a phase inverter 103.
Fig. 6 is the circuit structure diagram of embodiment of the present invention one.
Fig. 7 is the circuit structure diagram of embodiment of the present invention two.
Fig. 8 is the circuit structure diagram of embodiment of the present invention three.
Main element symbol description：
| Combinational logic circuit | 101 |
| Delayer | 102 |
| Reverser | 103 |
| D type flip flop | DFF |
Following specific embodiment will further illustrate the present invention with reference to above-mentioned accompanying drawing.
Specific implementation case 1：
As shown in fig. 6, including two DFF in sequential logical circuit of the invention, combinational logic electricity is contained between two DFF
Road 101.The input end of clock connection clock signal of DFF0 and DFF1, clock input signal CLOCK is input into since DFF1,
L0-L1Between be equipped with two phase inverters 103, L1Two phase inverters 103 are housed, the two phase inverters have certain time delay between-P
Effect.Data input signal DATA is accessed from DFF0 inputs.
Operation principle：When the sequential logical circuit in case study on implementation 1 works, data input signal DATA is input into from DFF0
Terminate into during existing state, the data-signal in DFF0 is " 0 ", and the data-signal in DFF1 is " 1 ".During next state, clock input signal
CLOCK is according to P-L1Track enter into DFF1 because P-L1Include two phase inverters, then clock signal is by reverse twice
Afterwards, the delay input of time is only completed, but signal will not change.Then data-signal " 0 ", in DFF0 enters DFF1
In, the data-signal " 1 " in DFF1 completes final output.Then clock input signal CLOCK is according to L1-L0Track enter
To DFF0, because the data-signal in DFF0 has been excluded, then data input signal DATA
DFF0 can smoothly be entered, sequential will not get muddled.
Specific implementation case 2：
As shown in fig. 7, sequential logical circuit of the invention includes three DFF, two combinational logics are contained between three DFF
Circuit 101.The input end of clock connection clock signal of DFF0, DFF1 and DFF2, clock input signal CLOCK is defeated since DFF2
Enter, in L0-L1Between be equipped with a delayer 102, in L1-L2Between two phase inverters 103 are housed, the two phase inverters have one
Fixed time-lag action.Data input signal DATA is accessed from DFF0 inputs.
Operation principle：When the sequential logical circuit in case study on implementation 2 works, data input signal DATA is input into from DFF0
Terminate into during existing state, the data-signal in DFF0 is " 0 ", and the data-signal in DFF1 is " 1 ", and the data-signal in DFF2 is
“0”.During next state, clock input signal CLOCK is according to P-L2Track be introduced into DFF2, then data-signal " 1 " in DFF1
Enter into DFF2, the data-signal " 0 " in DFF2 completes final output.Due to L2-L1Between two time delays of phase inverter
Effect, clock signal CLOCK is according to L2-L1Track enter into DFF1, because the data-signal in DFF1 is discharged in time,
Data-signal " 0 " then in DFF0 can smoothly enter DFF1.
Due to L1-L0Between have a delayer, then clock signal CLOCK is according to L1-L0Track enter enter finally into
During DFF0, because the data-signal " 0 " in DFF0 is discharged in time, then can smoothly to receive data input pin DATA defeated for DFF0
The signal for entering, sequential will not get muddled.
Specific implementation case 3：
As shown in figure 8, sequential logical circuit of the invention includes four DFF, three combinational logics are contained between four DFF
Circuit 101.The input end of clock connection clock signal of DFF0, DFF1, DFF2 and DFF3, clock input signal CLOCK is from DFF3
Start input, in L0-L1Between be equipped with a delayer 102, in L1-L2Between be equipped with a delayer 102, in L3Filled between-P
There is a delayer 102.Data input signal DATA is accessed from DFF0 inputs.
Operation principle：When the sequential logical circuit in case study on implementation 3 works, data input signal DATA is input into from DFF0
Terminate into during existing state, the data-signal in DFF0 is " 0 ", and the data-signal in DFF1 is " 1 ", and the data-signal in DFF2 is
" 0 ", the data-signal in DFF3 is " 1 ".Due to L0-L1、L1-L2And L3- P respectively has a delayer, then clock input signal
CLOCK can preferentially enter DFF3 and DFF2, subsequently into DFF1, finally enter DFF0.In this case, during next state, DFF2
Exported simultaneously with the data-signal in DFF3, will not generation timing sequence disorder.And DFF1 and DFF0 are also because clock input signal enters
There is delay the time for entering, disorderly without generation timing sequence.
Embodiment described above only expresses several embodiments of the invention, and its description is more specific and detailed, but simultaneously
Therefore the limitation to the scope of the claims of the present invention can not be interpreted as.It should be pointed out that for one of ordinary skill in the art
For, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to guarantor of the invention
Shield scope.Therefore, the protection domain of patent of the present invention should be determined by the appended claims.
Claims (9)
1. a kind of accurate new structure of sequential for keeping sequential logical circuit, its feature includes：N d type flip flop, it is each described
The input end of clock connection clock signal CLOCK of d type flip flop, described clock input signal CLOCK are from last d type flip flop
Start to access, data-signal DATA is accessed from first d type flip flop.
2. the accurate new structure of sequential of sequential logical circuit is kept as claimed in claim 1, it is characterised in that：Described
Containing up to (n-1) individual logic circuit between each d type flip flop, n is >=2 natural number, at least include a logic circuit.
3. the accurate new structure of sequential of sequential logical circuit is kept as claimed in claim 1, it is characterised in that：Clock is defeated
Enter signal CLOCK from after last DFF accesses, in the absence of time delay phenomenon.
4. the accurate new structure of sequential of sequential logical circuit is kept as claimed in claim 1, it is characterised in that：Described
After clock input signal CLOCK is accessed from last DFF, existence time delay phenomenon, then clock signal CLOCK will be advanced
Enter DFF (n-1), subsequently into DFF (n-2), subsequently into DFF (n-3), by that analogy, eventually enter into DFF0.
5. the accurate new structure of sequential of sequential logical circuit is kept as claimed in claim 4, it is characterised in that：In order to protect
There is time delay phenomenon between each described DFF of card, at least one is increased before clock input signal enters k-th described DFF
Individual delayer；Preferably, k be 1 to (n-1) in any one value；It is further preferred that k includes owning in 1 to (n-1)
Value.
6. the accurate new structure of sequential of sequential logical circuit is kept as claimed in claim 5, it is characterised in that：Described
Each delayer can have identical time delay, it is possible to have different time delays.
7. the accurate new structure of sequential of sequential logical circuit is kept as claimed in claim 5, it is characterised in that：Described
The time delay of each delayer>0, without considered critical scope.
8. the accurate new structure of sequential of sequential logical circuit is kept as claimed in claim 4, it is characterised in that：In order to protect
There is time delay phenomenon between the described each DFF of card, increase p is anti-phase before clock input signal enters k-th described DFF
Device, p is 2 integral multiple；K is any one or several values in 1 to (n-1).
9. the accurate new structure of sequential of sequential logical circuit is kept as claimed in claim 8, it is characterised in that：Described
Phase inverter causes that clock signal occurs 180 degree and inverts.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710148562.4A CN106849914A (en) | 2017-03-14 | 2017-03-14 | One kind keeps the accurate new structure of sequential logical circuit sequential |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710148562.4A CN106849914A (en) | 2017-03-14 | 2017-03-14 | One kind keeps the accurate new structure of sequential logical circuit sequential |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106849914A true CN106849914A (en) | 2017-06-13 |
Family
ID=59144373
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710148562.4A Pending CN106849914A (en) | 2017-03-14 | 2017-03-14 | One kind keeps the accurate new structure of sequential logical circuit sequential |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106849914A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109801663A (en) * | 2019-01-11 | 2019-05-24 | 广州华欣电子科技有限公司 | Shift-register circuit, circuit board, infrared touch frame and infrared touch device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101303709A (en) * | 2008-06-30 | 2008-11-12 | 北京中星微电子有限公司 | Simulation control method and system for programmable logic device |
| CN101320966A (en) * | 2007-06-05 | 2008-12-10 | 恩益禧电子股份有限公司 | Delay circuit |
-
2017
- 2017-03-14 CN CN201710148562.4A patent/CN106849914A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101320966A (en) * | 2007-06-05 | 2008-12-10 | 恩益禧电子股份有限公司 | Delay circuit |
| CN101303709A (en) * | 2008-06-30 | 2008-11-12 | 北京中星微电子有限公司 | Simulation control method and system for programmable logic device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109801663A (en) * | 2019-01-11 | 2019-05-24 | 广州华欣电子科技有限公司 | Shift-register circuit, circuit board, infrared touch frame and infrared touch device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101515796B (en) | Digital signal noise filtering device | |
| US8278979B2 (en) | Digital circuits with adaptive resistance to single event upset | |
| US9222971B2 (en) | Functional path failure monitor | |
| US10644683B2 (en) | Clock driving circuit resistant to single-event transient | |
| CN105553447B (en) | Clock switch circuit | |
| CN107342762B (en) | A kind of anti-single particle transient state clock tree construction | |
| CN103208994A (en) | Two-stage time digital convert (TDC) circuit | |
| CN102970013A (en) | Resetting method and resetting control device of register inside chip based on scanning chain | |
| CN104617925A (en) | Latch circuit | |
| CN107562163B (en) | Digital logic circuit with stable reset control | |
| CN109039307A (en) | It is double along Anti-shaking circuit structure | |
| EP3001562B1 (en) | Fault resistant flip-flop | |
| CN103812472B (en) | The triggering device of anti-single particle transient state effect | |
| CN109660247A (en) | Sequential control system and sequential control method in piece between voltage regulator | |
| CN107565936B (en) | Logic implementation device of input clock stabilizing circuit | |
| CN106849914A (en) | One kind keeps the accurate new structure of sequential logical circuit sequential | |
| CN106026982B (en) | A kind of monostable flipflop | |
| CN208272950U (en) | A kind of accurate new structure of holding sequential logical circuit timing | |
| CN208128214U (en) | multi-mode POR circuit for FPGA | |
| CN106484364A (en) | Randomizer based on transition effect ring oscillator | |
| CN108832918A (en) | A kind of radioresistance trigger circuit detected based on transmission gate and SET | |
| CN104579246B (en) | A kind of dutyfactor adjustment circuit | |
| CN103391072B (en) | Be used for detect clock pulse shake testing circuit | |
| CN107425841B (en) | A kind of timing error detection unit based on jump error check structure | |
| CN208707607U (en) | A kind of radioresistance trigger circuit detected based on transmission gate and SET |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20170613 |
|
| RJ01 | Rejection of invention patent application after publication |