Embodiment
Now will with reference to exemplary embodiment the present invention be described here.But those skilled in the art should be understood that the instruction of the application of the invention and realizes many interchangeable embodiment, and the embodiment that the invention is not restricted to illustrate for task of explanation.
First embodiment
Explain embodiments of the invention hereinafter with reference to accompanying drawing.Fig. 1 is the block diagram that has shown according to the delay circuit 100 of the first embodiment of the present invention.As shown in Figure 1, the delay circuit 100 according to present embodiment comprises that reference pulse produces circuit 10, counter 20, inhibit signal output circuit 30 and reset signal output circuit 40.
Reference pulse produces circuit 10 and has feedback circuit 11, and this feedback circuit 11 comprises the decay part that is used for determining the time interval between the reference pulse, and produces the reference pulse sequence in response to input signal.Feedback circuit 11 is by using signal based on the delay pulse sequence that produces at decay part, carry out calculating based on the signal and the input signal that produce from inhibit signal output circuit 30 (the explaining after a while) inhibit signal of output in the process that produces reference pulse, and result of calculation is provided to decay part.Counter 20 receives by reference pulse and produces reference pulse sequence that circuit 10 produces as reference clock, and based on the output count signal of this reference clock.Inhibit signal output circuit 30 produces also output delay signal based on input signal with from the count signal that counter 20 is exported.The reset signal that reset signal output circuit 40 will produce based on the inhibit signal of exporting from inhibit signal output circuit 30 outputs to counter 20.The following details of explaining each parts with reference to Fig. 1.
Reference pulse produces circuit 10 and has feedback circuit 11, rising single-shot trigger circuit 4 and decline single-shot trigger circuit 5.And feedback circuit 11 is made of inverter INV, NAND (with non-) circuit 1, counting circuit (hereinafter referred to as " AND (with) circuit ") 2 and decay part (hereinafter referred to as " rise edge delay circuit ") 3.
Inverter INV will be from the level inversion of the inhibit signal OUT of inhibit signal output circuit 30 (after a while explain) output, and consequential signal is outputed to NAND circuit 1.NAND circuit 1 calculate and output from the signal DS of rising single-shot trigger circuit 4 outputs and long-pending from the inverted logic of the inverse delayed signal OUT of inverter INV.Counting circuit 2 calculates input signal IN and from the logic product of the signal of NAND circuit 1 output, and output result signal is as input pulse sequence (hereinafter referred to as " signal DIN ").Rise edge delay circuit 3 produces and output delay pulse trains (hereinafter referred to as " signal DOUT "), and the rising edge of this delay pulse sequence is delayed from the rising edge from the signal DIN of counting circuit 2 outputs.
Rising single-shot trigger circuit 4 produces signal DS, and this signal DS rises synchronously with the rising edge of the signal DOUT that exports from rise edge delay circuit 3, and has predetermined pulse duration.This signal DS is input to NAND circuit 1 and decline single-shot trigger circuit 5.Decline single-shot trigger circuit 5 produces signal DSB, and the trailing edge of this signal DSB and signal DS rises synchronously, and has predetermined pulse duration.
Incidentally, although will be input to NAND circuit 1 by the signal DS that rising single-shot trigger circuit 4 produces in the present embodiment,, in other embodiments, can be with signal DOUT or the signal DSB that produces by rise edge delay circuit 3, rather than signal DS, be input to NAND circuit 1.In addition, in the present embodiment, to be input to counter 20 (explaining after a while) with the corresponding signal DSB of reference pulse sequence that decline single-shot trigger circuit 5 produces as reference clock, at other embodiment, can be with signal DOUT that produces by rise edge delay circuit 3 or the signal DS that produces by rising single-shot trigger circuit 4, rather than signal DSB, be input to counter 20 as reference clock.
Counter 20 has D type circuits for triggering DFF1-DFF3.The identical value of input value that D type circuits for triggering output is imported during as reference clock with the signal DSB that exports from decline single-shot trigger circuit 5 in input.Be input to the input end of clock CK of each D type circuits for triggering DFF1-DFF3 (being designated hereinafter simply as " dff circuit ") by the signal DSB of decline single-shot trigger circuit 5 generations.Continue to provide " height " level signal to the input D of dff circuit DFF1.In addition, the output Q of dff circuit DFF1 is connected to the input D of dff circuit DFF2, and the output Q of dff circuit DFF2 is connected to the input D of dff circuit DFF3.In addition, count signal D1-D3 is output from each output of dff circuit DFF1-DFF3, and is imported into inhibit signal output circuit 30 (explaining after a while).In addition, the output of reset signal output circuit 40 (explaining after a while) is connected to the R that resets of each dff circuit DFF1-DFF3.
Inhibit signal output circuit 30 is made of AND circuit 6.AND circuit 6 calculates input signal IN and from the logic product of the count signal D1-D3 of dff circuit DFF1-DFF3 output, and output result signal is as inhibit signal OUT.
Reset signal output circuit 40 have decline single-shot trigger circuit 7 and OR (or) circuit OR.Decline single-shot trigger circuit 7 outputs to OR circuit OR with pulse signal, and this pulse signal rises synchronously with trailing edge from the signal of AND circuit 6 output and has predetermined pulse duration.OR circuit OR calculate the signal that provides at reset terminal RT and from the logic of the signal of decline single-shot trigger circuit 7 outputs and, and consequential signal outputed to the R that resets of dff circuit DFF1-DFF3 as reset signal.
Fig. 2 is the sequential chart that has shown the waveform of each point in the delay circuit 100 that shows in Fig. 1.Explain operation in detail hereinafter with reference to Fig. 1 and Fig. 2 according to the delay circuit 100 of present embodiment.
Explain that at first, below reference pulse produces the operation of circuit 10.When delay circuit 100 begins to operate, be input to NAND circuit 1 from " height " level signal of inverter INV with from the signal DS that is in " low " level of rising single-shot trigger circuit 4 outputs, wherein this inverter INV inhibit signal OUT that will be in " low " level is inverted into " height " level.Thereby, NAND circuit 1 output " height " level signal.Therefore, when the input signal IN that is in " height " level was input to counting circuit 2, the signal DIN that counting circuit 2 will be in " height " level outputed to rise edge delay circuit 3 (referring to the t1 among Fig. 2).
Rise edge delay circuit 3 output signal DOUT, the rising edge of this signal DOUT is delayed (referring to the t2 Fig. 2) from the rising edge of the signal DIN of input.The time interval between the reference pulse that the amount of this delay is determined to be produced by rise edge delay circuit 3.The signal DOUT that is in " height " level is input to rising single-shot trigger circuit 4.Rising single-shot trigger circuit 4 produces signal DS, this signal DS and rising edge from the signal DOUT of rise edge delay circuit 3 outputs rise synchronously (referring to the t2 Fig. 2).
The signal DS that is in " height " level is input to NAND circuit 1.That is, be in the signal DS of " height " level and be input to NAND circuit 1 by the inverse delayed signal OUT that inverter INV is inverted into " height " level.Thereby NAND circuit 1 outputs to counting circuit 2 with " low " level signal.Therefore, begin after the internal circuit by NAND circuit 1 and counting circuit 2 postpones caused delay from the rising edge of signal DS, signal DIN becomes " low " level (referring to t2 among Fig. 2 and t3).Then, from the signal DOUT of rise edge delay circuit 3 output and the input signal DIN that is in " low " level descend synchronously (referring to the t3 Fig. 2).
Then, the signal DS that is in " height " level becomes " low " level (referring to the t4 among Fig. 2) after the preset time section.This signal DS that is in " low " level is input to NAND circuit 1.That is, be in this signal DS of " low " level and be input to NAND circuit 1 by the inverse delayed signal OUT that inverter INV is inverted into " height " level.Thereby NAND circuit 1 outputs to counting circuit 2 with " height " level signal.Therefore, begin after the internal circuit by NAND circuit 1 and counting circuit 2 postpones caused delay from the trailing edge of signal DS, counting circuit 2 outputs are in the signal DIN (referring to the t5 among Fig. 2) of " height " level.Then, when the signal DIN that is in " height " level is input to rise edge delay circuit 3, rise edge delay circuit 3 output signal DOUT, the rising edge of this signal DOUT is delayed (referring to the t6 Fig. 2) from the rising edge of input signal DIN.Rising single-shot trigger circuit 4 produces and the synchronous signal DS that rises of the rising edge of inhibit signal DOUT.
Decline single-shot trigger circuit 5 output signal DSB, this signal DSB rises synchronously with the trailing edge of the signal DS that is produced by rising single-shot trigger circuit 4, and descends after the preset time section.As mentioned above, the signal DSB that is produced by decline single-shot trigger circuit 5 is input to the input end of clock CK of each dff circuit DFF1-DFF3 as reference clock.
Reference pulse produces circuit 10 can produce the reference pulse sequence by repeating these actions.In addition, the interval of determining between the reference pulse by rise edge delay circuit 3.That is, the signal DOUT that is produced by rise edge delay circuit 3 is big more apart from the retardation of signal DIN, and it is long more that the interval between the reference pulse becomes.When the time interval between the reference pulse became longer, because be delayed from the output timing of the count signal of counter (after a while explain) output, delay circuit 100 can be exported the inhibit signal OUT that bigger delay is arranged apart from input signal IN.
Then, below explain the operation of counter 20.Continue to provide " height " level signal to the input D of dff circuit DFF1.Therefore, in the time will being input to input end of clock CK from the signal DSB of decline single-shot trigger circuit 5 outputs, dff circuit DFF1 exports the count signal D1 (referring to the t4 Fig. 2) that is in " height " level from output Q.The count signal D1 that is in " height " level is input to the input D of dff circuit DFF2.Therefore, when signal DSB was input to input end of clock CK, dff circuit DFF2 exported the count signal D2 (referring to the t7 Fig. 2) that is in " height " level from output Q.
The count signal D2 that is in " height " level is input to the input D of dff circuit DFF3.Therefore, when signal DSB was input to input end of clock CK, dff circuit DFF3 exported the count signal D3 (referring to the t8 Fig. 2) that is in " height " level from output Q.
Then, below explain the operation of inhibit signal output circuit 30.Be input to AND circuit 6 from the count signal D1-D3 of dff circuit DFF1-DFF3 output.That is, input signal IN and count signal D1-D3 are input to AND circuit 6.AND circuit 6 calculates the logic product of the signal of input, and produces inhibit signal OUT.Therefore, AND circuit 6 output delay signal OUT, the rising edge of this inhibit signal OUT and count signal D3 rise synchronously and with the trailing edge of input signal IN descend synchronously (referring to the t8-t9 among Fig. 2).By this way, delay circuit 100 can output delay signal OUT, and the rising edge of this inhibit signal OUT is delayed (referring to the t1-t8 Fig. 2) from the rising edge of input signal IN.Notice that count signal D1-D3 that will be not all is input to AND circuit 6, but can separately count signal D3 be input to AND circuit 6.
Then, inhibit signal OUT is input to the decline single-shot trigger circuit 7 in the reset signal output circuit 40.The trailing edge of the output of decline single-shot trigger circuit and inhibit signal OUT rises synchronously.Be input to OR circuit OR from " height " level signal that is in of decline single-shot trigger circuit output.Therefore, OR circuit OR outputs to reset signal the reset terminal RT of each dff circuit DFF1-DFF3.Based on the input of this reset signal dff circuit DFF1-DFF3 that resets.In addition, also can for example, produce reset signal by reset signal output circuit 40 by providing " height " level signal at reset signal input RT.
As mentioned above, in the present embodiment, rise edge delay circuit 3 produces signal OUT, and the rising edge of this signal OUT is delayed from the rising edge of signal DIN, and this signal DIN produces based on input signal IN with from the input of the signal of NAND circuit 1 output.Then, the signal DSB that produces in response to this signal DOUT is input to circuits for triggering in the counter 20 as the operation of reference clock signal with control counter 20.Circuits for triggering output count signal D1-D3, when signal DSB is input to input end of clock CK as reference clock, this count signal D1-D3 will become " height " level state.Inhibit signal output circuit 30 can be by calculating the logic product output delay signal OUT of described count signal D1-D3 and input signal IN, and the transformation (transition) of this inhibit signal OUT is from the transformation delay of input signal IN.Promptly, in the present embodiment, the reference pulse sequence that is produced circuit 10 generations by reference pulse is input to counter as reference clock, thereby delay circuit 100 can output delay signal OUT, the transformation of this inhibit signal OUT is from the transformation delay of input signal IN, and this reference pulse produces circuit 10 and comprises the rise edge delay circuit 3 of determining the time interval between the reference pulse.In addition, by feeding back to feedback circuit 11, can produce time of delay of 3 times (quantity of circuits for triggering) of the time of delay of single rising delay circuit 3 by the signal DS that rising single-shot trigger circuit 4 produces.In addition, although counter 20 is made of three circuits for triggering in the present embodiment, in other embodiments, also can increase time of delay by the quantity that increases circuits for triggering.
In addition, owing to have single rise edge delay circuit 3 according to the delay circuit 100 of present embodiment, unit delay time does not promptly change the time of delay of each rise edge delay circuit.Therefore, can reduce the final delay temporal differences.
In addition, when big time of delay of needs, delay circuit of the prior art produces delay by connecting some rise edge delay circuit.Therefore, need to be used for the big layout area of delay circuit in the prior art, thereby increased die size.Simultaneously, according to the delay circuit 100 of present embodiment can enough single rise edge delay circuit 3 produce be a delay circuit time of delay several times time of delay.Thereby, can reduce layout area.In addition, according to the delay circuit 100 of present embodiment can enough single rise edge delay circuit produce expectation time of delay (that is, be a delay circuit time of delay N doubly).Thereby, can be at t1 of the prior art shown in Figure 5 between the t2, or t3 is to setting up cut-off state between the t4 really.Therefore, for example, when delay circuit 100 is connected to the CMOS transistor, can set up cut-off state really, during this cut-off state, the two is cut-off state simultaneously for PMOS transistor and nmos pass transistor.Therefore, can prevent that really electric current from flowing to earth potential from power supply potential, otherwise when PMOS transistor and nmos pass transistor became conducting state simultaneously, this electric current may occur.
In addition, the through current of the prior art that shows at Fig. 8 prevents in the circuit 80, controls the operation (referring to Fig. 8) of interconnective some triggers based on the clock signal that is input to input end of clock CK.Therefore, current preventing circuit 80 of the prior art needs external clock to produce circuit is input to input end of clock CK with generation clock signal.Simultaneously, in the present embodiment, the reference pulse sequence that produces in inside in response to input signal IN is used as reference clock.Therefore, therefore delay circuit 100, does not need external clock to produce circuit without any need for external timing signal.
In addition, reset signal output circuit 40 is forwarded to the reset terminal of each dff circuit with reset signal, and this reset signal produces synchronously with trailing edge from the inhibit signal OUT of inhibit signal output circuit 30.Therefore, can change over moment of " low " level state from " height " level state at inhibit signal OUT, a plurality of circuits for triggering in the reset counter.In addition, also may be for example by " height " level signal dff circuit that resets is provided to reset signal input RT.
Second embodiment
Fig. 3 is the block diagram that has shown delay circuit 200 according to a second embodiment of the present invention.Incidentally, in Fig. 3, with identical allocation of symbols give with Fig. 1 in parts parts and the structure identical with structure, and omit their detailed explanation.In first embodiment, counter 20 is made of dff circuit DFF1-DFF3.Relative therewith, in the delay circuit 200 of present embodiment, counter 50 is made of a plurality of dff circuit DFF1-DFFn (n is the integer greater than 1).In addition, delay circuit 200 comprises the selector 8 that is connected between counter 50 and the inhibit signal output circuit 30, and the counter 20 in the delay circuit 100 of this counter 50 and first embodiment is corresponding.Note, except the structure and operation of counter 50 and the new selector 8 that adds, according to the structure of the delay circuit 200 of present embodiment and operation with according to the structure of the delay circuit 100 of first embodiment with operate identical.Therefore, only explain the structure and the operation of counter 50 and the new selector 8 that adds below.
Counter 50 is made of a plurality of dff circuit DFF1-DFFn.The signal DSB that is produced by decline single-shot trigger circuit 5 is input among the dff circuit DFF1-DFFn each as reference clock.Continue to provide " height " level signal to the input D of dff circuit DFF1.In addition, the output Q of dff circuit DFF1 is connected to the input D of dff circuit DFF2, and the output Q of dff circuit DFF2 is connected to the input D of dff circuit DFF3.And the output Q of dff circuit DFF (n-1) is connected to the input D of dff circuit DFFn.In addition, with count signal D1-Dn from dff circuit DFF1-DFFn each output Q output to selector 8.In addition, the output of reset signal output circuit 40 is connected to the R that resets of each dff circuit DFF1-DFFn.
Selector 8 receives from the count signal D1-Dn of a plurality of dff circuit DFF1-DFFn outputs.And selector 8 is selected a count signal based on the selection signal that offers selector 8 from count signal D1-Dn, and it is outputed to inhibit signal output circuit 30.By this way, delay circuit 200 can output delay signal OUT, and the rising edge of this inhibit signal OUT is delayed from the rising edge of input signal IN.
As mentioned above, in the present embodiment, selector 8 is arranged between the counter 50 and inhibit signal output circuit 30 that is made of a plurality of dff circuit DFF1-DFFn.Then, selector 8 is selected a count signal based on the selection signal from count signal D1-Dn, and it is outputed to inhibit signal output circuit 30.Therefore, inhibit signal output circuit 30 can be by calculating input signal IN and producing inhibit signal OUT by the logic product of selector 8 selected count signals.That is, in the delay circuit 200 according to present embodiment, although use single rise edge delay circuit, amount can be selected from and arrive n doubly 1 of original time of delay time of delay.
In addition, because based on the selection signal that is applied to selector 8, delay circuit 200 can produce the time of delay of expectation, thus do not need to change circuit design, and have the flexibility of height at design aspect.In addition, can for example pass through serial line interface, externally set up this selection signal.Therefore, this has allowed to set up from the outside of device the time of delay of expectation.
Obviously, the invention is not restricted to above embodiment, but can under situation about not departing from the scope of the present invention with spirit, revise and change.For example, although produce the reference pulse sequence from rise edge delay circuit 3 in the present embodiment, in other embodiments, can use its trailing edge to produce the reference pulse sequence from the trailing edge delay circuit of the signal DIN delay of input.