CN111092611A - Signal processing device and method with small edge slope - Google Patents
Signal processing device and method with small edge slope Download PDFInfo
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- CN111092611A CN111092611A CN201911131181.0A CN201911131181A CN111092611A CN 111092611 A CN111092611 A CN 111092611A CN 201911131181 A CN201911131181 A CN 201911131181A CN 111092611 A CN111092611 A CN 111092611A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/12—Shaping pulses by steepening leading or trailing edges
Abstract
The invention provides a signal processing device with small slope, comprising: the input end of the frequency doubling module receives a clock signal and doubles the frequency of the clock signal; the clock end of the register module is connected with the output end of the frequency doubling module, and the register module receives a first signal input in series and then outputs a second signal in parallel; and the input end of the gate circuit is connected with the output end of the register module, and the gate circuit is used for carrying out logic operation on the second signals output in parallel to obtain third signals. The device of the invention multiplies the frequency of a clock clk, for example, the frequency of a main clock of a calculation frequency meter is multiplied when the frequency is measured, then the frequency multiplication clock is multiplexed to sample and shift and register the input signal, and then gate circuit processing is carried out to obtain a third signal. The number of edges is counted after the third signal is obtained by the device, so that the influence of small noise is avoided when the signal with too slow level turnover is processed, and the processing result is more accurate.
Description
Technical Field
The invention relates to the field of signal processing, in particular to a signal processing device and method with small edge slope.
Background
The signal input has a problem of noise tolerance, and for a signal with a large edge slope, that is, a signal that completes a rising or falling process within one clock cycle, even if the sampling time of the signal is in the rising/falling process, the time judgment result may be a low level or a high level, but there is no influence on the counting result of the rising/falling edges because the time for the signal to keep the low/high level before and after the rising/falling is necessarily more than one clock cycle.
If the input signal level is inverted too slowly, i.e. the slope of the edge is too small, even if the input voltage noise is small, the judgment of the edge may be mistaken, which may result in inaccurate rising/falling times of the calculated signal. That is, in the case of only one rising edge (or falling edge), the processing result of the FPGA becomes more than one edge, thereby affecting the final result. For example, in practical applications, when the frequency is measured by using a method of counting rising edges by using a logic chip, the number of rising/falling times is not accurately calculated.
Disclosure of Invention
In view of the above, the present invention has been made to provide a signal processing apparatus and method with a small slope, which overcome or at least partially solve the above problems.
According to an aspect of the present invention, there is provided a signal processing apparatus having a small slope, including:
the input end of the frequency doubling module receives a clock signal and doubles the frequency of the clock signal;
the clock end of the register module is connected with the output end of the frequency doubling module, and the register module receives a first signal input in series and then outputs a second signal in parallel;
the input end of the gate circuit is connected with the output end of the register module, and the gate circuit is used for carrying out logic operation on the second signals output in parallel to obtain third signals.
Preferably, the register module is a shift register.
Preferably, the shift register comprises a plurality of flip-flops connected in series, and the number of the flip-flops is consistent with the frequency multiplication number of the frequency multiplication module.
Preferably, the gate circuit is at least an or gate circuit or an and gate circuit.
Preferably, the output end of each flip-flop is connected to the input end of the gate circuit, the output end of the flip-flop located at the previous stage is connected to the input end of the flip-flop located at the subsequent stage, and the output end of the frequency doubling module is connected to the clock end of each flip-flop.
According to an aspect of the present invention, there is provided a signal processing method with a small slope, including:
receiving a clock signal and multiplying the clock signal;
receiving a first signal input in series according to the frequency-multiplied clock signal and then outputting a second signal in parallel;
and carrying out logic operation on the second signals output in parallel to obtain third signals.
Preferably, the frequency multiplication factor for the clock signal is identical to the number of bits of the second signal output in parallel.
Preferably, the logic operation on the second signal at least includes: an or operation or an and operation.
Preferably, the shift register is used for receiving the first signal input in series and then outputting the second signal in parallel.
Preferably, when each bit of the second signal output in parallel is at a high level, the signal to be detected is at a high level, otherwise, the signal to be detected is at a low level; and when each bit of the second signals output in parallel is at a low level, the signal to be detected is at a low level, otherwise, the signal to be detected is at a high level.
The clock frequency clk is multiplied by the processing device and the processing method, then the input first signal is sampled by multiplexing the multiplied clock, and then the gate circuit processing is carried out. By counting the number of edges after the device provided by the embodiment of the invention is used, the signal with too slow level turnover is processed without being influenced by small noise, so that the processing result is more accurate.
The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic diagram of a signal processing apparatus with a small slope according to an embodiment of the present invention;
FIG. 2 is a flow chart of a method for processing a signal with a small slope according to an embodiment of the present invention;
FIG. 3 is a timing diagram of a first signal during a rise with a clock signal;
FIG. 4 is a schematic diagram of signal output without being processed by the signal processing apparatus according to the embodiment of the present invention;
fig. 5 is a schematic diagram of a signal output processed by the signal processing apparatus according to the embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
An embodiment of the present invention provides a signal processing apparatus with a small slope, as shown in fig. 1, including:
and the input end of the frequency doubling module 10 receives a clock signal and doubles the frequency of the clock signal.
Wherein the counting is more accurate when the frequency multiplication rate is larger. However, in actual operation, the specific frequency multiplication is determined according to noise conditions that may occur in a use scene in actual application, a degree of small slope of a signal to be measured, performance of the FPGA chip for determining high and low levels, cost, and the like. For example, the frequency multiplication factor is 4, and the input frequency is 50Mhz, the main frequency of the clock signal can be multiplied to 200Mhz through the frequency multiplication module 10.
The clock end of the register module 20 is connected with the output end of the frequency doubling module, and the register module receives a first signal input in series and then outputs a second signal in parallel; specifically, when the first signal is in the analog signal phase, the slope of the edge is too small for some reason, that is, the slope of the rising edge or the falling edge of the signal is small, the apparatus according to the embodiment of the present invention is directed to such a signal, and if the first signal is directly measured without passing through the apparatus according to the embodiment of the present invention, the subsequent trigger may be triggered by mistake. The main function of the register module is to make the first signal input in series output in parallel for the subsequent logic operation.
A gate circuit 30, an input end of which is connected to an output end of the register module to perform a logic operation on the second signal output in parallel to obtain a third signal. . Specifically, the gate 30 is used to perform a logic operation on the output of the register module 20, and the number of input terminals thereof matches the number of output terminals of the register module. After the logical operation of the gate circuit, the number of the third signal counting edges can obtain a correct counting result. Wherein the number of edges may comprise the number of rising edges or the number of falling edges.
The device of the embodiment of the invention multiplies the clock frequency clk, for example, the frequency of the main clock of a calculation frequency meter is multiplied when the frequency is measured, then the frequency multiplication clock is multiplexed to sample the input first signal, the first signal is converted into the second signal which is output in parallel, and then the gate circuit processing is carried out to obtain the third signal. By counting the number of the third signal edges after the device provided by the embodiment of the invention is used, the signal with too slow level turnover is processed without being influenced by small noise, so that the processing result is more accurate.
In a preferred embodiment, the register module is a shift register.
Preferably, the shift register comprises a plurality of flip-flops connected in series, and the number of the flip-flops is consistent with the frequency multiplication number of the frequency multiplication module. For example, if the frequency multiplication factor is N, the number of flip-flops is also N, so as to avoid the false determination that there is a rise or a fall and there is no rise or fall, and at the same time, to improve the effect of processing small noise, thereby improving the accuracy.
According to the signal processing device with small edge slope, the gate circuit is at least an OR gate circuit or an AND gate circuit. Specifically, when the gate circuit is an or gate, the third signal output by the gate circuit is 0 only when the outputs of the N flip-flops are all 0; and when the outputs of the N triggers are other conditions, namely not all 0, the third signal output by the gate circuit is 1. For another example, when the gate circuit is an and gate, the third signal output by the gate circuit is 1 only when the outputs of N flip-flops are all 1; and when the outputs of the N triggers are other conditions, namely not all 1, the third signal output by the gate circuit is 0. Or in order to unify the counting rule, the above process can be implemented by using either a nand gate circuit or a nor gate circuit, so the selection of the gate circuit is wider, and the and gate circuit or the gate circuit is not limited, and is not described herein again.
In a preferred embodiment, an output end of each of the flip-flops is connected to an input end of the gate circuit, an output end of the flip-flop located at a previous stage is connected to an input end of the flip-flop located at a subsequent stage, and an output end of the frequency doubling module is connected to a clock end of each of the flip-flops, respectively. The first signal input in series is converted into the second signal output in parallel through the structure, and the trigger clock of each trigger is provided by the clock after frequency multiplication.
An embodiment of the present invention further provides a signal processing method with a small slope, as shown in fig. 2, including:
step S201, receiving a clock signal and multiplying the frequency of the clock signal; specifically, the method according to the embodiment of the present invention does not directly use a clock signal for sampling, but first performs frequency multiplication on the clock signal and uses the frequency-multiplied clock signal for sampling.
Step S202, receiving the first signal input in series according to the frequency-multiplied clock signal and then outputting the second signal in parallel. Specifically, the first signal input in series is actually a signal to be tested in the prior art, and when the first signal is in an analog signal phase, the slope of the edge is too small due to some reason, that is, the slope of the rising edge or the falling edge of the signal is small, the apparatus according to the embodiment of the present invention is directed to such a signal, and if the first signal is directly used without the method according to the embodiment of the present invention, the subsequent flip-flop may be triggered erroneously.
Step S203, performing a logic operation on the second signals output in parallel to obtain a third signal. Specifically, the method according to the embodiment of the present invention does not directly use the signal to be measured, i.e., the first signal is directly output, but the first signal is processed first, i.e., the first signal is acquired through frequency doubling time, the first signal input in series is converted into the second signal output in parallel, and then the third signal is obtained through logic operation, and then the third signal is counted, so that the obtained count is correct.
Preferably, the frequency multiplication number of the clock signal is consistent with the number of bits of the second signal output in parallel. For example, the frequency multiplication factor is N, and the number of bits of the second signal output in parallel is also N, so as to avoid the rise and fall and the misjudgment that the second signal is not raised and fallen, and at the same time, improve the effect of processing small noise, thereby improving the accuracy.
Preferably, the logic operation on the second signal at least comprises: the or operation or the and operation, and the signal after the logic operation (i.e. the third signal) is different from the first signal, i.e. the high level time and the low level time of the signal under test are redefined, so that the counting of the edges of the signal under test is more accurate.
In a preferred embodiment, when each bit of the second signal output in parallel is at a high level, it is known that the signal to be measured is at a high level, otherwise, it is at a low level; or, when each bit of the second signal output in parallel is at a low level, it is known that the signal to be measured is at a low level, otherwise, it is at a high level. The specific judgment result differs according to the difference of different logic gate circuits.
Specifically, when performing an or operation on the second signals output in parallel, the third signal output is 0 only when N bits of the second signals are all 0, which means that the signal to be measured is regarded as a low level only in this case; and when the N bits of the second signal are not all 0, the output of the third signal is 1, and the signal to be measured is high level. For another example, when performing the and operation, only in the case where the N bits of the second signal are all 1, the third signal output is 1, which means that only in this case the signal to be measured is regarded as a high level; and when the N bits of the second signal are other conditions, that is, not all are 1, the third signal output after the and operation is 0, and the signal to be measured is at low level. Or in order to unify the counting rule, the above process can be implemented by nand operation or nor operation, so the selection of the logic operation is wider, and the and operation or the or operation is not limited, and is not described herein again.
Preferably, the shift register is used for receiving the first signal input in series and then outputting the second signal in parallel.
In the following, a specific embodiment is used to illustrate the above process, but the scope of the present invention is not limited to this embodiment.
As shown in fig. 3, it is a time relationship diagram of the signal to be measured pulse and the clock signal clk in the rising process. In the figure, the pulse of the signal to be measured has a small slope in one rising process and is doped with noise in the middle. As shown in fig. 4, if the signal to be measured pulse (the number of rising or falling counts) is directly measured without sampling the scheme, that is, the signal to be measured pulse is sampled when the rising edge of the clock signal clk arrives, the obtained result will be low, high, and 2 rising counts, but as can be seen from fig. 3, the signal to be measured pulse actually only goes through a rising process, so the counting method in the prior art is prone to errors in such a situation. If the device or method described in this embodiment is used to process and then measure the signal to be measured, assuming that the number of flip-flops and the frequency multiplication factor are both 4, and the signal timing sequence is as shown in fig. 5, PLL _ out _ clk is a frequency multiplication clock (output of PLL), reg0, reg 1, reg 2, and reg 3 are signals output by each flip-flop, and C _ out is a third signal output by a gate circuit, that is, the third signal after processing the signal to be measured pulse is C _ out, at this time, measurement is performed, that is, the third signal C _ out signal is sampled when the rising edge of the clock signal clk arrives, and the result is low, high, and the count is 1 rise, so that the false count is not counted as 2 rises.
In summary, the clock frequency clk is multiplied by the processing apparatus and the processing method of the present invention, and then the multiplied clock is multiplexed to sample the input first signal, and then the gate processing is performed. By counting the number of edges after the device provided by the embodiment of the invention is used, the signal with too slow level turnover is processed without being influenced by small noise, so that the processing result is more accurate.
It should be understood that, in various embodiments of the present invention, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.
It should also be understood that, in the embodiment of the present invention, the term "and/or" is only one kind of association relation describing an associated object, and means that three kinds of relations may exist. For example, a and/or B, may represent: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
Those of ordinary skill in the art will appreciate that the elements and algorithm steps of the examples described in connection with the embodiments disclosed herein may be embodied in electronic hardware, computer software, or combinations of both, and that the components and steps of the examples have been described in a functional general in the foregoing description for the purpose of illustrating clearly the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may also be an electric, mechanical or other form of connection.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment of the present invention.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention essentially or partially contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
The principle and the implementation mode of the invention are explained by applying specific embodiments in the invention, and the description of the embodiments is only used for helping to understand the method and the core idea of the invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (10)
1. A signal processing apparatus having a small slope, comprising:
the input end of the frequency doubling module receives a clock signal and doubles the frequency of the clock signal;
the clock end of the register module is connected with the output end of the frequency doubling module, and the register module receives a first signal input in series and then outputs a second signal in parallel;
the input end of the gate circuit is connected with the output end of the register module, and the gate circuit is used for carrying out logic operation on the second signals output in parallel to obtain third signals.
2. The apparatus of claim 1, wherein the register module is a shift register.
3. The apparatus of claim 2, wherein the shift register comprises a plurality of flip-flops connected in series, and the number of flip-flops is equal to the frequency of the frequency doubling module.
4. The apparatus of claim 1, wherein the gate circuit is at least an or gate circuit or an and gate circuit.
5. The apparatus according to claim 3, wherein an output terminal of each of the flip-flops is connected to an input terminal of the gate circuit, an output terminal of the flip-flop at the previous stage is connected to an input terminal of the flip-flop at the subsequent stage, and an output terminal of the frequency doubling module is connected to a clock terminal of each of the flip-flops, respectively.
6. A method for processing a signal having a small slope, comprising:
receiving a clock signal and multiplying the clock signal;
receiving a first signal input in series according to the frequency-multiplied clock signal and then outputting a second signal in parallel;
and carrying out logic operation on the second signals output in parallel to obtain third signals.
7. The method for processing a signal with a small slope according to claim 6, comprising: the frequency multiplication number of the clock signal is consistent with the number of bits of the second signal which is output in parallel.
8. The method of claim 7, wherein performing the logic operation on the second signal comprises at least: an or operation or an and operation.
9. The signal processing method according to claim 6, wherein the shift register is used to receive the first signal inputted serially and output the second signal in parallel.
10. The method as claimed in claim 6, wherein when each bit of the second signal outputted in parallel is at high level, the signal to be tested is at high level, otherwise, the signal to be tested is at low level; or, when each bit of the second signal output in parallel is at a low level, the signal to be detected is at a low level, otherwise, the signal to be detected is at a high level.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112100955A (en) * | 2020-09-11 | 2020-12-18 | 北京灵汐科技有限公司 | Signal transmission method and device |
| CN112100956A (en) * | 2020-09-11 | 2020-12-18 | 北京灵汐科技有限公司 | Signal transmission method and device |
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| CN112100955B (en) * | 2020-09-11 | 2023-12-01 | 北京灵汐科技有限公司 | Signal transmission method and device |
| CN112100956B (en) * | 2020-09-11 | 2024-02-09 | 北京灵汐科技有限公司 | Signal transmission method and device |
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