CN112100955B

CN112100955B - Signal transmission method and device

Info

Publication number: CN112100955B
Application number: CN202010955332.0A
Authority: CN
Inventors: 沈杨书; 商通; 张旺
Original assignee: Beijing Lynxi Technology Co Ltd
Current assignee: Beijing Lynxi Technology Co Ltd
Priority date: 2020-09-11
Filing date: 2020-09-11
Publication date: 2023-12-01
Anticipated expiration: 2040-09-11
Also published as: CN112100955A

Abstract

The invention discloses a signal transmission method, which is applied to a digital circuit, wherein the digital circuit comprises a plurality of circuit modules and a data transmission module arranged between two adjacent circuit modules, and the signal transmission method comprises the following steps: based on a first clock signal provided by a first clock, a plurality of circuit modules execute each operation process; based on a second clock signal provided by a second clock, the data transmission module transmits an interaction signal between two adjacent circuit modules; the execution processing at the operation and the transmission of the interaction signal are completed in one clock period of the first clock, and the clock frequency of the second clock is larger than that of the first clock. The invention also discloses a signal transmission device. The invention divides the digital circuit into a plurality of circuit modules to realize respective functions, and transmits the interactive signals between two adjacent circuit modules in a high-speed data transmission mode, and the data processing of the circuit modules and the transmission of the interactive signals are completed in a low-speed clock period.

Description

Signal transmission method and device

Technical Field

The invention relates to the technical field of digital circuits, in particular to a signal transmission method and device.

Background

Large-scale digital circuits are usually designed to implement complex functions, and in the process of calculation or simulation, the process of calculation or simulation is complicated and takes a long time because the amount of calculation or simulation data is too large.

Disclosure of Invention

In order to solve the above problems, an object of the present invention is to provide a signal transmission method and apparatus, which divide a digital circuit into a plurality of circuit modules to realize respective functions, and transmit an interaction signal between two adjacent circuit modules in a high-speed data transmission manner, wherein data processing of the plurality of circuit modules and transmission of the interaction signal are completed in a low-speed clock period.

The invention provides a signal transmission method, which is applied to a digital circuit, wherein the digital circuit comprises a plurality of circuit modules and a data transmission module arranged between two adjacent circuit modules, and the method comprises the following steps:

the plurality of circuit modules execute respective arithmetic processing based on a first clock signal provided by a first clock;

based on a second clock signal provided by a second clock, the data transmission module transmits an interaction signal between two adjacent circuit modules;

the plurality of circuit modules comprise a first circuit module and a second circuit module, the interaction signals comprise a first signal output to the second circuit module by the first circuit module and a third signal to be fed back to the first circuit module after the second circuit module performs operation processing according to the first signal, the third signal is used for the first circuit module to perform operation processing in the current clock period of the first clock, the execution of the operation processing and the transmission of the interaction signals are completed in one clock period of the first clock, and the clock frequency H2 of the second clock is larger than the clock frequency of the first clock.

As a further improvement of the invention, the first signal comprises at least one of the following signals:

the first circuit module executes a signal obtained by operation processing in the current clock period of the first clock;

the first circuit module executes the signal obtained by operation processing in the target clock period of the first clock, wherein the target clock period is the clock period before the current clock period.

As a further development of the invention, the first circuit module is controlled by the first clock signal,

wherein the plurality of circuit modules execute respective arithmetic processing based on the first clock signal provided by the first clock, including:

the first circuit module causes an input signal to be responsive to the first clock signal when a clock edge of the first clock signal triggers;

and in one clock cycle of the first clock, the first circuit module executes first operation processing on the input signal to obtain a first signal and outputs the first signal to the data transmission module.

As a further improvement of the present invention, the second clock signal provided based on the second clock, the data transmission module transmits an interaction signal between two adjacent circuit modules, including:

The data transmission module receives the second clock signal;

the data transmission module causes the first signal to respond to the second clock signal when a clock edge of the second clock signal triggers;

and in one clock period of the first clock, the data transmission module transmits the first signal to a second circuit module where a second signal is located, so that the second circuit module executes second operation processing according to the first signal and the second signal.

As a further development of the invention, the second circuit module is controlled by the first clock signal,

wherein, based on the first clock signal provided by the first clock, the plurality of circuit modules execute each operation process, and further comprising:

the second circuit module causes the second signal to be responsive to the first clock signal when a clock edge of the first clock signal triggers;

and when the first signal is received, the second circuit module executes the second operation processing on the first signal and the second signal in one clock period of the first clock to obtain a third signal and feeds the third signal back to the data transmission module.

As a further improvement of the invention, the second signal comprises at least one of the following signals:

an input signal of the second circuit module;

the second circuit module executes a signal obtained by operation processing in the current clock period of the first clock;

and the second circuit module executes the signal obtained by operation processing in the target clock period of the first clock.

As a further improvement of the present invention, the second clock signal provided based on the second clock, the data transmission module transmits an interaction signal between two adjacent circuit modules, further includes:

the data transmission module causes the third signal to be responsive to the second clock signal when a clock edge of the second clock signal triggers;

the data transmission module transmits the third signal to the first circuit module in one clock period of the first clock, so that the first circuit module executes third operation processing according to the third signal.

As a further improvement of the present invention, the plurality of circuit modules execute respective arithmetic processing based on the first clock signal supplied by the first clock, further includes:

The first circuit module causes a fourth signal to be responsive to the first clock signal when a clock edge of the first clock signal triggers;

and when the third signal is received, the first circuit module executes the third operation processing on the third signal and the fourth signal in one clock period of the first clock to obtain a fifth signal and register the fifth signal.

As a further improvement of the present invention, the method further comprises: and determining the clock frequency H2 of the second clock according to the clock frequency H1 of the first clock.

As a further improvement of the present invention, the determining the clock frequency H2 of the second clock according to the clock frequency H1 of the first clock includes:

determining a channel bit width W2 for transmitting an interaction signal between the two adjacent circuit modules, a data bit width W1 of the first signal and a data bit width W3 of the third signal;

determining the clock frequency H2 of the second clock according to the channel bit width W2 of the interactive signal between the two adjacent circuit modules, the data bit width W1 of the first signal, the data bit width W3 of the third signal and the clock frequency H1 of the first clock, wherein H2 is more than or equal to ((W1+W3) W2) H1,

Wherein, H1, H2, W1, W2 and W3 are all greater than 0.

The invention also provides a signal transmission device applied to a digital circuit, comprising:

a plurality of circuit modules for executing respective arithmetic processing based on a first clock signal supplied from a first clock;

the data transmission module is arranged between the two adjacent circuit modules and is used for transmitting interaction signals between the two adjacent circuit modules based on a second clock signal provided by a second clock;

the plurality of circuit modules comprise a first circuit module and a second circuit module, the interaction signal comprises a first signal output to the second circuit module by the first circuit module and a signal fed back to the first circuit module after the second circuit module executes operation processing according to the first signal, the third signal is used for the first circuit module to execute operation processing in the current clock cycle of the first clock, execution of the operation processing and transmission of the interaction signal are completed in one clock cycle of the first clock, and the clock frequency H2 of the second clock is larger than the clock frequency H1 of the first clock.

As a further improvement of the invention, the device determines the clock frequency H2 of the second clock by the channel bit width W2 of the data transmission module, the data bit width W1 of the first signal, the data bit width W3 of the third signal and the clock frequency H1 of the first clock, wherein h2.gtoreq ((w1+w3)/w2). H1,

Wherein, H1, H2, W1, W2 and W3 are all greater than 0.

As a further improvement of the invention, the device comprises:

the first circuit module is controlled to receive the first clock signal, and when the clock edge of the first clock signal is triggered, the first circuit module enables an input signal to respond to the first clock signal, and in the current clock period of the first clock, first operation processing is carried out on the input signal to obtain a first signal and output the first signal to the data transmission module; the clock edge trigger circuit is further used for enabling a fourth signal to respond to the first clock signal when the clock edge of the first clock signal is triggered, and executing third operation processing on the third signal and the fourth signal in the current clock period of the first clock when the third signal is received, so that a fifth signal is obtained and registered;

The data transmission module is used for receiving the second clock signal, and enabling the first signal to respond to the second clock signal when the clock edge of the second clock signal is triggered, and transmitting the first signal to a second circuit module where the second signal is located in the current clock period of the first clock; the first circuit module is further used for enabling the third signal to respond to the second clock signal when the clock edge of the second clock signal is triggered, and transmitting the third signal to a fourth signal in the current clock period of the first clock;

the second circuit module is controlled by the first clock signal, when the clock edge of the first clock signal is triggered, the second signal pair responds to the first clock signal, when the first signal is received, the second operation processing is carried out on the second signal and the first signal in the current clock period of the first clock, the third signal is obtained, and the third signal is fed back and output to the data transmission module.

an input signal of the second circuit module;

As a further development of the invention, the input signal comprises a first operational signal and a second operational signal,

wherein the first circuit module comprises:

the first register is controlled by the first clock signal, is triggered at the clock edge of the first clock signal and registers the first operation signal;

the second register is controlled by the first clock signal, is triggered at the clock edge of the first clock signal and registers the second operation signal;

the third register is controlled by the first clock signal, is triggered at the clock edge of the first clock signal and registers the fourth signal;

the first operation processing unit is used for executing first operation processing on the first operation signal and the second operation signal in one clock period of the first clock signal to obtain the first signal and outputting the first signal to the data transmission module;

and a third operation processing unit, when receiving the third signal, executing the third operation processing on the third signal and the fourth signal in the current clock cycle of the first clock signal to obtain the fifth signal.

As a further improvement of the present invention, the first circuit module further includes:

and a sixth register controlled by the first clock signal and triggered at the clock edge of the first clock signal to register the fifth signal.

As a further improvement of the present invention, the second circuit module includes:

a fifth register controlled by the first clock signal and triggered at the clock edge of the first clock signal to register the second signal;

and the second operation processing unit is used for receiving the first signal, executing the second operation processing on the second signal and the first signal in the current clock period of the first clock signal, obtaining the third signal and feeding back the third signal to the data transmission module.

As a further improvement of the present invention, the second circuit module further includes:

and a fourth register controlled by the first clock signal and triggered at the clock edge of the first clock signal to register the third signal.

The invention also provides an electronic device comprising a memory for storing one or more computer instructions, and a processor, wherein the one or more computer instructions are executed by the processor to implement the method.

The invention also provides a computer readable storage medium having stored thereon a computer program for execution by a processor to perform the method.

The beneficial effects of the invention are as follows: the large-scale digital circuit is segmented, the segmented multiple circuit modules realize respective functions, interaction signals between two adjacent circuit modules are transmitted in a high-speed data transmission mode, and data processing of the multiple circuit modules and transmission of the interaction signals are completed in a low-speed clock period, so that the whole circuit realizes shielding processing of the transmission process of the interaction signals in the simulation calculation process, and the calculation effect of simulating one circuit module equivalent to the multiple circuit modules by utilizing the multiple circuit modules can be realized.

Drawings

In order to more clearly illustrate the embodiments of the present disclosure or the prior art, the drawings that are used in the description of the embodiments or the prior art will be briefly described below. It will be apparent to those of ordinary skill in the art that the drawings in the following description are merely examples of the disclosure and that other drawings may be derived from them without inventive faculty.

Fig. 1 is a flow chart of a signal transmission method according to an exemplary embodiment of the disclosure;

FIG. 2 is a schematic diagram of a digital circuit divided into two circuit modules according to an exemplary embodiment of the present disclosure;

FIG. 3 is a flow chart of a signal transmission method of the digital circuit shown in FIG. 2;

FIG. 4 is a schematic diagram of a digital circuit divided into three circuit modules according to an exemplary embodiment of the present disclosure;

fig. 5 is a schematic diagram of a signal transmission device according to an exemplary embodiment of the present disclosure.

Detailed Description

The following description of the technical solutions in the embodiments of the present disclosure will be made clearly and completely with reference to the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are only some embodiments of the present disclosure, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without inventive effort, based on the embodiments in this disclosure are intended to be within the scope of this disclosure.

It should be noted that, if directional indications (such as up, down, left, right, front, and rear … …) are included in the embodiments of the present disclosure, the directional indications are merely used to explain the relative positional relationship, movement conditions, etc. between the components in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indications are correspondingly changed.

In addition, in the description of the present disclosure, the terminology used is for the purpose of illustration only and is not intended to limit the scope of the present disclosure. The terms "comprises" and/or "comprising" are used to specify the presence of elements, steps, operations, and/or components, but do not preclude the presence or addition of one or more other elements, steps, operations, and/or components. The terms "first," "second," and the like may be used for describing various elements, do not represent a sequence, and are not intended to limit the elements. Furthermore, in the description of the present disclosure, unless otherwise indicated, the meaning of "a plurality" is two and more. These terms are only used to distinguish one element from another element. These and/or other aspects will become apparent to those of ordinary skill in the art from a review of the following drawings and description of the embodiments of the present disclosure. The drawings are intended to depict embodiments of the disclosure for purposes of illustration only. Those skilled in the art will readily recognize from the following description that alternative embodiments of the structures and methods illustrated in the present disclosure may be employed without departing from the principles of the present disclosure.

The signal transmission method of the embodiment of the disclosure is applied to a digital circuit, the digital circuit includes a plurality of circuit modules and a data transmission module disposed between two adjacent circuit modules, as shown in fig. 1, and the method includes:

S1, based on a first clock signal provided by a first clock, a plurality of circuit modules execute each operation process;

s2, based on a second clock signal provided by a second clock, the data transmission module transmits an interaction signal between two adjacent circuit modules;

the plurality of circuit modules comprise a first circuit module and a second circuit module, the interaction signal comprises a first signal which is output to the second circuit module by the first circuit module and a third signal which is fed back to the first circuit module after the second circuit module executes operation processing according to the first signal, the third signal is used for the first circuit module to execute operation processing in the current clock cycle of the first clock, the execution of the operation processing and the transmission of the interaction signal are completed in one clock cycle of the first clock, and the clock frequency H2 of the second clock is larger than the clock frequency H1 of the first clock.

According to the method disclosed by the disclosure, a large-scale circuit can be divided into a plurality of independent circuit modules according to functions to be realized by the large-scale digital circuit, each circuit module realizes respective functions (performs each operation process, for example, may be a combinational logic operation process), the operation processes of the plurality of circuit modules and the transmission of an interaction signal are completed in a clock period of a low-speed clock (for example, a first clock with a clock frequency of 1 MHZ), and no additional low-speed clock period is consumed, so that, for example, when the large-scale circuit is simulated, the same complete simulation effect as that when each circuit module performs operation in one circuit module can be realized. The interaction signal is determined according to each segmented circuit module, and for the two adjacent circuit modules which are interacted, the interaction signal between the two adjacent circuit modules can be, for example, a signal which is output to the second circuit module after the first circuit module performs operation processing, and a signal which is fed back to the first path module after the second circuit module performs operation processing.

The first clock signal provided by the clock may be a synchronous clock signal provided by each independent circuit module in the whole large-scale circuit, the first clock signal may be triggered by a rising edge or a falling edge (hereinafter referred to as a clock edge), and the triggering mode of the first clock signal is not limited in this disclosure. The second clock signal provided by the second clock is different from the first clock signal, the second clock signal is a clock signal provided for the first signal transmission process, the second clock signal can be triggered by a rising edge or a falling edge (hereinafter referred to as a clock edge), and the triggering mode of the second clock signal is not limited in the disclosure. The first clock and the second clock have different clock frequencies and different clock periods, and the clock frequency of the second clock is larger than that of the first clock.

In an alternative embodiment, the first signal comprises at least one of the following signals:

the first circuit module executes the signal obtained by operation processing in a target clock period of the first clock, wherein the target clock period is a clock period before the current clock period.

In an alternative embodiment, the first circuit module is controlled by a first clock signal,

wherein, based on the first clock signal provided by the first clock, the plurality of circuit modules execute each operation process, including:

the first circuit module makes the input signal respond to the first clock signal when the clock edge of the first clock signal triggers;

in one clock period of the first clock, the first circuit module executes first operation processing on the input signal to obtain a first signal and outputs the first signal to the data transmission module.

In an alternative embodiment, based on a second clock signal provided by a second clock, the data transmission module transmits an interaction signal between two adjacent circuit modules, including:

the data transmission module receives a second clock signal;

the data transmission module enables the first signal to respond to the second clock signal when the clock edge of the second clock signal triggers;

in one clock period of the first clock, the data transmission module transmits the first signal to the second circuit module where the second signal is located, so that the second circuit module executes second operation processing according to the first signal and the second signal.

In an alternative embodiment, the second circuit module is controlled by the first clock signal,

Wherein, based on the first clock signal provided by the first clock, the plurality of circuit modules execute each operation process, further comprising:

the second circuit module makes the second signal respond to the first clock signal when the clock edge of the first clock signal triggers;

when the first signal is received, the second circuit module executes second operation processing on the first signal and the second signal in the current clock period of the first clock, obtains a third signal and feeds back and outputs the third signal to the data transmission module.

In an alternative embodiment, the second signal comprises at least one of the following signals:

an input signal of the second circuit module;

the second circuit module executes a signal obtained by operation processing in the current clock cycle of the first clock;

the second circuit module executes the signal obtained by the operation processing in the target clock period of the first clock.

In an alternative embodiment, the data transmission module transmits the interaction signal between two adjacent circuit modules based on the second clock signal provided by the second clock, and further includes:

the data transmission module enables the third signal to respond to the second clock signal when the clock edge of the second clock signal triggers;

in one clock period of the first clock, the data transmission module transmits the third signal to the first circuit module where the fourth signal is located, so that the first circuit module executes third operation processing according to the third signal.

The fourth signal may be at least one of an input signal of the first circuit module in a current clock cycle of the first clock, a signal obtained by the first circuit module performing the operation processing in the current clock cycle of the first clock, and a signal obtained by the first circuit module performing the operation processing in the target clock cycle of the first clock.

In an alternative embodiment, the plurality of circuit modules perform respective arithmetic processes based on a first clock signal provided by a first clock, further comprising:

the first circuit module causes the fourth signal to be responsive to the first clock signal when a clock edge of the first clock signal triggers;

when the third signal is received, the first circuit module executes third operation processing on the third signal and the fourth signal in the current clock period of the first clock, and obtains and registers a fifth signal.

For example, as shown in fig. 2, for example, a large-scale digital circuit is divided into two circuit modules, a first circuit module and a second circuit module, wherein the first circuit module performs a first operation process and a third operation process, the second circuit module performs a second operation process, both circuit modules are controlled by a low-speed clock (for example, a first clock with a frequency of 1 MHZ), and a data transmission module is disposed between the first circuit module and the second circuit module. The interaction signal between the two circuit modules is a first signal to be output to the second circuit module after the first circuit module performs a first operation process, and a third signal to be fed back to the first circuit module after the second circuit module performs a second operation process according to the first signal and the second signal (the first signal is an output signal in the interaction signal, and the third signal is a feedback signal in the interaction signal).

As shown in fig. 3, the digital circuit shown in fig. 2 has a signal transmission method comprising the following steps:

when the clock edge of the first clock signal is triggered, the first circuit module enables the input signal to respond to the first clock signal, and in the current period of the first clock, the first circuit module executes first operation processing on the input signal to obtain a first signal and outputs the first signal to the data transmission module;

the data transmission module receives a second clock signal provided by a second clock, and when the clock edge of the second clock signal is triggered, the data transmission module enables the first signal to respond to the second clock signal and transmits the first signal to a second circuit module where the second signal is located in the current clock period of the first clock;

when the clock edge of the first clock signal is triggered, the second circuit module enables the second signal to respond to the first clock signal, and when the first signal is received, the first signal and the second signal execute second operation processing in the second circuit module in the current clock period of the first clock to obtain a third signal and feed back and output the third signal to the data transmission module;

after the third signal is stable, the data transmission module receives a second clock signal provided by the second clock, and when the clock edge of the second clock signal is triggered, the data transmission module enables the third signal to respond to the second clock signal, and the third signal is continuously transmitted to the first circuit module where the fourth signal is located in the current clock period of the first clock;

When the clock edge of the first clock signal is triggered, the first circuit module enables the fourth signal to respond to the first clock signal, and when the third signal is received, the first circuit module executes third operation processing on the third signal and the fourth signal in the current clock period of the first clock, obtains a fifth signal and registers the fifth signal.

The first clock signal provided by the first clock is used for each operation process, and the second clock signal provided by the second clock is used for transmitting interaction signals between two adjacent circuit modules. When the current clock cycle of the first clock starts, a first operation process is started in a first circuit module to obtain a first signal, the first signal is transmitted to a second circuit module where a second signal is located, the first signal and the second signal are subjected to a second operation process in the second circuit module to obtain a third signal, the third signal is fed back and transmitted to the first circuit module where a fourth signal is located, and the third signal and the fourth signal are subjected to a third operation process in the first circuit module to obtain a third signal. The first arithmetic processing, the transmission of the first signal, the second arithmetic processing, the transmission of the third signal, and the third arithmetic processing are completed within one clock cycle of the first clock, so that the arithmetic processing of the two circuit modules and the transmission of the interaction signal between the two circuit modules are completed within one clock cycle of the first clock while being completed within a plurality of clock cycles of the second clock.

For example, as shown in fig. 4, the digital circuit may be further divided into three circuit modules, a first circuit module, a second circuit module and a third circuit module, the first circuit module performs a first operation process and a third operation process, the second circuit module performs a second operation process, a fourth operation process and a sixth operation process, the third circuit module performs a fifth operation process, the three circuit modules are all controlled by the same low-speed clock (for example, a first clock with a frequency of 1 MHZ), a first data transmission module is provided between the first circuit module and the second circuit module, and a second data transmission module is provided between the second circuit module and the third circuit module. The interactive signals of the first circuit module and the second circuit module are first signals which are output to the second circuit module after the first circuit module executes first operation processing, third signals which are fed back to the first circuit module after the second circuit module executes second operation processing according to the first signals and the second signals, seventh signals which are output to the third circuit module after the second circuit module executes fourth operation processing according to the sixth signals, and ninth signals which are fed back to the second circuit module after the third circuit module executes fifth operation processing according to the seventh signals and the eighth signals. When the current clock period of the first clock starts, starting first operation processing on an input signal in a first circuit module, outputting a first signal, transmitting the first signal to a second circuit module through a first output transmission module, feeding back and outputting a third signal after the first signal and the second signal execute second operation processing in the second circuit module, transmitting the third signal to the first circuit module through the first output transmission module, and executing third operation processing on the third signal and the fourth signal in the first circuit module to obtain a fifth signal; and simultaneously, when the current clock cycle of the first clock starts, fourth operation processing is performed in the second circuit module according to the sixth signal to output a seventh signal, the seventh signal is transmitted to the third circuit module through the second transmission module, the eighth signal and the seventh signal are fed back to output a ninth signal after fifth operation processing is performed in the third circuit module, the ninth signal is transmitted to the second circuit module through the second transmission module, and the ninth signal and the tenth signal are subjected to sixth operation processing in the second circuit module to obtain an eleventh signal. Wherein the first arithmetic processing, the transmission of the first signal, the second arithmetic processing, the transmission sum of the third signal and the third arithmetic processing are completed in one low-speed clock cycle; meanwhile, the fourth operation processing, the transmission of the seventh signal, the fifth operation processing, the transmission of the ninth signal, and the sixth operation processing are completed in one low-speed clock cycle. The arithmetic processing of the plurality of circuit modules and the transmission of the interaction signal are pipelined.

It can be understood that no matter the digital circuit is divided into several independent circuit modules, the operation processing of the plurality of circuit modules and the transmission of the interaction signal are completed in one low-speed clock period, and no extra low-speed clock period is consumed, so that the whole circuit does not have transmission delay of a plurality of extra low-speed clock periods in the analog calculation process, and a good analog calculation effect can be realized.

In an alternative embodiment, the method further comprises: and determining the clock frequency H2 of the second clock according to the clock frequency H1 of the first clock.

In an alternative embodiment, determining the clock frequency H2 of the second clock from the clock frequency H1 of the first clock comprises:

determining a channel bit width W2 for transmitting an interaction signal between two adjacent circuit modules, a data bit width W1 of a first signal and a data bit width W3 of a third signal;

determining the clock frequency H2 of the second clock according to the channel bit width W2 of the interactive signal between two adjacent circuit modules, the data bit width W1 of the first signal, the data bit width W3 of the third signal and the clock frequency H1 of the first clock, wherein H2 is more than or equal to ((W1+W3)/W2) H1,

Wherein, H1, H2, W1, W2 and W3 are all greater than 0.

The transmission of the interaction signals between two adjacent circuit modules is realized through a high-speed data transmission module. The data transmission module is a data transmission channel and is used for transmitting signals output after the first circuit module in the two adjacent circuit modules are subjected to operation processing to the second circuit module to perform other operation processing, and for transmitting output signals after the second circuit module is subjected to operation processing back to the first circuit module to perform other operation processing. The clock frequency of the second clock may be determined by the path bit width of the data transmission channel, the data bit width of the interaction signal to be transmitted (including the data bit widths of the first signal and the third signal), and the clock frequency of the first clock.

For example, as shown in fig. 2, for example, a large-scale digital circuit is divided into two circuit modules, a first circuit module and a second circuit module, where the first circuit module performs a first operation process and a third operation process, the second circuit module performs a second operation process, and both the two circuit modules are controlled by a low-speed clock (for example, a first clock with a frequency of 1 MHZ), where an interaction signal between the two circuit modules is a first signal of the second circuit module to be output to the first circuit module after the first circuit module performs the first operation process, and a third signal to be fed back to the first circuit module after the second circuit module performs the second operation process. The data bit width W1 of the first signal (output signal in the interaction signal) is 2bits, the data bit width W3 of the third signal (feedback signal in the interaction signal) is 98bits, the channel bit width W2 of the data transmission module is 2bits, the clock frequency H1 of the first clock is 1MHz, one clock cycle of the second clock can transmit 2bits signals, and the total 100bits signals (the first signal and the third signal) need to be transmitted within at least 50 clock cycles of the second clock, so that the clock frequency H2 of the second clock can be determined to be greater than or equal to 50MHz.

The data transmission modules can be arranged according to the circuit modules, and one data transmission module is arranged between two adjacent circuit modules. As shown in fig. 4, for example, when the digital circuit is divided into three circuit modules, the first circuit module performs a first operation, and then outputs a first signal, the first signal is transmitted to the second circuit module through the first data transmission module, the second signal and the first signal perform a second operation in the second circuit module and then feedback to output a third signal, the third signal is transmitted to the first circuit module through the first data transmission module, and the first circuit module performs a third operation; meanwhile, the second circuit module outputs a seventh signal after executing fourth operation processing, the seventh signal is transmitted to the third circuit module through the second data transmission module, the seventh signal and the eighth signal are fed back to output a ninth signal after executing fifth operation processing in the third circuit module, and the ninth signal is transmitted to the second circuit module through the second data transmission module.

According to the method disclosed by the disclosure, a large-scale digital circuit is divided into a plurality of circuit modules, each part realizes respective functions (each operation processing is executed, for example, each operation processing can be combined logic operation processing), and by setting a high-speed data transmission channel based on a high-speed clock period (clock period of a second clock) between two circuit modules, the operation processing and interaction signals of the plurality of circuit modules can be completed in a low-speed clock period (clock period of a first clock), and no additional delay of the low-speed clock period exists, so that the same complete simulation effect as that each circuit module performs operation in one circuit module can be realized during large-scale circuit simulation.

A signal transmission device according to an embodiment of the present disclosure is applied to a digital circuit, and the device includes:

a plurality of circuit modules for executing each operation process based on a first clock signal provided by a first clock;

According to the device disclosed by the disclosure, according to the functions to be realized by the large-scale digital circuit, the large-scale circuit can be divided into a plurality of circuit modules to realize respective functions (each operation processing is executed, for example, each operation processing can be a combinational logic operation processing), the operation processing of the plurality of circuit modules and the transmission of the interaction signals are completed in a clock cycle of a low-speed clock (for example, a first clock with a clock frequency of 1 MHz), and no additional transmission delay of the low-speed clock cycle is generated, so that the complete simulation effect as if each circuit module performs operation in one circuit module can be realized during the simulation of the large-scale circuit.

The signal transmission device according to the embodiment of the present disclosure may be part or all of a large-scale digital circuit, and may be used together with other circuit modules to realize functions to be realized by the large-scale digital circuit, or may be used together by a plurality of signal transmission devices to simulate functions of the large-scale circuit, which is not limited in this disclosure.

The first clock signal provided by the first clock may be a synchronous clock signal provided by each independent circuit module in the whole large-scale digital circuit, and the first clock signal may be triggered by a rising edge or a falling edge (hereinafter referred to as a clock edge), which does not limit a triggering manner of the first clock signal. The second clock signal provided by the second clock is different from the first clock signal, the second clock signal is a clock signal provided for the first signal transmission process, the second clock signal can be triggered by a rising edge or a falling edge (hereinafter referred to as a clock edge), and the triggering mode of the second clock signal is not limited in the disclosure. The first clock and the second clock have different clock frequencies and different clock periods, and the clock frequency of the second clock is larger than that of the first clock.

Wherein the first signal comprises at least one of the following signals:

In an alternative embodiment, the device determines the clock frequency H2 of the second clock by the channel bit width W2 of the data transmission module, the data bit width W1 of the first signal, the data bit width W3 of the third signal and the clock frequency H1 of the first clock, wherein H2 ∈ ((W1+W3)/W2). Times.H2,

wherein, H1, H2, W1, W2 and W3 are all greater than 0.

The data transmission module is a data transmission channel and is used for transmitting output signals after the first circuit module in the two adjacent circuit modules are subjected to operation processing to the second circuit module so as to perform other operation processing, and transmitting the output signals after the second circuit module is subjected to operation processing back to the first circuit module as feedback signals so as to perform other operation processing. The clock frequency of the second clock may be determined by the path bit width of the data transmission channel, the data bit width of the interaction signal to be transmitted (including the data bit widths of the first signal and the third signal), and the clock frequency of the first clock.

For example, as shown in fig. 2, for example, a large-scale digital circuit is divided into two circuit modules, a first circuit module and a second circuit module, where the first circuit module performs a first operation process and a third operation process, the second circuit module performs a second operation process, and both circuit modules are controlled by a low-speed clock (for example, a first clock with a frequency of 1 MHZ), where an interaction signal between the two circuit modules is a first signal to be output to the second circuit module after the first circuit module performs the first operation process and a third signal to be fed back to the first circuit module after the second circuit module performs the second operation process. The data bit width W1 of the first signal (output signal in the interaction signal) is 2bits, the data bit width W3 of the third signal (input signal in the interaction signal) is 98bits, the channel bit width W2 of the data transmission module is 2bits, the clock frequency H1 of the first clock is 1MHz, one clock cycle of the second clock can transmit 2bits signals, and the total 100bits signals (the first signal and the third signal) need to be transmitted within at least 50 clock cycles of the second clock, so that the clock frequency H2 of the second clock can be determined to be greater than or equal to 50MHz.

The data transmission modules can be arranged according to the circuit modules, and one data transmission module is arranged between two adjacent circuit modules. As shown in fig. 4, for example, when the circuit is divided into three circuit modules, a first signal output after the first circuit module performs a first operation is transmitted to a second circuit module through a first data transmission module, the second signal and the first signal perform a second operation in the second circuit module and are fed back to output a third signal, the third signal is transmitted to the first circuit module through the first data transmission module, and the first circuit module performs a third operation; meanwhile, the second circuit module executes a seventh signal output after fourth operation processing, the seventh signal is transmitted to the third circuit module through the second data transmission module, the seventh signal and the eighth signal are fed back to output a ninth signal after fifth operation processing is executed in the third circuit module, and the ninth signal is transmitted to the second circuit module through the second data transmission module.

In an alternative embodiment, as shown in fig. 5, the apparatus includes:

the first circuit module is controlled to receive a first clock signal, and when the clock edge of the first clock signal is triggered, the first circuit module enables the input signal to respond to the first clock signal, and in the current clock period of the first clock, first operation processing is carried out on the input signal to obtain a first signal and output the first signal to the data transmission module; the system is also used for enabling the fourth signal to respond to the first clock signal when the clock edge of the first clock signal is triggered, and executing third operation processing on the third signal and the fourth signal in the current clock period of the first clock to obtain a fifth signal and register the fifth signal when the third signal is received;

The data transmission module is used for receiving a second clock signal, enabling the first signal to respond to the second clock signal when the clock edge of the second clock signal is triggered, and transmitting the first signal to a second circuit module where the second signal is located in the current clock period of the first clock; the first circuit module is also used for enabling the third signal to respond to the second clock signal when the clock edge of the second clock signal is triggered, and transmitting the third signal to the fourth signal in one clock period of the first clock;

the second circuit module is controlled to receive the first clock signal, when the clock edge of the first clock signal is triggered, the first signal and the second signal are enabled to respond to the first clock signal, when the first signal is received, the second operation processing is carried out on the second signal and the first signal in the current clock period of the first clock, and a third signal is obtained and fed back to be output to the data transmission module.

The digital circuit is divided into two circuit modules, a first circuit module and a second circuit module, wherein the first circuit module executes a first operation process and a third operation process, the second circuit module executes a second operation process, the two circuit modules are controlled by a low-speed clock (for example, a first clock with the frequency of 1 MHz), an interaction signal between the two circuit modules is a first signal output after the first operation process and a third signal feedback-output after the second operation process (the first signal is an output signal in the interaction signal, and the third signal is an input signal in the interaction signal).

an input signal of the second circuit module;

the second circuit module executes the signal obtained by operation processing in the target clock period of the first clock.

For example, as shown in fig. 4, the digital circuit may be further divided into three circuit modules, a first circuit module, a second circuit module and a third circuit module, the first circuit module performs a first operation process and a third operation process, the second circuit module performs a second operation process, a fourth operation process and a sixth operation process, the third circuit module performs a fifth operation process, the three circuit modules are all controlled by the same low-speed clock (for example, a first clock with a frequency of 1 MHZ), a first data transmission module is provided between the first circuit module and the second circuit module, and a second data transmission module is provided between the second circuit module and the third circuit module. The interactive signals of the first circuit module and the second circuit module are a first signal output after first operation processing and a third signal output after second operation processing, and the interactive signals of the second circuit module and the third circuit module are a seventh signal output after fourth operation processing and a ninth signal output after fifth operation processing. When the current clock period of the first clock starts, starting first operation processing on an input signal in a first circuit module, outputting a first signal, transmitting the first signal to a second circuit module by a first data transmission module, feeding back and outputting a third signal after the first signal and the second signal execute second operation processing in the second circuit module, and transmitting the third signal to the first circuit module by the first data transmission module, and obtaining a fifth signal after the third signal and the fourth signal execute third operation processing in the first circuit module; and simultaneously, when the current clock cycle of the first clock starts, fourth operation processing is performed in the second circuit module according to the sixth signal to output a seventh signal, the second data transmission module transmits the seventh signal to the third circuit module, the eighth signal and the seventh signal are fed back to output a ninth signal after the fifth operation processing is performed in the third circuit module, the second data transmission module transmits the ninth signal to the second circuit module, and the ninth signal and the tenth signal are subjected to sixth operation processing in the second circuit module to obtain an eleventh signal. The first operation processing, the transmission of the first signal, the second operation processing, the transmission of the third signal and the third operation processing are completed in one low-speed clock cycle; meanwhile, the fourth operation processing, the transmission of the seventh signal, the fifth operation processing, the transmission of the ninth signal, and the sixth operation processing are completed in one low-speed clock cycle.

It can be understood that no matter the digital circuit is divided into several circuit modules, the operation processing of the circuit modules and the transmission of the interaction signals are completed in one low-speed clock period, and no transmission delay of the extra low-speed clock period exists, so that the whole circuit does not have the transmission delay of the extra low-speed clock period in the analog calculation process, and a good analog calculation effect can be realized.

In another alternative embodiment, the input signal includes a first operational signal and a second operational signal,

wherein the first circuit module comprises:

the first register is controlled by the first clock signal, is triggered at the clock edge of the first clock signal and registers a first operation signal;

the second register is controlled by the first clock signal, is triggered at the clock edge of the first clock signal and registers a second operation signal;

the third register is controlled by the first clock signal, is triggered at the clock edge of the first clock signal and registers a fourth signal;

the first operation processing unit is used for executing first operation processing on the first clock signal operation signal and the second operation signal in the current clock period of the first clock signal to obtain a first signal and outputting the first signal to the data transmission module;

And the third operation processing unit is used for executing third operation processing on the third signal and the fourth signal in the current clock cycle of the first clock signal when receiving the third signal, obtaining a fifth signal and registering the fifth signal.

In another alternative embodiment, the first circuit module further comprises:

and the sixth register is controlled by the first clock signal, is triggered on the clock edge of the first clock signal and registers the fifth signal.

Wherein the first clock signal is provided to control the input signals (including the first operation signal and the second operation signal) provided by the first register, the second register, the third register and the sixth register, and the fourth signal is provided to the third register. When the clock edge of the first clock signal triggers, the input signal responds to the first clock signal, the input signal can execute first operation processing through a combinational logic circuit, the first signal is output after the combinational logic operation processing is completed, the fourth signal and the third signal respond to the first clock signal after receiving the third signal fed back by the second operation processing, the fourth signal and the third signal can execute third operation processing through the combinational logic circuit, and the fifth signal is registered after the combinational logic operation processing is completed.

In an alternative embodiment, the second circuit module includes:

and the second operation processing unit is used for receiving the first signal, executing second operation processing on the second signal and the first signal in one clock period of the first clock, obtaining a third signal and feeding back and outputting the third signal to the data transmission module.

In another alternative embodiment, the second circuit module further includes:

and the fourth register is controlled by the first clock signal, is triggered on the clock edge of the first clock signal and registers the third signal.

Wherein the first clock signal controls the fourth register and the fifth register, and the second signal for performing the second operation process may be input into the fifth register. When the clock edge of the first clock signal triggers, the second signal and the first signal respond to the first clock signal, the second signal and the first signal can execute second operation processing through a combinational logic circuit, and after the combinational logic operation processing is completed, the third signal is fed back and output.

The following will illustrate an example:

One large-scale circuit needs to implement p=xop 1Y, x=az op 2M: the function of Z op 3N, where op1, op2, and op3 represent some operation or process, is not particularly limited by the present disclosure. The process of P can be divided into two phases, x=azop 2M: z op 3N, p=xop 1Y. Where a denotes a first signal output after the first arithmetic processing, x=azop 2M: z op 3N denotes a second arithmetic process, Z, M, N denotes a second signal, X denotes a third signal, p=xop 1Y denotes a third arithmetic process, and Y denotes a fourth signal. clk1 represents a first clock and clk2 represents a second clock. For example, the data bit width W1 of the a signal is 2bits, the data bit width W3 of the X signal is 98bits, the channel bit width W2 of the data transmission module is 2bits, the clock frequency H1 of clk1 is 1MHz, one clock cycle of clk2 can transmit 2bits of signals, and the total 100bits of signals (a plus X signal) need to be transmitted within at least 50 clock cycles of clk2, so the clock frequency H2 of clk2 can be designed to be 50MHz or more. This makes it possible to perform the second arithmetic processing on the a signal transmission within one clock cycle of clk1 and the third arithmetic processing on the X signal transmission, while the transmission of the a signal and the transmission of the X signal are completed within 50 clock cycles of clk 2.

In the device disclosed by the disclosure, a large-scale digital circuit is divided into a plurality of circuit modules, each part realizes respective functions (each operation processing is executed, for example, each operation processing can be combined logic operation processing), and by setting a high-speed data transmission channel based on a high-speed clock period (clock period of a second clock) between two circuit modules, the operation processing of the plurality of circuit modules and the transmission of interaction signals can be completed in a low-speed clock period (clock period of a first clock), and no additional delay of the low-speed clock period exists, so that the same complete simulation effect as the operation of each circuit module in one circuit module can be realized in the large-scale circuit simulation.

The disclosure also relates to an electronic device, including a server, a terminal, and the like. The electronic device includes: at least one processor; a memory communicatively coupled to the at least one processor; and a communication component in communication with the storage medium, the communication component receiving and transmitting data under control of the processor; wherein the memory stores instructions executable by the at least one processor to implement the methods of the above embodiments.

In an alternative embodiment, the memory is implemented as a non-volatile computer-readable storage medium, and is used to store non-volatile software programs, non-volatile computer-executable programs, and modules. The processor executes the various functional applications of the device and data processing, i.e., the implementation method, by running non-volatile software programs, instructions and modules stored in the memory.

The memory may include a memory program area and a memory data area, wherein the memory program area may store an operating system, at least one application program required for a function; the storage data area may store a list of options, etc. In addition, the memory may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory optionally includes memory remotely located from the processor, the remote memory being connectable to the external device through a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

One or more modules are stored in memory that, when executed by one or more processors, perform the methods of any of the method embodiments described above.

The product may perform the method provided by the embodiment of the present application, and has the corresponding functional module and beneficial effect of the performing method, and technical details not described in detail in the embodiment of the present application may be referred to the method provided by the embodiment of the present application.

The present disclosure also relates to a computer-readable storage medium storing a computer-readable program for causing a computer to perform some or all of the above-described method embodiments.

That is, it will be understood by those skilled in the art that all or part of the steps in implementing the methods of the embodiments described above may be implemented by a program stored in a storage medium, where the program includes several instructions for causing a device (which may be a single-chip microcomputer, a chip or the like) or a processor (processor) to perform all or part of the steps in the methods of the embodiments of the application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the disclosure may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

Furthermore, one of ordinary skill in the art will appreciate that while some embodiments herein include some features but not others included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the present disclosure and form different embodiments. For example, in the claims, any of the claimed embodiments may be used in any combination.

It will be understood by those skilled in the art that while the present disclosure has been described with reference to exemplary embodiments, various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the present disclosure. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the disclosure without departing from the essential scope thereof. Therefore, it is intended that the disclosure not be limited to the particular embodiments disclosed, but that the disclosure will include all embodiments falling within the scope of the appended claims.

Claims

1. A signal transmission method, characterized in that it is applied to a digital circuit, the digital circuit including a plurality of circuit modules and a data transmission module disposed between two adjacent circuit modules, the method comprising:

the plurality of circuit modules comprise a first circuit module and a second circuit module, the interaction signals comprise a first signal output to the second circuit module by the first circuit module and a third signal to be fed back to the first circuit module after the second circuit module performs operation processing according to the first signal, the third signal is used for the first circuit module to perform operation processing in the current clock period of the first clock, the execution of the operation processing and the transmission of the interaction signals are completed in one clock period of the first clock, and the clock frequency H2 of the second clock is larger than the clock frequency H1 of the first clock.

2. The method of claim 1, wherein the first signal comprises at least one of:

3. The method of claim 1, wherein the first circuit module is controlled by the first clock signal;

and in the current clock period of the first clock, the first circuit module executes first operation processing on the input signal to obtain a first signal and outputs the first signal to the data transmission module.

4. A method according to claim 3, wherein the data transmission module transmits an interaction signal between two adjacent circuit modules based on a second clock signal provided by a second clock, comprising:

the data transmission module receives the second clock signal;

And in the current clock period of the first clock, the data transmission module transmits the first signal to a second circuit module where a second signal is located, so that the second circuit module executes second operation processing according to the first signal and the second signal.

5. The method of claim 4, wherein the second circuit module is controlled by the first clock signal,

and when the first signal is received, the second circuit module executes the second operation processing on the first signal and the second signal in the current clock period of the first clock to obtain a third signal and feeds back and outputs the third signal to the data transmission module.

6. The method of claim 4, the second signal comprising at least one of:

an input signal of the second circuit module;

7. The method of claim 5, wherein the data transmission module transmits an interaction signal between two adjacent circuit modules based on a second clock signal provided by a second clock, further comprising:

and in the current clock cycle of the first clock, the data transmission module transmits the third signal to the first circuit module so that the first circuit module executes third operation processing according to the third signal.

8. The method of claim 7, wherein the plurality of circuit modules perform respective arithmetic processing based on a first clock signal provided by a first clock, further comprising:

and when the third signal is received, the first circuit module executes the third operation processing on the third signal and the fourth signal in the current clock period of the first clock to obtain a fifth signal and register the fifth signal.

9. The method of claim 1, wherein the method further comprises: and determining the clock frequency H2 of the second clock according to the clock frequency H1 of the first clock.

10. The method of claim 9, wherein the determining the clock frequency H2 of the second clock from the clock frequency H1 of the first clock comprises:

determining the clock frequency H2 of the second clock according to the channel bit width W2 of the interactive signal between the two adjacent circuit modules, the data bit width W1 of the first signal, the data bit width W3 of the third signal and the clock frequency H1 of the first clock, wherein H2 is more than or equal to ((W1+W3)/W2) H1,

wherein, H1, H2, W1, W2 and W3 are all greater than 0.

11. A signal transmission device for use in a digital circuit, said device comprising:

12. The apparatus of claim 11, wherein the apparatus determines a clock frequency H2 of the second clock by a channel bit width W2 of the data transmission module, a data bit width W1 of the first signal, a data bit width W3 of the third signal, and a clock frequency H1 of the first clock, wherein H2 ∈W1+W3)/W2.H2,

wherein, H1, H2, W1, W2 and W3 are all greater than 0.

13. The apparatus of claim 11, wherein the first signal comprises at least one of:

14. The apparatus of claim 11, wherein the apparatus comprises:

the first circuit module is controlled by the first clock signal, and is used for enabling an input signal to respond to the first clock signal when the clock edge of the first clock signal is triggered, and executing first operation processing on the input signal in the current clock period of the first clock to obtain a first signal and outputting the first signal to the data transmission module; the clock edge trigger circuit is further used for enabling a fourth signal to respond to the first clock signal when the clock edge of the first clock signal is triggered, and executing third operation processing on the third signal and the fourth signal in the current clock period of the first clock when the third signal is received, so that a fifth signal is obtained and registered;

the data transmission module is used for receiving the second clock signal, and when the clock edge of the second clock signal is triggered, the first signal is caused to respond to the second clock signal, and the first signal is transmitted to the second circuit module where the second signal is located in the current clock period of the first clock; and the third signal is used for responding to the second clock signal when the clock edge of the second clock signal is triggered, and transmitting the third signal to the first circuit module in the current clock period of the first clock;

And the second circuit module is controlled by the first clock signal, is used for enabling the second signal to respond to the first clock signal when the clock edge of the first clock signal is triggered, and is used for executing second operation processing on the second signal and the first signal in the current clock period of the first clock when the first signal is received, so as to obtain the third signal and feeding back and outputting the third signal to the data transmission module.

15. The apparatus of claim 14, wherein the second signal comprises at least one of:

an input signal of the second circuit module;

16. The apparatus of claim 14, wherein the input signal comprises a first operational signal and a second operational signal,

wherein the first circuit module comprises:

the first operation processing unit is used for executing first operation processing on the first operation signal and the second operation signal in the current clock period of the first clock to obtain the first signal and outputting the first signal to the data transmission module;

and a third operation processing unit, when receiving the third signal, executing the third operation processing on the third signal and the fourth signal in the current clock cycle of the first clock to obtain the fifth signal.

17. The apparatus of claim 16, wherein the first circuit module further comprises:

18. The apparatus of claim 14, wherein the second circuit module comprises:

and the second operation processing unit is used for receiving the first signal, executing the second operation processing on the second signal and the first signal in the current clock period of the first clock, obtaining the third signal and feeding back and outputting the third signal to the data transmission module.

19. The apparatus of claim 18, wherein the second circuit module further comprises:

20. An electronic device comprising a memory and a processor, wherein the memory is configured to store one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the method of any of claims 1-10.

21. A computer readable storage medium having stored thereon a computer program, wherein the computer program is executed by a processor to implement the method of any of claims 1-10.