CN104407668A - Board card for controlling automatic electrification of board card based on X86 system architecture - Google Patents
Board card for controlling automatic electrification of board card based on X86 system architecture Download PDFInfo
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- CN104407668A CN104407668A CN201410594521.4A CN201410594521A CN104407668A CN 104407668 A CN104407668 A CN 104407668A CN 201410594521 A CN201410594521 A CN 201410594521A CN 104407668 A CN104407668 A CN 104407668A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
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Abstract
The invention discloses a board card for controlling the automatic electrification of a board card based on an X86 system architecture. The board card concretely comprises a first device, a second device, a combined logic and a bridge chip, wherein the first device is used for outputting first signals to the combined logic, the second device is used for outputting second signals to the combined logic, the combined logic is used for receiving the first signals and the second signals, in addition, the first signals and the second signals are utilized for generating third signals, in addition, the third signals are output to the bridge chip, the bridge chip is used for receiving the third signals of the combined logic, in addition, after the third signals are received, back-stage electrification control signals are output for triggering the board card to realize electrification. According to the embodiment, and hardware resources on the board card are used for providing PWRBTN (power button) signals, so that the board card can be automatically and normally electrified, the operation reliability of a system is improved, PCB (printed circuit board) resources of the board card can be saved, and labor resources are saved.
Description
Technical field
The present invention relates to communication technical field, particularly relate to the board that a kind of control powers on automatically based on the board of X86 system architecture.
Background technology
Board based on the exploitation of X86 (a kind of instruction set) system architecture has strict demand to powering on, and needs experience two steps: the first step is Standby (wait) Power supply, and this step automatically completes after external power source input.Second step is rear class Power supply, namely other Power supply outside Standby power supply, this step needs to provide PWRBTN (Power button to south bridge, power button) signal, trigger south bridge and export electric control signal in rear class, thus Control card powers on, and start guidance system and board initialization.
In prior art, provide PWRBTN signal by artificial or software mode to south bridge.But in some application scenarios, the modes such as artificial or software cannot provide PWRBTN signal to south bridge, thus cause south bridge cannot export electric control signal in rear class, uncontrollable board is caused to power on, namely board cannot normally power on, all can cause board and whole system and have a strong impact on, have a strong impact on the reliability service of whole system.
Summary of the invention
The board that the embodiment of the present invention provides a kind of control automatically to power on based on the board of X86 system architecture, to provide PWRBTN signal by hardware resource to bridge chip, makes board automatically normally to power on, improves the reliability of system cloud gray model.
The board that the embodiment of the present invention provides a kind of control automatically to power on based on the board of X86 system architecture, described board specifically comprises: the first device, the second device, combinational logic and bridge chip; Wherein:
Described first device, for described Combinational logic output first signal;
Described second device, for described Combinational logic output secondary signal;
Described combinational logic, for receiving the first signal and secondary signal, and utilizes described first signal and described secondary signal to generate the 3rd signal, and described 3rd signal is exported to described bridge chip;
Described bridge chip, for receiving the 3rd signal from described combinational logic, and after receiving described 3rd signal, exports electric control signal in rear class, to trigger powering on of described board.
Described first device, specifically for the electric power thus supplied of monitoring Standby power supply; When not monitoring described Standby power supply normal power supply, then to the low level signal of described Combinational logic output; When monitoring described Standby power supply normal power supply, then to the first signal of described Combinational logic output high level;
Described second device, specifically for the electric power thus supplied of monitoring Standby power supply; When not monitoring described Standby power supply normal power supply, then to the low level signal of described Combinational logic output; When monitoring described Standby power supply normal power supply, then to the secondary signal of described Combinational logic output high level.
Preferably, in the embodiment of the present invention, described board also comprises the first electric capacity and the second electric capacity, and described first electric capacity is connected with the first device, and described second electric capacity is connected with the second device;
Described first electric capacity, for making rear to the first signal described in described Combinational logic output in the time delay very first time of described first device; Described second electric capacity, for making rear to secondary signal described in described Combinational logic output in time delay second time of described second device; Wherein, the capacitance of described first electric capacity is different from the capacitance of described second electric capacity, and the described very first time is different from described second time.
Preferably, in the embodiment of the present invention, described first device comprises the IC chip on described board, and described second device comprises the IC chip on described board.
Preferably, in the embodiment of the present invention, described combinational logic specifically comprises: the first triode, the second triode and AND circuit; Wherein, described first triode, for receiving described secondary signal, and utilizes described secondary signal to generate the 4th signal, and described 4th signal is exported to described AND circuit; Described AND circuit, for receiving described first signal and described 4th signal, and utilizes described first signal and described 4th signal to generate the 5th signal, and described 5th signal is exported to described second triode; Described second triode, for receiving described 5th signal, and utilizes described 5th signal to generate described 3rd signal, and described 3rd signal is exported to described bridge chip.
Preferably, in the embodiment of the present invention, described first triode, specifically for carrying out anti-phase process to described secondary signal, obtains described 4th signal; Described AND circuit, specifically for carrying out and process described first signal and described 4th signal, obtains described 5th signal; Described second triode, specifically for carrying out anti-phase process to described 5th signal, obtains described 3rd signal.
Preferably, in the embodiment of the present invention, described 3rd signal is specially power button PWRBTN signal, and described PWRBTN signal is Low level effective.
Preferably, in the embodiment of the present invention, the low level retention time T of described PWRBTN signal is greater than 16ms, and described low level retention time T is less than 4s.
Preferably, in the embodiment of the present invention, the mistiming between described first signal and the rising edge of described secondary signal, meet the requirement of described low level retention time T.
Preferably, in the embodiment of the present invention, when north bridge chips and South Bridge chip separate dispose time, then described bridge chip is specially described South Bridge chip; When north bridge chips and South Bridge chip are deployed in same north and south bridge chip, then described bridge chip is specially described north and south bridge chip.
Compared with prior art, the embodiment of the present invention at least has the following advantages: in the embodiment of the present invention, the board that can automatically power on based on X86 system architecture is provided, the hardware resource on board is utilized to provide PWRBTN signal to bridge chip, board is normally powered on automatically, improve the reliability of system cloud gray model, avoid the modes such as artificial or software cannot provide PWRBTN signal to bridge chip, cause bridge chip cannot export electric control signal in rear class, cause uncontrollable board to power on, have a strong impact on the problems such as the reliability service of whole system.Aforesaid way, without the need to additionally increasing part category, saves PCB (Printed CircuitBoard, the printed circuit board) resource of board, and without the need to manual intervention in automatic power up, saves human resources.
Accompanying drawing explanation
In order to the technical scheme of the embodiment of the present invention is clearly described, below the accompanying drawing used required in describing the embodiment of the present invention is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings of the embodiment of the present invention.
The structural representation of Fig. 1 board that to be a kind of control of providing of the embodiment of the present invention one power on automatically based on the board of X86 system architecture;
Fig. 2 is the structural representation of the combinational logic proposed in the embodiment of the present invention one;
Fig. 3 is the waveform schematic diagram of the PWRBTN signal of the input proposed in the embodiment of the present invention one;
The waveform schematic diagram of each signal when Fig. 4 is the combinational logic process proposed in the embodiment of the present invention one.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only a part of embodiment of the present invention, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making other embodiments all obtained under creative work prerequisite, belong to the scope of protection of the invention.
Embodiment one
For problems of the prior art, the embodiment of the present invention one provides a kind of board controlling automatically to power on based on the board of X86 (X86 is a kind of sophisticated vocabulary released by Intel, the program for the operation of control chip) system architecture.Wherein, the board that this control powers on automatically based on the board of X86 system architecture can power on automatically, and the board controlling automatically to power on based on the board of X86 system architecture can be widely used on the veneer based on X86 system architecture in the communications field, sector application.As shown in Figure 1, for controlling the structural representation of the board automatically powered on based on the board of X86 system architecture in the embodiment of the present invention.
In the embodiment of the present invention, the board controlling automatically to power on based on the board of X86 system architecture specifically includes but not limited to: the first device, the second device, combinational logic and bridge chip.Wherein, the first device specifically includes but not limited to IC (Integrated Circuit, the integrated circuit) chip on board, such as TPS3808 family chip; Second device specifically includes but not limited to the IC chip on board, such as TPS3808 family chip.Further, for X86 system architecture, generally adopt the composition structure of central processing unit+north bridge chips+South Bridge chip, when north bridge chips and South Bridge chip separate dispose time, then bridge chip is specially South Bridge chip; When north bridge chips and South Bridge chip are deployed in same north and south bridge chip, then bridge chip is specially north and south bridge chip.
In the embodiment of the present invention, the first device, for Combinational logic output first signal.Further, the first device, specifically for the electric power thus supplied of monitoring Standby power supply; When not monitoring Standby power supply normal power supply, then the first device is to the low level signal of Combinational logic output; When monitoring Standby power supply normal power supply, then the first device is to the first signal of Combinational logic output high level.Further, board can also comprise the first electric capacity, this first electric capacity is connected with above-mentioned first device, and this first electric capacity, for making rear to Combinational logic output first signal in the time delay very first time of the first device.
In the embodiment of the present invention, the second device, for Combinational logic output secondary signal.Further, the second device, specifically for the electric power thus supplied of monitoring Standby power supply; When not monitoring Standby power supply normal power supply, then the second device is to the low level signal of Combinational logic output; When monitoring Standby power supply normal power supply, then the second device is to the secondary signal of Combinational logic output high level.Further, board can also comprise the second electric capacity, this second electric capacity is connected with above-mentioned second device, and this second electric capacity, for making rear to Combinational logic output secondary signal in time delay second time of the second device.
In the embodiment of the present invention, the capacitance of the first electric capacity is different from the capacitance of the second electric capacity, and the very first time is different from the second time.Suppose that the very first time was less than for the second time, then the second device is to the secondary signal of Combinational logic output relative to first signal of the first device to Combinational logic output, has certain time-delay.
As shown in Figure 1, the first device and the second device, by the input of monitoring first order Standby power supply, export corresponding signal.First electric capacity C1 configures the output time delay of the first device, and the second electric capacity C2 configures the output time delay of the second device.In the embodiment of the present invention, the first device and the second device are after chip self working power is normal, and can keep low-level output signal, namely the first device is to the low level signal of Combinational logic output, and the second device is to the low level signal of Combinational logic output.When input for monitor Standby Power supply normal after, the first device and the second device can export high level respectively after the delay, and the time of time delay is determined by electric capacity; That is, the first device is at rear first signal to Combinational logic output high level of the time delay very first time, and the very first time of time delay is determined by the first electric capacity; Second device is in the rear secondary signal to Combinational logic output high level of time delay second time, and the second time of time delay is determined by the second electric capacity.
In above-mentioned processing procedure, be P_OUT signal by the first signal framing, secondary signal is orientated as P_OUT_DELAY signal, P_OUT_DELAY signal has certain time-delay relative to P_OUT signal.
In the embodiment of the present invention, combinational logic, for receiving the first signal (P_OUT signal) and secondary signal (P_OUT_DELAY signal), and utilize the first signal and secondary signal to generate the 3rd signal, and the 3rd signal is exported to bridge chip.Further, bridge chip, for receiving the 3rd signal from combinational logic, and after receiving the 3rd signal, exports electric control signal in rear class, to trigger powering on of board.Wherein, the 3rd signal is specially PWRBTN signal, and PWRBTN signal is Low level effective.
As shown in Figure 2, be the structural representation of combinational logic proposed in the embodiment of the present invention, combinational logic specifically comprises: the first triode, the second triode and AND circuit.Wherein, the first triode, for receiving secondary signal, and utilizes secondary signal to generate the 4th signal, and the 4th signal is exported to AND circuit.AND circuit, for receiving the first signal and the 4th signal, and utilizes the first signal and the 4th signal to generate the 5th signal, and the 5th signal is exported to the second triode.Second triode, for receiving the 5th signal, and utilizes the 5th signal to generate the 3rd signal, and the 3rd signal is exported to bridge chip.Further, the first triode, specifically for carrying out anti-phase process to secondary signal, to obtain the 4th signal.AND circuit, specifically for carrying out and process the first signal and the 4th signal, to obtain the 5th signal.Second triode, specifically for carrying out anti-phase process to the 5th signal, to obtain the 3rd signal.
In the embodiment of the present invention, the low level retention time T of PWRBTN signal (the 3rd signal) is greater than 16ms, and low level retention time T is less than 4s.Further, by to the monitoring of power supply and delays time to control, hardware realizes meet the demands automatic on electric control signal, based on this, mistiming between the rising edge of the first signal (P_OUT signal) and secondary signal (P_OUT_DELAY signal), the requirement of demand fulfillment low level retention time T.As shown in Figure 3, for the waveform schematic diagram of the PWRBTN signal of input, mistiming between P_OUT_DELAY signal and P_OUT signal rising edge will meet the requirement of time T, to make the PWRBTN signal of combinational logic generation for being supplied to bridge chip, and to bridge chip input PWRBTN signal, this PWRBTN signal is Low level effective, then makes bridge chip Control card power on.After bridge chip receives the PWRBTN signal of the combinational logic input shown in Fig. 1, trigger rear class power supply electrifying control signal.Under normal circumstances, the low level retention time is: 16ms < T < 4s.
For the first signal be P_OUT signal, secondary signal is P_OUT_DELAY signal, the 3rd signal is PWRBTN_N signal, the 4th signal for R_P_OUT_DELAY signal and the 5th signal for R_PWRBTN signal, then the waveform schematic diagram of each signal during combinational logic process is as shown in Figure 4.
As shown in Figure 4, the first triode is after receiving P_OUT_DELAY signal, and P_OUT_DELAY signal carries out anti-phase through the first triode, obtains R_P_OUT_DELAY signal.R_P_OUT_DELAY signal is exported to AND circuit by the first triode.AND circuit is after receiving P_OUT signal and R_P_OUT_DELAY signal, and P_OUT signal and R_P_OUT_DELAY signal are undertaken and process by AND circuit, obtain R_PWRBTN signal, and R_PWRBTN signal is exported to the second triode.Second triode is after receiving R_PWRBTN signal, and R_PWRBTN signal is undertaken anti-phase by the second triode again, obtains the PWRBTN_N signal needing to export to bridge chip.
In above-mentioned implementation, as shown in Figure 2, combinational logic is that employing first triode, the second triode and AND circuit realize.In actual applications, be not limited to and adopt triode and AND circuit to realize combinational logic, as long as all combinational logics that the first signal and secondary signal can be converted to the 3rd signal all can as the specific implementation of the embodiment of the present invention.Such as, the realization of combinational logic also can adopt other logical device to realize, such as 74LVC125, Sheffer stroke gate, XOR gate etc.
In sum, in the embodiment of the present invention, the board that can automatically power on based on X86 system architecture is provided, utilize the hardware resource on board to provide PWRBTN signal to bridge chip, board is normally powered on automatically, improve the reliability of system cloud gray model, avoid the modes such as artificial or software cannot provide PWRBTN signal to bridge chip, cause bridge chip cannot export electric control signal in rear class, cause uncontrollable board to power on, have a strong impact on the problems such as the reliability service of whole system.Aforesaid way, without the need to additionally increasing part category, saves the PCB resource of board, without the need to manual intervention in automatic power up, saves human resources.
Through the above description of the embodiments, those skilled in the art can be well understood to the mode that the present invention can add required general hardware platform by software and realize, and can certainly pass through hardware, but in a lot of situation, the former is better embodiment.Based on such understanding, technical scheme of the present invention can embody with the form of software product the part that prior art contributes in essence in other words, this computer software product is stored in a storage medium, comprising some instructions in order to make a computer equipment (can be personal computer, server, or the network equipment etc.) perform method described in each embodiment of the present invention.It will be appreciated by those skilled in the art that accompanying drawing is the schematic diagram of a preferred embodiment, the module in accompanying drawing or flow process might not be that enforcement the present invention is necessary.It will be appreciated by those skilled in the art that the module in the device in embodiment can carry out being distributed in the device of embodiment according to embodiment description, also can carry out respective change and be arranged in the one or more devices being different from the present embodiment.The module of above-described embodiment can merge into a module, also can split into multiple submodule further.The invention described above embodiment sequence number, just to describing, does not represent the quality of embodiment.Be only several specific embodiment of the present invention above, but the present invention is not limited thereto, the changes that any person skilled in the art can think of all should fall into protection scope of the present invention.
Claims (10)
1. control the board automatically powered on based on the board of X86 system architecture, it is characterized in that, described board specifically comprises: the first device, the second device, combinational logic and bridge chip; Wherein:
Described first device, for described Combinational logic output first signal;
Described second device, for described Combinational logic output secondary signal;
Described combinational logic, for receiving the first signal and secondary signal, and utilizes described first signal and described secondary signal to generate the 3rd signal, and described 3rd signal is exported to described bridge chip;
Described bridge chip, for receiving the 3rd signal from described combinational logic, and after receiving described 3rd signal, exports electric control signal in rear class, to trigger powering on of described board.
2. board as claimed in claim 1, is characterized in that,
Described first device, specifically for the electric power thus supplied of monitoring Standby power supply; When not monitoring described Standby power supply normal power supply, then to the low level signal of described Combinational logic output; When monitoring described Standby power supply normal power supply, then to the first signal of described Combinational logic output high level;
Described second device, specifically for the electric power thus supplied of monitoring Standby power supply; When not monitoring described Standby power supply normal power supply, then to the low level signal of described Combinational logic output; When monitoring described Standby power supply normal power supply, then to the secondary signal of described Combinational logic output high level.
3. board as claimed in claim 1, it is characterized in that, described board also comprises the first electric capacity and the second electric capacity, and described first electric capacity is connected with the first device, and described second electric capacity is connected with the second device;
Described first electric capacity, for making rear to the first signal described in described Combinational logic output in the time delay very first time of described first device; Described second electric capacity, for making rear to secondary signal described in described Combinational logic output in time delay second time of described second device; Wherein, the capacitance of described first electric capacity is different from the capacitance of described second electric capacity, and the described very first time is different from described second time.
4. the board as described in any one of claim 1-3, is characterized in that, described first device comprises the IC chip on described board, and described second device comprises the IC chip on described board.
5. board as claimed in claim 1, it is characterized in that, described combinational logic specifically comprises: the first triode, the second triode and AND circuit; Wherein, described first triode, for receiving described secondary signal, and utilizes described secondary signal to generate the 4th signal, and described 4th signal is exported to described AND circuit; Described AND circuit, for receiving described first signal and described 4th signal, and utilizes described first signal and described 4th signal to generate the 5th signal, and described 5th signal is exported to described second triode; Described second triode, for receiving described 5th signal, and utilizes described 5th signal to generate described 3rd signal, and described 3rd signal is exported to described bridge chip.
6. board as claimed in claim 5, is characterized in that, described first triode, specifically for carrying out anti-phase process to described secondary signal, obtaining described 4th signal; Described AND circuit, specifically for carrying out and process described first signal and described 4th signal, obtains described 5th signal; Described second triode, specifically for carrying out anti-phase process to described 5th signal, obtains described 3rd signal.
7. the board as described in claim 1 or 5 or 6, is characterized in that, described 3rd signal is specially power button PWRBTN signal, and described PWRBTN signal is Low level effective.
8. board as claimed in claim 7, it is characterized in that, the low level retention time T of described PWRBTN signal is greater than 16ms, and described low level retention time T is less than 4s.
9. board as claimed in claim 8, is characterized in that, the mistiming between described first signal and the rising edge of described secondary signal, meets the requirement of described low level retention time T.
10. board as claimed in claim 1, is characterized in that, when north bridge chips and South Bridge chip separate dispose time, then described bridge chip is specially described South Bridge chip; When north bridge chips and South Bridge chip are deployed in same north and south bridge chip, then described bridge chip is specially described north and south bridge chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410594521.4A CN104407668B (en) | 2014-10-29 | 2014-10-29 | It is a kind of to control the upper electric board automatically of the board based on X86 system architectures |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410594521.4A CN104407668B (en) | 2014-10-29 | 2014-10-29 | It is a kind of to control the upper electric board automatically of the board based on X86 system architectures |
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| CN104407668A true CN104407668A (en) | 2015-03-11 |
| CN104407668B CN104407668B (en) | 2017-07-28 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107678871B (en) * | 2017-09-13 | 2021-04-16 | 浙江大华技术股份有限公司 | Electronic equipment starting method and electronic equipment |
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| Publication number | Publication date |
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| CN104407668B (en) | 2017-07-28 |
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