CN104407668B - It is a kind of to control the upper electric board automatically of the board based on X86 system architectures - Google Patents
It is a kind of to control the upper electric board automatically of the board based on X86 system architectures Download PDFInfo
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- CN104407668B CN104407668B CN201410594521.4A CN201410594521A CN104407668B CN 104407668 B CN104407668 B CN 104407668B CN 201410594521 A CN201410594521 A CN 201410594521A CN 104407668 B CN104407668 B CN 104407668B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
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Abstract
The upper electric board automatically of the board based on X86 system architectures is controlled the invention discloses a kind of, the board is specifically included：First device, the second device, combinational logic and bridge chip；Wherein：First device, for the signal of Combinational logic output first；Second device, for the Combinational logic output secondary signal；The combinational logic, generates the 3rd signal, and give the bridge chip by the 3rd signal output for receiving the first signal and secondary signal, and using first signal and the secondary signal；The bridge chip, for receiving the 3rd signal from the combinational logic, and after the 3rd signal is received, electric control signal in output rear class, to trigger the upper electricity of the board.In the embodiment of the present invention, PWRBTN signals are provided to bridge chip using the hardware resource on board, enables board automatically normally upper electric, improves system operation reliability, save board PCB resources, save human resources.
Description
Technical field
The present invention relates to communication technical field, more particularly to a kind of board of the control based on X86 system architectures are automatically upper electric
Board.
Background technology
Had based on the board that a kind of X86 (instruction set) system architecture is developed to upper electricity and be strict with, it is necessary to undergo two
Step：The first step is that Standby (wait) power supply is powered, the step for be automatically performed after outside power input.Second step is
Level power supply is powered afterwards, i.e., other power supplys outside Standby power supplys are powered, and this step needs south bridge to provide PWRBTN (Power
Button, power button) signal, triggering south bridge exports electric control signal in rear class, so that electricity on Control card, and start guiding
System and board initialization.
In the prior art, PWRBTN signals are provided by artificial or software mode south bridge.But in some application scenarios,
The modes such as artificial or software can not south bridge PWRBTN signals are provided, believe so as to cause south bridge can not export electric control in rear class
Number, leading to not electricity, i.e. board on Control card can not be normally upper electric, and board and whole system can all be caused to have a strong impact on,
Have a strong impact on the reliability service of whole system.
The content of the invention
The embodiment of the present invention provides a kind of board of the control based on X86 system architectures upper electric board automatically, with by hard
Part resource provides PWRBTN signals to bridge chip so that board can be automatically normally upper electric, improves the reliability of system operation.
The embodiment of the present invention provides a kind of board of the control based on X86 system architectures upper electric board, the board automatically
Specifically include：First device, the second device, combinational logic and bridge chip；Wherein：
First device, for the signal of Combinational logic output first；
Second device, for the Combinational logic output secondary signal；
The combinational logic, for receiving the first signal and secondary signal, and utilizes first signal and described second
The signal of signal generation the 3rd, and give the bridge chip by the 3rd signal output；
The bridge chip, for receiving the 3rd signal from the combinational logic, and receive the 3rd signal it
Afterwards, electric control signal in output rear class, to trigger the upper electricity of the board.
First device, the electric power thus supplied specifically for monitoring Standby power supplys；When not monitoring the Standby
During power supply normal power supply, then to the low level signal of the Combinational logic output；Normally supplied when monitoring the Standby power supplys
When electric, then to the first signal of the Combinational logic output high level；
Second device, the electric power thus supplied specifically for monitoring Standby power supplys；When not monitoring the Standby
During power supply normal power supply, then to the low level signal of the Combinational logic output；Normally supplied when monitoring the Standby power supplys
When electric, then to the secondary signal of the Combinational logic output high level.
Preferably, in the embodiment of the present invention, the board also include the first electric capacity and the second electric capacity, first electric capacity with
First device is connected, and second electric capacity is connected with the second device；
First electric capacity, for making first device in the rear to the Combinational logic output institute of the very first time that be delayed
State the first signal；Second electric capacity, for make second device be delayed the second time it is rear defeated to the combinational logic
Go out the secondary signal；Wherein, the capacitance of first electric capacity is different from the capacitance of second electric capacity, and described first
Time is different from second time.
Preferably, in the embodiment of the present invention, first device includes the IC chip on the board, described
Second device includes the IC chip on the board.
Preferably, in the embodiment of the present invention, the combinational logic is specifically included：First triode, the second triode and with
Gate circuit；Wherein, first triode, is believed for receiving the secondary signal, and using secondary signal generation the 4th
Number, and by the 4th signal output to described and gate circuit；Described and gate circuit, for receiving first signal and described
4th signal, and first signal and the signal of the 4th signal generation the 5th are utilized, and the 5th signal output is given
Second triode；Second triode, for receiving the 5th signal, and using described in the 5th signal generation
3rd signal, and give the bridge chip by the 3rd signal output.
Preferably, in the embodiment of the present invention, first triode, specifically for carrying out anti-phase place to the secondary signal
Reason, obtains the 4th signal；Described and gate circuit, specifically for being carried out and place to first signal and the 4th signal
Reason, obtains the 5th signal；Second triode, specifically for carrying out anti-phase processing to the 5th signal, obtains institute
State the 3rd signal.
Preferably, in the embodiment of the present invention, the 3rd signal is specially power button PWRBTN signals, and described
PWRBTN signals are that low level is effective.
Preferably, in the embodiment of the present invention, the low level retention time T of the PWRBTN signals is more than 16ms, and described
Low level retention time T is less than 4s.
Preferably, in the embodiment of the present invention, the time difference between first signal and the rising edge of the secondary signal,
Meet the requirement of low level retention time T.
Preferably, in the embodiment of the present invention, when north bridge chips are separately disposed with South Bridge chip, then the bridge chip is specific
For the South Bridge chip；When north bridge chips and South Bridge chip are deployed in same north and south bridge chip, then the bridge chip is specially
The north and south bridge chip.
Compared with prior art, the embodiment of the present invention at least has advantages below：In the embodiment of the present invention there is provided based on
The board for being capable of upper electricity automatically of X86 system architectures, provides PWRBTN signals to bridge chip using the hardware resource on board, makes
Board can be automatically normally upper electric, improves the reliability of system operation, it is to avoid the mode such as artificial or software is carried without normal direction bridge chip
For PWRBTN signals, cause bridge chip can not export electric control signal in rear class, lead to not electricity on Control card, have a strong impact on
The problems such as reliability service of whole system.Aforesaid way saves the PCB (Printed of board without additionally increasing part category
Circuit Board, printed circuit board) resource, and automatically in power up without manual intervention, save human resources.
Brief description of the drawings
In order to clearly illustrate the technical scheme of the embodiment of the present invention, institute in being described below to the embodiment of the present invention
The accompanying drawing needed to use is briefly described, it should be apparent that, drawings in the following description are only some implementations of the present invention
Example, for those of ordinary skill in the art, on the premise of not paying creative work, can also be according to present invention implementation
These accompanying drawings of example obtain other accompanying drawings.
Fig. 1 is the board that board of a kind of control based on X86 system architectures that the embodiment of the present invention one is provided goes up electricity automatically
Structural representation；
Fig. 2 is the structural representation of the combinational logic proposed in the embodiment of the present invention one；
Fig. 3 is the waveform diagram of the PWRBTN signals of the input proposed in the embodiment of the present invention one；
The waveform diagram of each signal when Fig. 4 is the combinational logic processing proposed in the embodiment of the present invention one.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation is described, it is clear that described embodiment is only a part of embodiment of the present invention, rather than whole embodiments.Base
Embodiment in the present invention, those of ordinary skill in the art obtained under the premise of creative work is not made it is all its
Its embodiment, belongs to the scope of protection of the invention.
Embodiment one
For problems of the prior art, the embodiment of the present invention one provide a kind of control based on X86 (X86 be by
A kind of sophisticated vocabulary that Intel is released, the program for the operation of control chip) system architecture board upper electricity automatically plate
Card.Wherein, upper electric board being capable of upper electricity, and control is based on X86 systems automatically automatically for board of the control based on X86 system architectures
Unite framework board upper electricity automatically board can be widely applied in the communications field, sector application based on X86 system architectures
Veneer on.As shown in figure 1, to control the board based on X86 system architectures to go up electric board automatically in the embodiment of the present invention
Structural representation.
In the embodiment of the present invention, upper electric board is specifically included but not limited board of the control based on X86 system architectures automatically
In：First device, the second device, combinational logic and bridge chip.Wherein, the first device is specifically including but not limited on board
IC (Integrated Circuit, integrated circuit) chip, such as TPS3808 family chips；Second device is specifically included but not
It is limited to the IC chip on board, such as TPS3808 family chips.Further, it is general using center for X86 system architectures
The composition structure of processor+north bridge chips+South Bridge chip, when north bridge chips are separately disposed with South Bridge chip, then bridge chip has
Body is South Bridge chip；When north bridge chips and South Bridge chip are deployed in same north and south bridge chip, then bridge chip is specially north and south bridge
Chip.
In the embodiment of the present invention, the first device, for the signal of Combinational logic output first.Further, the first device,
Electric power thus supplied specifically for monitoring Standby power supplys；When not monitoring Standby power supply normal power supplies, then the first device
To the low level signal of Combinational logic output；When monitoring Standby power supply normal power supplies, then the first device is to combinational logic
Export the first signal of high level.Further, the first electric capacity, first electric capacity and above-mentioned first device can also be included on board
Part is connected, and first electric capacity, for making the first device in the rear to the signal of Combinational logic output first of the very first time that be delayed.
In the embodiment of the present invention, the second device, for Combinational logic output secondary signal.Further, the second device,
Electric power thus supplied specifically for monitoring Standby power supplys；When not monitoring Standby power supply normal power supplies, then the second device
To the low level signal of Combinational logic output；When monitoring Standby power supply normal power supplies, then the second device is to combinational logic
Export the secondary signal of high level.Further, the second electric capacity, second electric capacity and above-mentioned second device can also be included on board
Part is connected, and second electric capacity, for making the second device rear to Combinational logic output secondary signal in second time that was delayed.
In the embodiment of the present invention, the capacitance of the first electric capacity is different from the capacitance of the second electric capacity, and the very first time and the
Two times are different.Assuming that the very first time be less than the second time, then secondary signal from the second device to Combinational logic output relative to
The first signal from first device to Combinational logic output, with certain time-delay.
As shown in figure 1, the first device and the second device are by monitoring the inputs of first order Standby power supplys, to export phase
Induction signal.First electric capacity C1 configures the output delay of the first device, and the second electric capacity C2 configures the output delay of the second device.This hair
In bright embodiment, the first device and the second device can keep low-level output signal, i.e., after chip itself working power is normal
First device is to the low level signal of Combinational logic output, and the second device is to the low level signal of Combinational logic output.Work as input
Be used for monitor Standby power supplys power it is normal after, the first device and the second device can export high level after the delay respectively, and
The time of delay is determined by electric capacity；That is, the first device is rear to the first of Combinational logic output high level the delay very first time
Signal, the very first time of delay is determined by the first electric capacity；Second device is rear high to Combinational logic output second time that was delayed
The secondary signal of level, the second time of delay is determined by the second electric capacity.
In above-mentioned processing procedure, it is P_OUT signals by the first signal framing, orientates secondary signal as P_OUT_
DELAY signals, P_OUT_DELAY signals have certain time-delay relative to P_OUT signals.
In the embodiment of the present invention, combinational logic, for receiving the first signal (P_OUT signals) and secondary signal (P_OUT_
DELAY signals), and the 3rd signal is generated using the first signal and secondary signal, and by the 3rd signal output to bridge chip.Enter one
Step, bridge chip, for receiving the 3rd signal from combinational logic, and after the 3rd signal is received, electricity in output rear class
Control signal, to trigger the upper electricity of board.Wherein, the 3rd signal is specially PWRBTN signals, and PWRBTN signals are low level
Effectively.
As shown in Fig. 2 for the structural representation of the combinational logic proposed in the embodiment of the present invention, combinational logic is specifically wrapped
Include：First triode, the second triode and and gate circuit.Wherein, the first triode, for receiving secondary signal, and utilizes
Binary signal generates the 4th signal, and the 4th signal output is given into gate circuit.With gate circuit, for receive the first signal and the 4th
Signal, and the first signal and the signal of the 4th signal generation the 5th are utilized, and give the second triode by the 5th signal output.Two or three
Pole pipe, for receiving the 5th signal, and utilizes the signal of the 5th signal generation the 3rd, and by the 3rd signal output to bridge chip.Enter
One step, the first triode, specifically for carrying out anti-phase processing to secondary signal, to obtain the 4th signal.With gate circuit, specifically
For carrying out the first signal and the 4th signal with handling, to obtain the 5th signal.Second triode, specifically for believing the 5th
Number anti-phase processing is carried out, to obtain the 3rd signal.
In the embodiment of the present invention, the low level retention time T of PWRBTN signals (the 3rd signal) is more than 16ms, and low level
Retention time T is less than 4s.Further, by the monitoring to power supply and delays time to control, realization meets oneself of requirement on hardware
Dynamic upper electric control signal, based on this, the first signal (P_OUT signals) and the rising edge of secondary signal (P_OUT_DELAY signals)
Between time difference, it is necessary to meet low level retention time T requirement.As shown in figure 3, the waveform of the PWRBTN signals for input
Schematic diagram, the time difference between P_OUT_DELAY signals and P_OUT signal rising edges will meet time T requirement, so that combination
Logic generates the PWRBTN signals for being supplied to bridge chip, and inputs PWRBTN signals to bridge chip, and the PWRBTN signals are
Low level effectively, then causes electricity on bridge chip Control card.When bridge chip receives the combinational logic input shown in Fig. 1
After PWRBTN signals, rear class power supply electrifying control signal is triggered.Under normal circumstances, the low level retention time is：16ms ＜ T ＜
4s。
It is that P_OUT_DELAY signals, the 3rd signal are PWRBTN_N letters by P_OUT signals, secondary signal of the first signal
Number, the 4th signal be R_P_OUT_DELAY signals and exemplified by the 5th signal is R_PWRBTN signals, then when combinational logic is handled
Each signal waveform diagram it is as shown in Figure 4.
As shown in figure 4, the first triode is after P_OUT_DELAY signals are received, P_OUT_DELAY signals pass through the one or three
Pole pipe progress is anti-phase, obtains R_P_OUT_DELAY signals.R_P_OUT_DELAY signal outputs are given an electricity by the first triode
Road.With gate circuit after P_OUT signals and R_P_OUT_DELAY signals is received, P_OUT signals and R_P_OUT_DELAY
Signal obtains R_PWRBTN signals, and give the second triode by R_PWRBTN signal outputs by carrying out and handling with gate circuit.
Second triode is after R_PWRBTN signals are received, and R_PWRBTN signals are anti-phase again by the progress of the second triode, obtain
The PWRBTN_N signals to bridge chip are exported to needs.
In above-mentioned implementation, as shown in Fig. 2 combinational logic be using the first triode, the second triode and with door
Circuit realiration.In actual applications, it is not limited to using triode and realizing combinational logic with gate circuit, as long as can be by
First signal and secondary signal be converted to all combinational logics of the 3rd signal can as the embodiment of the present invention specific reality
Existing mode.For example, the realization of combinational logic can also be realized using other logical devices, such as 74LVC125, NAND gate, XOR
Door etc..
In summary, utilized in the embodiment of the present invention there is provided the board of electricity can be gone up automatically based on X86 system architectures
Hardware resource on board provides PWRBTN signals to bridge chip, enables board automatically normally upper electric, improves system operation
Reliability, it is to avoid the mode such as artificial or software provides PWRBTN signals without normal direction bridge chip, causes bridge chip can not export rear class
Upper electric control signal, leads to not electric on Control card, the problems such as having a strong impact on the reliability service of whole system.Aforesaid way without
Part category need to additionally be increased, save without manual intervention in the PCB resources of board, automatic power up, save human resources.
Through the above description of the embodiments, those skilled in the art can be understood that the present invention can be by
Software adds the mode of required general hardware platform to realize, naturally it is also possible to which by hardware, but in many cases, the former is more
Good embodiment.Understood based on such, what technical scheme substantially contributed to prior art in other words
Part can be embodied in the form of software product, and the computer software product is stored in a storage medium, if including
Dry instruction is to cause a computer equipment (can be personal computer, server, or network equipment etc.) to perform this hair
Method described in each bright embodiment.It will be appreciated by those skilled in the art that accompanying drawing is the schematic diagram of a preferred embodiment,
Module or flow in accompanying drawing are not necessarily implemented necessary to the present invention.It will be appreciated by those skilled in the art that in embodiment
Device in module can according to embodiment description carry out be distributed in the device of embodiment, can also carry out respective change position
In one or more devices different from the present embodiment.The module of above-described embodiment can be merged into a module, can also
It is further split into multiple submodule.The embodiments of the present invention are for illustration only, and the quality of embodiment is not represented.With
Several specific embodiments of the upper disclosed only present invention, still, the present invention is not limited to this, any those skilled in the art
Member can think of change should all fall into protection scope of the present invention.
Claims (9)
1. a kind of control the upper electric board automatically of the board based on X86 system architectures, it is characterised in that the board is specifically wrapped
Include：First device, the second device, combinational logic and bridge chip；Wherein：
First device, for the signal of Combinational logic output first；
Second device, for the Combinational logic output secondary signal；
The combinational logic, for receiving the first signal and secondary signal, and utilizes first signal and the secondary signal
The 3rd signal is generated, and the bridge chip is given by the 3rd signal output；
The bridge chip, it is defeated for receiving the 3rd signal from the combinational logic, and after the 3rd signal is received
Go out electric control signal in rear class, to trigger the upper electricity of the board；
The board also includes the first electric capacity and the second electric capacity, and first electric capacity is connected with the first device, second electric capacity
It is connected with the second device；
First electric capacity, for making first device rear to described in the Combinational logic output the in the delay very first time
One signal；Second electric capacity, for make second device be delayed the second time it is rear to the Combinational logic output institute
State secondary signal；Wherein, the capacitance of first electric capacity is different from the capacitance of second electric capacity, and the very first time
It is different from second time.
2. board as claimed in claim 1, it is characterised in that
First device, the electric power thus supplied specifically for monitoring Standby power supplys；When not monitoring the Standby power supplys
During normal power supply, then to the low level signal of the Combinational logic output；When monitoring the Standby power supplys normal power supply
When, then to the first signal of the Combinational logic output high level；
Second device, the electric power thus supplied specifically for monitoring Standby power supplys；When not monitoring the Standby power supplys
During normal power supply, then to the low level signal of the Combinational logic output；When monitoring the Standby power supplys normal power supply
When, then to the secondary signal of the Combinational logic output high level.
3. the board as described in claim any one of 1-2, it is characterised in that first device includes the collection on the board
Into circuit IC chip, second device includes the IC chip on the board.
4. board as claimed in claim 1, it is characterised in that the combinational logic is specifically included：First triode, second
Triode and and gate circuit；Wherein, first triode, for receiving the secondary signal, and utilizes the secondary signal
The 4th signal is generated, and by the 4th signal output to described and gate circuit；Described and gate circuit, for receiving described first
Signal and the 4th signal, and first signal and the signal of the 4th signal generation the 5th are utilized, and by the described 5th
Signal output gives second triode；Second triode, believes for receiving the 5th signal, and using the described 5th
Number generation the 3rd signal, and will the 3rd signal output to the bridge chip.
5. board as claimed in claim 4, it is characterised in that first triode, specifically for the secondary signal
Anti-phase processing is carried out, the 4th signal is obtained；Described and gate circuit, specifically for first signal and the 4th letter
Number carry out with processing, obtain the 5th signal；Second triode, specifically for carrying out anti-phase place to the 5th signal
Reason, obtains the 3rd signal.
6. the board as described in claim 1 or 4 or 5, it is characterised in that the 3rd signal is specially power button PWRBTN
Signal, and the PWRBTN signals are that low level is effective.
7. board as claimed in claim 6, it is characterised in that the low level retention time T of the PWRBTN signals is more than
16ms, and low level retention time T is less than 4s.
8. board as claimed in claim 7, it is characterised in that between first signal and the rising edge of the secondary signal
Time difference, meet the requirement of low level retention time T.
9. board as claimed in claim 1, it is characterised in that when north bridge chips and South Bridge chip are separately disposed, then described
Bridge chip is specially the South Bridge chip；When north bridge chips and South Bridge chip are deployed in same north and south bridge chip, then the bridge
Chip is specially the north and south bridge chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410594521.4A CN104407668B (en) | 2014-10-29 | 2014-10-29 | It is a kind of to control the upper electric board automatically of the board based on X86 system architectures |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410594521.4A CN104407668B (en) | 2014-10-29 | 2014-10-29 | It is a kind of to control the upper electric board automatically of the board based on X86 system architectures |
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| Publication Number | Publication Date |
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| CN104407668A CN104407668A (en) | 2015-03-11 |
| CN104407668B true CN104407668B (en) | 2017-07-28 |
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Cited By (1)
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| CN107678871A (en) * | 2017-09-13 | 2018-02-09 | 浙江大华技术股份有限公司 | A kind of electronic equipment starting-up method and electronic equipment |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114155888B (en) * | 2021-11-21 | 2023-08-29 | 苏州浪潮智能科技有限公司 | Hard disk power supply control device and method, computer equipment and storage medium |
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Also Published As
| Publication number | Publication date |
|---|---|
| CN104407668A (en) | 2015-03-11 |
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