CN110750889B - Real-time simulator Ethernet communication device based on FPGA - Google Patents
Real-time simulator Ethernet communication device based on FPGA Download PDFInfo
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- CN110750889B CN110750889B CN201910966952.1A CN201910966952A CN110750889B CN 110750889 B CN110750889 B CN 110750889B CN 201910966952 A CN201910966952 A CN 201910966952A CN 110750889 B CN110750889 B CN 110750889B
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Abstract
The invention discloses an Ethernet communication device of a real-time simulator based on FPGA, which comprises a shared memory RAM, a memory manager, a network communication processor, a network data transceiving module, a simulation data storage module and an MAC module, wherein the shared memory RAM is connected with the memory manager through the network communication processor; the shared memory RAM is respectively connected with the network communication processor, the network data transceiving module and the simulation data storage module and is used for storing data; the memory manager is respectively connected with the network communication processor, the network data transceiving module and the simulation data storage module and is used for allocating memory areas; the network communication processor is also connected with the MAC module and is used for finishing the initialization of the MAC module; the network data transceiver module is connected with the MAC module and is used for completing the mutual transmission of network data packets; the simulation data storage module is connected with the real-time simulator and used for receiving simulation result data; and the MAC module is connected with the computer system through the Ethernet and is used for receiving the control command and transmitting data. The invention can meet the requirement of fast data output of the FPGA real-time simulator.
Description
Technical Field
The invention relates to the technical field of design of real-time simulators of electric power systems, in particular to an Ethernet communication device of a real-time simulator based on an FPGA.
Background
With the access of a large number of resources on the power distribution side such as a distributed power supply, an energy storage device, a micro-grid and the like, the organization structure and the operation characteristics of the active power distribution network are changed deeply, so that the steady state simulation analysis of the traditional power distribution network cannot meet the requirements, and the operation mechanism and the dynamic characteristics of the active power distribution network need to be deeply known by means of fine transient simulation. The FPGA has a large number of parallel bottom layer structures and distributed memories, and depth parallel computation can be realized; meanwhile, the processing speed of the digital signal is improved by adopting a pipeline operation mode, the FPGA active power distribution network real-time simulator can be used for real-time simulation of an active power distribution network, but a large amount of simulation result data can be generated during the operation of the FPGA active power distribution network real-time simulator, a communication device with high bandwidth, low delay and real-time property guarantee needs to be configured, and no communication device meeting the requirements is available in the market at present.
Disclosure of Invention
The embodiment of the invention aims to provide an Ethernet communication device of a real-time simulator based on an FPGA (field programmable gate array), which has the characteristics of low time delay and high-speed communication capacity and can meet the requirement of the rapid data output of the FPGA real-time simulator.
In order to achieve the above object, an embodiment of the present invention provides an ethernet communication device for a real-time simulator based on an FPGA, which includes a shared memory RAM, a memory manager, a network communication processor, a network data transceiver module, a simulation data storage module, and an MAC module; wherein the content of the first and second substances,
a first input/output end of the shared memory RAM is connected with a first input/output end of the network communication processor, a second input/output end of the shared memory RAM is connected with a first input/output end of the network data transceiver module, and an input end of the shared memory RAM is connected with an output end of the simulation data storage module and is used for storing data sent by the network communication processor, the network data transceiver module and the simulation data storage module;
a first input/output end of the memory manager is connected with a second input/output end of the network communication processor, a second input/output end of the memory manager is connected with a second input/output end of the network data transceiver module, and a third input/output end of the memory manager is connected with an input/output end of the simulation data storage module, and is used for allocating memory areas for the network communication processor, the network data transceiver module and the simulation data storage module;
a third input/output end of the network communication processor is connected with the first input/output end of the MAC module and is used for finishing the initialization of the MAC module;
the third input/output end of the network data transceiver module is connected with the second input/output end of the MAC module through a bus and is used for finishing the mutual transmission of network data packets;
the input end of the simulation data storage module is connected with the output end of the real-time simulator and used for receiving simulation result data generated by the real-time simulator;
the MAC module is connected with an external computer system through Ethernet and used for receiving control instructions of the computer system and transmitting data to the computer system.
Preferably, M data storage areas and N temporary variable storage areas are arranged in the shared memory RAM, and the length of each data storage area is N bytes; wherein M is more than or equal to 1, N is more than or equal to 1, and n is more than or equal to 1500.
Preferably, M state variables are correspondingly set in the memory manager, and the state variable of the ith data storage area is sig _ state i Wherein i is more than or equal to 1 and less than or equal to M, the idle state is sig _ state _ idle, the received network data state is sig _ state _ rx _ eth, the received simulation data state is sig _ state _ rx _ sim, the sent network data state is sig _ state _ tx _ eth, and the network communication processor state is sig _ state _ ena.
Preferably, the network communication processor comprises an instruction decoding module, a control module, an arithmetic processing module, a jump processing module, an instruction memory ROM and a register set RAM; wherein the content of the first and second substances,
the instruction decoding module is used for reading the instruction in the instruction storage ROM and decomposing the instruction into an instruction code, a first operand, a second operand, a memory addressing mode and an immediate field;
the control module is used for completing the operation of taking a first operand and the operation of taking a second operand; the arithmetic processing module is used for sending an arithmetic instruction to the arithmetic processing module and sending a jump instruction to the jump processing module; the register bank RAM and the shared memory RAM are used for writing the output result of the arithmetic processing module and the output result of the jump processing module into the register bank RAM and the shared memory RAM;
the arithmetic processing module is configured to receive the first operand, the second operand, and the operation instruction sent by the control module, and output a calculation result obtained by performing the instruction encoding specified arithmetic operation on the first operand and the second operand;
and the jump processing module is used for receiving the jump instruction and the destination address sent by the control module and realizing the functions of selection, circulation and shutdown of the network communication processor.
Preferably, a first end of the control module is connected to a first input/output end of the shared memory RAM, a second end of the control module is connected to a first input/output end of the MAC module, and a third end of the control module is connected to an input end of the real-time simulator.
Preferably, the jump processing module is connected to a first input/output end of the memory manager.
Compared with the prior art, the Ethernet communication device of the real-time simulator based on the FPGA provided by the embodiment of the invention fully considers the requirements and characteristics of simulation data output, utilizes the high-speed computing capability and the high-speed network communication capability of the FPGA, improves the speed of simulation data output under the condition of ensuring the real-time property of the simulation data output, has the characteristics of low time delay and high-speed communication capability, and can meet the requirement of the rapid data output of the FPGA real-time simulator.
Drawings
Fig. 1 is a schematic structural diagram of an ethernet communication device of a real-time simulator based on an FPGA according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a network communication processor according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of an exemplary photovoltaic power generation system according to an embodiment of the present invention;
fig. 4 is a real-time waveform diagram of a phase voltage and time of a photovoltaic power generation system according to an embodiment of the present invention;
FIG. 5 is a real-time waveform of phase A current versus time for a simulation of a photovoltaic power generation system according to an embodiment of the present invention;
FIG. 6 is a real-time waveform of DC voltage versus time for a simulation of a photovoltaic power generation system according to an embodiment of the present invention;
FIG. 7 shows a photovoltaic power generation system according to an embodiment of the present invention real-time oscillogram of active power and time for system simulation;
FIG. 8 is a real-time waveform of reactive power versus time for a simulation of a photovoltaic power generation system according to an embodiment of the present invention;
FIG. 9 is a real-time waveform of frequency versus time for a simulation of a photovoltaic power generation system according to an embodiment of the present invention;
fig. 10 is a real-time phase angle versus time waveform diagram for a photovoltaic power generation system simulation according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, which is a schematic structural diagram of an ethernet communication device of a real-time simulator based on an FPGA according to an embodiment of the present invention, the ethernet communication device includes a shared memory RAM, a memory manager, a network communication processor, a network data transceiver module, a simulation data storage module, and an MAC module; wherein the content of the first and second substances,
a first input/output end of the shared memory RAM is connected with a first input/output end of the network communication processor, a second input/output end of the shared memory RAM is connected with a first input/output end of the network data transceiver module, and an input end of the shared memory RAM is connected with an output end of the simulation data storage module and is used for storing data sent by the network communication processor, the network data transceiver module and the simulation data storage module;
a first input/output end of the memory manager is connected with a second input/output end of the network communication processor, a second input/output end of the memory manager is connected with a second input/output end of the network data transceiver module, and a third input/output end of the memory manager is connected with an input/output end of the simulation data storage module, and is used for allocating memory areas for the network communication processor, the network data transceiver module and the simulation data storage module;
a third input/output end of the network communication processor is connected with the first input/output end of the MAC module and is used for completing initialization of the MAC module;
the third input/output end of the network data transceiver module is connected with the second input/output end of the MAC module through a bus and is used for finishing the mutual transmission of network data packets;
the input end of the simulation data storage module is connected with the output end of the real-time simulator and used for receiving simulation result data generated by the real-time simulator;
the MAC module is connected with an external computer system through Ethernet and used for receiving control instructions of the computer system and transmitting data to the computer system.
Specifically, the FPGA-based real-time simulator Ethernet communication device comprises a shared memory RAM, a memory manager, a network communication processor, a network data receiving and transmitting module, a simulation data storage module and an MAC module; the connection and the function among the modules are as follows:
the first input/output end of the shared memory RAM is connected with the first input/output end of the network communication processor, the second input/output end of the shared memory RAM is connected with the first input/output end of the network data transceiving module, the input end of the shared memory RAM is connected with the output end of the simulation data storage module, the shared memory RAM is used for storing data sent by the network communication processor, the network data transceiving module and the simulation data storage module and storing data sent by the network communication processor, the network data transceiving module and the simulation data storage module, specifically, the network communication processor stores network communication data to the shared memory RAM, the network data transceiving module stores network data to the shared memory RAM, and the simulation data storage module stores simulation result data to the shared memory RAM.
The first input/output end of the memory manager is connected with the second input/output end of the network communication processor, the second input/output end of the memory manager is connected with the second input/output end of the network data transceiver module, the third input/output end of the memory manager is connected with the input/output end of the simulation data storage module and used for allocating memory areas for the network communication processor, the network data transceiver module and the simulation data storage module, the memory manager is used for managing the data storage area of the shared memory RAM and is provided with state variables corresponding to the data storage area of the shared memory RAM, and the memory manager is allocated according to the state variables when allocating the memory areas, so that the allocated memory areas of the network communication processor, the network data transceiver module and the simulation data storage module are guaranteed to be not conflicted with each other.
The third input/output end of the network communication processor is connected with the first input/output end of the MAC module and is used for finishing the initialization of the MAC module, and the network communication processor can finish the initialization of the MAC module and the Ethernet chip in the FPGA development board when the FPGA power supply is started correspondingly.
And the third input/output end of the network data transceiver module is connected with the second input/output end of the MAC module through a bus and is used for finishing the mutual transmission of network data packets. Wherein the bus is an Avalon-ST bus. After the network communication processor processes simulation result data in the shared memory RAM to generate a network data packet, the network communication processor sends a control signal to the memory manager, and hands over the network data packet to the network data transceiver module, so that the network data transceiver module can send the network data packet to the MAC module through the Avalon-ST bus, and the MAC module and the Ethernet chip send the network data packet to the computer system through the Ethernet. When the computer system transmits an external network data packet to the MAC module, the MAC module transmits the external network data packet to the network data transceiver module through the Avalon-ST bus, the network data transceiver module writes the network data packet into an idle data storage area, after the writing is finished, the network data transceiver module sends a control signal to the memory manager, the network data packet is handed over to the network communication processor, and a new idle data storage area is applied to the memory manager for allocation. The two processes of mutually transmitting the network data packets are independent and do not influence each other.
The input end of the simulation data storage module is connected with the output end of the real-time simulator and used for receiving simulation result data generated by the real-time simulator; the real-time simulator is an active power distribution network real-time simulator and is used for carrying out simulation calculation to obtain simulation result data. And the simulation data storage module writes the obtained simulation result data into a free data storage area in the shared memory RAM.
And the MAC module is connected with an external computer system through Ethernet and used for receiving control instructions of the computer system and transmitting data to the computer system. The computer system typically sends a start signal to the FPGA over ethernet where it is received by the MAC module and then transmitted over the Avalon-ST bus. The network data packet generated in the FPGA is transmitted to the computer system through the MAC module.
According to the Ethernet communication device of the real-time simulator based on the FPGA, provided by the embodiment of the invention, the requirement and the characteristic of simulation data output are fully considered, the high-speed computing capability and the high-speed network communication capability of the FPGA are utilized, the speed of simulation data output is increased under the condition of ensuring the real-time property of the simulation data output, the Ethernet communication device has the characteristics of low time delay and high-speed communication capability, and the rapid data output of the FPGA real-time simulator can be met.
As an improvement of the above scheme, M data storage areas and N temporary variable storage areas are arranged in the shared memory RAM, and the length of each data storage area is N bytes; wherein M is more than or equal to 1, N is more than or equal to 1, and n is more than or equal to 1500.
Specifically, M data storage areas and N temporary variable storage areas are arranged in a shared memory RAM, and the length of each data storage area is N bytes; wherein M is more than or equal to 1, N is more than or equal to 1, and n is more than or equal to 1500. Preferably, M is 8 and N is 1. The shared memory RAM is mainly used for storing simulation result data generated in the simulation process and data interaction involved in the simulation calculation process.
As an improvement of the above scheme, the memory manager is correspondingly provided with M state variables, and the state variable of the ith data storage area is sig _ state i Wherein i is more than or equal to 1 and less than or equal to M, the idle state is sig _ state _ idle, the state of receiving network data is sig _ state _ rx _ eth, the state of receiving simulation data is sig _ state _ rx _ sim, the state of sending network data is sig _ state _ tx _ eth, and the state of the network communication processor is sig _ state _ ena.
Specifically, M state variables are correspondingly set in the memory manager, and the state variable of the ith data storage area is sig _ state i Wherein i is more than or equal to 1 and less than or equal to M, the idle state is sig _ state _ idle, the received network data state is sig _ state _ rx _ eth, the received simulation data state is sig _ state _ rx _ sim, the sent network data state is sig _ state _ tx _ eth, and the network communication processor state is sig _ state _ ena. The memory manager allocates the memory area according to the state variable of the data storage area.
Generally, the state variable sig _ state i Initial value set toNetwork communication processor state sig _ state _ ena; when the control signal of the network communication processor is 1, the state variable sig _ state of the network communication processor state sig _ state _ ena is i Setting to send network data state sig _ state _ tx _ eth; when the control signal of the simulation data saving module is '1', the state variable sig _ state of the simulation data receiving state sig _ state _ rx _ sim is i Setting the state as the state sig _ state _ ena of the network communication processor, and setting the state variable sig _ state in the idle state sig _ state _ idle i Set to receive the simulated data state sig _ state _ rx _ sim; when the network data receiving and transmitting module receives the network data and the control signal is '01', the state variable sig _ state of the state sig _ state _ rx _ eth of the network data is received i Setting the state as the state sig _ state _ ena of the network communication processor, and setting the state variable sig _ state in the idle state sig _ state _ idle i Set to receive the network data state sig _ state _ rx _ eth; when the network data transmitting and receiving module finishes transmitting the network data and the control signal is 10, the state variable sig _ state of the network data transmitting state sig _ state _ tx _ eth is i And set to idle state sig _ state _ idle.
When the state variable is changed, each module accesses the corresponding data storage area, for example, the network communication processor accesses the data storage area currently in the state of the network communication processor, the network data transceiver module accesses the data storage area currently in the state of receiving network data and sending network data, and the simulation data storage module accesses the data storage area currently in the state of receiving simulation data.
As an improvement of the above scheme, the network communication processor comprises an instruction decoding module, a control module, an arithmetic processing module, a jump processing module, an instruction memory ROM and a register bank RAM; wherein the content of the first and second substances,
the instruction decoding module is used for reading the instruction in the instruction storage ROM and decomposing the instruction into an instruction code, a first operand, a second operand, a memory addressing mode and an immediate field;
the control module is used for completing the operation of taking a first operand and the operation of taking a second operand; the arithmetic processing module is used for sending an arithmetic instruction to the arithmetic processing module and sending a jump instruction to the jump processing module; the register bank RAM and the shared memory RAM are used for writing the output result of the arithmetic processing module and the output result of the jump processing module into the register bank RAM and the shared memory RAM;
the arithmetic processing module is configured to receive the first operand, the second operand, and the operation instruction sent by the control module, and output a calculation result obtained by performing the instruction encoding specified arithmetic operation on the first operand and the second operand;
and the jump processing module is used for receiving the jump instruction and the destination address sent by the control module and realizing the functions of selection, circulation and shutdown of the network communication processor.
Fig. 2 is a schematic structural diagram of a network communication processor according to an embodiment of the present invention. As can be seen from fig. 2, the network communication processor includes an instruction decoding module, a control module, an arithmetic processing module, a jump processing module, an instruction memory ROM, and a register set RAM; wherein, the first and the second end of the pipe are connected with each other,
the instruction decoding module is used for reading an instruction in the instruction storage ROM and decomposing the instruction into an instruction code, a first operand, a second operand, a memory addressing mode and an immediate field;
the control module is used for completing the operation of taking a first operand and the operation of taking a second operand, particularly accessing the register bank RAM according to the first operand to complete the operation of taking the first operand, and accessing the register bank RAM and the shared memory RAM according to the second operand, a memory addressing mode and an immediate field to complete the operation of taking the second operand. The control module is also used for sending an operation instruction to the arithmetic processing module and sending a jump instruction to the jump processing module, and specifically, sending control signals to the arithmetic processing module and the jump processing module according to the instruction code, the first operand, the second operand, the memory addressing mode and the immediate field to complete the operation specified by the instruction code. The control module is also used for writing the output result of the arithmetic processing module and the output result of the jump processing module into a register bank RAM and a shared memory RAM, and specifically, the output results of the arithmetic processing module and the jump processing module are written into the register bank RAM and the shared memory RAM according to the instruction code, the first operand, the second operand, the memory addressing mode and the immediate field to finish the storage of the instruction operation result.
The arithmetic processing module is used for receiving the first operand, the second operand and the operation instruction sent by the control module and outputting a calculation result obtained after the first operand and the second operand are subjected to instruction coding and appointed arithmetic operation; the operation instruction is an instruction for performing a specified operation based on an instruction code.
And the jump processing module is used for receiving the jump instruction and the destination address sent by the control module and realizing the functions of selection, circulation and shutdown of the network communication processor. The jump instruction corresponds to an instruction code, and the jump processing module receives the jump instruction, namely receives the instruction code. When the stop instruction is executed, the current instruction pointer is set to be 0, and a control signal is sent to the memory manager according to the first operand, so that the change of the state variable of the data storage area is completed.
As an improvement of the above scheme, a first end of the control module is connected to a first input/output end of the shared memory RAM, a second end of the control module is connected to a first input/output end of the MAC module, and a third end of the control module is connected to an input end of the real-time emulator.
Specifically, the first terminal of the control module is connected to the first input/output terminal of the shared memory RAM, in order to store the second operand of the control module and the instruction operation result to the shared memory RAM. The second end of the control module is connected to the first input/output end of the MAC module, which is convenient for the control module, i.e. the network communication processor, to perform initialization processing on the MAC module. The third end of the control module is connected with the input end of the real-time simulator, and the purpose is to send a starting signal generated by the control module, namely the network communication processor, to the real-time simulator so that the real-time simulator starts simulation.
As an improvement of the above scheme, the jump processing module is connected to a first input/output end of the memory manager.
Specifically, the jump processing module is connected to a first input/output end of the memory manager, which is to say that the first input/output end of the corresponding memory manager is connected to a second input/output end of the network communication processor, which is to satisfy the requirement that the network communication processor sends a control signal to the memory manager to complete the change of the state variable of the data storage area.
In order to deepen understanding of the present invention, the embodiment of the present invention provides a simulation method for an ethernet communication device of a real-time simulator based on an FPGA, which includes the following specific steps:
1) Starting an FPGA power supply, and finishing initialization of an MAC module in the FPGA and an Ethernet chip in an FPGA development board by a network communication processor;
2) The computer system sends a start signal to the FPGA through the Ethernet, the MAC module transmits the start signal through an Avalon-ST bus, the network data transceiver module writes the start signal into an idle data storage area in a shared memory RAM, then sends a first control signal to the memory manager, hands over the start signal to the network communication processor, and applies for allocating a new first idle data storage area to the memory manager;
3) The network communication processor judges a start signal received by the RAM, if the received start signal is a simulation starting command, the next step is carried out, and if not, the step 2) is returned;
4) Setting simulation time t =0, and starting simulation;
5) The simulation time is advanced by one step length, and t = t + Δ t;
6) The active power distribution network real-time simulator completes the simulation calculation of the current time step to obtain simulation result data, and the simulation result data are written into an idle data storage area in the shared memory RAM by the simulation data storage module;
7) Judging whether the data storage area where the simulation result data is located is full, if so, sending a second control signal to the memory manager by the simulation data storage module, transferring the simulation result data to the network communication processor, applying for distributing a new second idle data storage area to the memory manager by the simulation data storage module, and if not, jumping to the step 10);
8) After the network communication processor processes the simulation result data in the shared memory RAM to generate a network data packet, the network communication processor sends a third control signal to the memory manager, and hands over the network data packet to the network data transceiver module;
9) The network data transceiving module sends the network data packet to the MAC module through an Avalon-ST bus, and the MAC module and the Ethernet chip send the network data packet to the computer system through the Ethernet;
10 Whether the simulation time reaches the set simulation finishing time is judged, if the set simulation finishing time is reached, the simulation is finished, otherwise, the step 5) is returned.
The handover of the data storage area mentioned in the above step refers to a change of a state variable of the data storage area, and when the state variable is changed, each module accesses the corresponding data storage area.
In order to demonstrate the effectiveness of the present invention, the embodiment of the present invention provides a simulation example, and referring to fig. 3, it is a mathematical example topological diagram of a photovoltaic power generation system provided by the embodiment of the present invention. In the embodiment, the real-time simulator adopts Stratix V series FPGA 5SGSMD5K2F40C2 of Altera corporation and a matched official development board thereof, the whole active power distribution network real-time simulator is driven by a 125MHz clock, the FPGA is connected with a computer system through a gigabit Ethernet, and a simulation result is transmitted to the computer system for display in real time through an Ethernet communication device. As can be seen from fig. 3, the main structure of the photovoltaic power generation system is that the unipolar photovoltaic power generation unit is connected with an infinite bus. In the photovoltaic power generation unit, the inverter adopts V dc -Q control, photovoltaic voltage reference V ref Given in constant form, the temperature in the examples is set at 298K ref Set to 350V and Qref to 0Var, to ensure unity power factor operation. The power supply and the transformer are simulated by adopting a voltage source connected in series with a constant impedance. In working examplesIn (c), the electrical system contains 5 power class elements (2 controlled current sources and 1 three-phase voltage source), 11 RLC elements, 6 IGBTs, 6 diodes, 8 measurement elements. The calculation example adopts 5 microsecond simulation step lengths, the output quantities comprise three-phase voltage, three-phase current, direct current voltage, active power, reactive power, frequency, phase angle and illumination intensity, wherein the three-phase voltage and the three-phase current are represented by double-precision floating point numbers, other quantities are represented by single-precision floating point numbers, the simulation result is output to the computer system every two step lengths, and the transmission speed reaches 57.6Mbps. Fig. 4 to 10 show real-time waveforms drawn after the simulation result is transmitted to the computer system through the ethernet communication device. As can be seen from fig. 4 to fig. 10, the transmission of simulation result data is real and reliable, the waveform is clear and complete, and the situations of transmission interruption, data loss and the like do not occur, so that the effectiveness of the ethernet communication device of the active power distribution network real-time simulator based on the FPGA provided by the invention is verified.
In summary, the ethernet communication device of the real-time simulator based on the FPGA provided by the embodiment of the present invention fully considers the requirement and characteristics of the simulation data output, utilizes the high-speed computing capability and the high-speed network communication capability of the FPGA, improves the speed of the simulation data output under the condition of ensuring the real-time performance of the simulation data output, meets the data output requirement of the small-step active power distribution network real-time simulator with the simulation step length of only a few microseconds, and lays a foundation for utilizing the computer system to store and analyze the result of the FPGA active power distribution network real-time simulator. The Ethernet communication device has the characteristics of high bandwidth, low time delay and capability of ensuring real-time performance and data integrity, and can meet the requirement of rapid data output of the FPGA real-time simulator.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention.
Claims (6)
1. An Ethernet communication device of a real-time simulator based on FPGA is characterized by comprising a shared memory RAM, a memory manager, a network communication processor, a network data transceiver module, a simulation data storage module and an MAC module; wherein, the first and the second end of the pipe are connected with each other,
a first input/output end of the shared memory RAM is connected with a first input/output end of the network communication processor, a second input/output end of the shared memory RAM is connected with a first input/output end of the network data transceiver module, and an input end of the shared memory RAM is connected with an output end of the simulation data storage module and is used for storing data sent by the network communication processor, the network data transceiver module and the simulation data storage module;
a first input/output end of the memory manager is connected with a second input/output end of the network communication processor, a second input/output end of the memory manager is connected with a second input/output end of the network data transceiver module, and a third input/output end of the memory manager is connected with an input/output end of the simulation data storage module, and is used for allocating memory areas for the network communication processor, the network data transceiver module and the simulation data storage module;
a third input/output end of the network communication processor is connected with the first input/output end of the MAC module and is used for finishing the initialization of the MAC module;
the third input/output end of the network data transceiver module is connected with the second input/output end of the MAC module through a bus and is used for finishing the mutual transmission of network data packets;
the input end of the simulation data storage module is connected with the output end of the real-time simulator and used for receiving simulation result data generated by the real-time simulator;
the MAC module is connected with an external computer system through Ethernet and used for receiving control instructions of the computer system and transmitting data to the computer system.
2. The FPGA-based real-time emulator Ethernet communication device of claim 1, wherein M data storage areas and N temporary variable storage areas are provided in the shared memory RAM, each data storage area having a length of N bytes; wherein M is more than or equal to 1, N is more than or equal to 1, and n is more than or equal to 1500.
3. The ethernet communication device for FPGA-based real-time emulator of claim 2, wherein M state variables are correspondingly disposed in the memory manager, and the state variable of the ith data storage area is sig _ state i Wherein i is more than or equal to 1 and less than or equal to M, the idle state is sig _ state _ idle, the received network data state is sig _ state _ rx _ eth, the received simulation data state is sig _ state _ rx _ sim, the sent network data state is sig _ state _ tx _ eth, and the network communication processor state is sig _ state _ ena.
4. The FPGA-based real-time emulator Ethernet communication device of claim 1, wherein the network communication processor comprises an instruction decoding module, a control module, an arithmetic processing module, a jump processing module, an instruction memory ROM, and a register set RAM; wherein the content of the first and second substances,
the instruction decoding module is used for reading the instruction in the instruction storage ROM and decomposing the instruction into an instruction code, a first operand, a second operand, a memory addressing mode and an immediate field;
the control module is used for completing the operation of taking a first operand and the operation of taking a second operand; the arithmetic processing module is used for sending an arithmetic instruction to the arithmetic processing module and sending a jump instruction to the jump processing module; the register bank RAM and the shared memory RAM are used for writing the output result of the arithmetic processing module and the output result of the jump processing module into the register bank RAM and the shared memory RAM;
the arithmetic processing module is configured to receive the first operand, the second operand, and the operation instruction sent by the control module, and output a calculation result obtained by performing the instruction encoding specified arithmetic operation on the first operand and the second operand;
and the jump processing module is used for receiving the jump instruction and the destination address sent by the control module and realizing the functions of selection, circulation and shutdown of the network communication processor.
5. The FPGA-based real-time emulator Ethernet communication device of claim 4, wherein a first terminal of the control module is connected to a first input/output terminal of the shared memory RAM, a second terminal of the control module is connected to a first input/output terminal of the MAC module, and a third terminal of the control module is connected to an input terminal of the real-time emulator.
6. The FPGA-based real-time emulator Ethernet communication device of claim 4, wherein the jump processing module is coupled to the first input/output of the memory manager.
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