CN211979671U

CN211979671U - Platform chip and chip verification platform

Info

Publication number: CN211979671U
Application number: CN202020438942.9U
Authority: CN
Inventors: 周天阳
Original assignee: Nanjing Dayu Semiconductor Co ltd
Current assignee: Nanjing Dayu Semiconductor Co ltd
Priority date: 2020-03-30
Filing date: 2020-03-30
Publication date: 2020-11-20
Anticipated expiration: 2030-03-30

Abstract

The present disclosure relates to a platform chip and a chip verification platform, the platform chip includes: hardware resources and virtual hardware layer, virtual hardware layer and hardware resources are connected, and the hardware resources include: the system comprises a processor, a memory and an expansion interface, wherein the expansion interface corresponds to an interface of a chip to be tested one by one, a target firmware is loaded on a virtual hardware layer, hardware resources are configured according to the target firmware, the target firmware is used for realizing the function of the chip to be tested, software to be tested corresponding to the chip to be tested runs on the processor, the virtual hardware layer receives a control instruction sent by the software to be tested through a preset virtual interface, and when the control instruction is received, a virtual address of the control instruction is mapped according to the target firmware so as to realize the control instruction. The test method and the test device have the advantages that the test of the software to be tested is realized by loading the firmware corresponding to the chip to be tested on the virtual hardware layer, the association degree between the software and the chip can be reduced, the development and maintenance efficiency is improved, and the cost is reduced.

Description

Platform chip and chip verification platform

Technical Field

The present disclosure relates to the field of electronic control technologies, and in particular, to a platform chip and a chip verification platform.

Background

The chip is a core element of the electronic equipment, and the speed and quality of chip development are of great importance to the development of electronic control technology. Generally, during the development of a chip, one or more MPW (Multi Project Wafer, chinese) processes are performed, and then a formal tape-out process is performed, and if a problem occurs in the chip, an ECO (Engineering Change Order, chinese) process is performed to make the chip meet various requirements, which results in a long development cycle of the chip. After the chip is developed, the software applied to the chip can be tested, the development of the software is influenced due to the slow development speed of the chip, the requirement for adjusting the chip can also appear in the process of testing the software, and the development period is further prolonged. The mutual dependence between the chip and the software causes the problems of low development and maintenance efficiency and high cost.

SUMMERY OF THE UTILITY MODEL

The purpose of the present disclosure is to provide a platform chip and a chip verification platform, which are used for solving the problems of low chip development efficiency and high cost in the prior art.

In order to achieve the above object, according to a first aspect of embodiments of the present disclosure, there is provided a platform chip including: hardware resources and virtual hardware layers; the virtual hardware layer is connected with the hardware resources, and the hardware resources comprise: the system comprises a processor, a memory and expansion interfaces, wherein the expansion interfaces correspond to interfaces of a chip to be tested one by one;

target firmware is loaded on the virtual hardware layer, and the hardware resources are configured according to the target firmware, wherein the target firmware is used for realizing the functions of the chip to be tested;

the processor runs to-be-tested software corresponding to the to-be-tested chip;

and the virtual hardware layer receives a control instruction sent by the software to be tested through a preset virtual interface, and maps a virtual address of the control instruction according to the target firmware when receiving the control instruction so as to realize the control instruction.

Optionally, the virtual hardware layer includes: a first Flash memory Flash and a first random access memory RAM;

the target firmware is stored in the first Flash;

and when the platform chip runs, the first RAM acquires the target firmware from the first Flash and loads the target firmware.

Optionally, the virtual hardware layer includes: the power supply module and the clock module;

the power supply module is connected with the power supply control end of the hardware resource so as to configure the power supply of the hardware resource according to the target firmware;

and the clock module is connected with the clock control end of the hardware resource so as to configure the clock of the hardware resource according to the target firmware.

Optionally, the hardware resources include at least one processor and at least one memory;

the power supply module is connected with the power supply control end of each hardware resource so as to configure the power supply of the hardware resource to be in an on state or an off state according to the target firmware;

the clock module is connected with the clock control end of each hardware resource to configure the frequency of the clock of the processor according to the target firmware.

Optionally, the virtual hardware layer includes: an address mapping module;

and the address mapping module receives the control instruction from the virtual interface and maps the virtual address of the control instruction into the register address of the processor according to the target firmware so as to realize the read-write operation of the register address of the processor by the control instruction.

Optionally, the virtual hardware layer includes: an address mapping module;

and the address mapping module receives the control instruction from the virtual interface and maps the virtual address of the control instruction into the physical address of the memory according to the target firmware so as to realize the read-write operation of the control instruction on the physical address of the memory.

Optionally, the expansion interface is connected with a preset external chip;

and when receiving the signal sent by the external chip, the expansion interface sends the signal to the hardware resource according to the target firmware.

Optionally, the processor includes one or more of a central processing unit CPU, a field programmable gate array FPGA, a digital signal processor DSP, an embedded neural network processor NPU, and a hardware accelerator;

the memory includes: one or more of RAM, ROM and Flash.

According to a second aspect of the embodiments of the present disclosure, there is provided a chip verification platform, including: a chip to be tested and the platform chip of any one of the first aspect of the embodiments of the present disclosure;

the virtual hardware layer of the platform chip is loaded with target firmware, and the target firmware is used for realizing the function of the chip to be tested;

and the processor of the platform chip is loaded with to-be-tested software corresponding to the to-be-tested chip.

Optionally, the chip verification platform further includes: connecting a chip externally;

the platform chip is connected with the external chip through an expansion interface, and when the expansion interface receives a signal sent by the external chip, the signal is sent to the hardware resource of the platform chip according to the target firmware.

Through above-mentioned technical scheme, platform chip in this disclosure includes: the hardware resource comprises a processor, a memory and an expansion interface, the expansion interface corresponds to the interface of the chip to be tested one by one, target firmware for realizing the function of the chip to be tested is loaded on the virtual hardware layer, the hardware resource can be configured according to the target firmware, the software to be tested corresponding to the chip to be tested runs on the processor, the virtual hardware layer receives a control instruction sent by the software to be tested through a preset virtual interface, and when the control instruction is received, a virtual address of the control instruction is mapped according to the target firmware so as to realize the control instruction. According to the method and the device, the firmware corresponding to the chip to be tested is loaded on the virtual hardware layer, so that the platform chip can replace the chip to be tested, the test of the software to be tested is realized, the association degree between the software and the chip can be reduced, the development and maintenance efficiency is improved, and the cost is reduced.

Additional features and advantages of the disclosure will be set forth in the detailed description which follows.

Drawings

The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the disclosure without limiting the disclosure. In the drawings:

FIG. 1 is a block diagram illustrating a platform chip in accordance with an exemplary embodiment;

FIG. 2 is a block diagram illustrating another platform chip in accordance with an example embodiment;

FIG. 3 is a block diagram illustrating another platform chip in accordance with an example embodiment;

FIG. 4 is a block diagram illustrating another platform chip in accordance with an example embodiment;

FIG. 5 is a block diagram illustrating another platform chip in accordance with an example embodiment;

FIG. 6 is a block diagram illustrating another platform chip in accordance with an example embodiment.

Description of the reference numerals

Platform chip 100 virtual hardware layer 101

Hardware resource 102 first Flash 1011

First RAM1012 processor 11021

Processor 21022 memory 11023

Memory 21024 power module 1013

Clock module 1014 address mapping module 1015

External chip 200

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the exemplary embodiments below are not intended to represent all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure, as detailed in the appended claims.

Before introducing the platform chip and the chip verification platform provided by the present disclosure, an application scenario related to various embodiments of the present disclosure is first introduced. The application scene can be a platform chip comprising various hardware resources, the platform chip can be connected with a hardware serial port of an upper computer, and the platform chip can send generated test data to a display screen of the upper computer through the hardware serial port to be displayed, so that a tester can debug the chip to be tested according to the test data. The upper computer may be a mobile terminal such as a tablet computer or a portable computer, or may be a fixed terminal such as a desktop computer.

Fig. 1 is a block diagram illustrating a platform chip according to an exemplary embodiment, and as shown in fig. 1, the platform chip 100 includes: hardware resources 102 and virtual hardware layer 101. The virtual hardware layer 101 is connected to the hardware resources 102, and the hardware resources 102 include: the system comprises a processor, a memory and an expansion interface, wherein the expansion interface corresponds to an interface of a chip to be tested one by one (the expansion interface is not marked in the figure).

The virtual hardware layer 101 is loaded with target firmware, and configures the hardware resources 102 according to the target firmware, where the target firmware is used to implement functions of a chip to be tested.

For example, the virtual hardware layer 101 may be loaded with different firmware to implement functions of different chips to be tested, that is, each chip to be tested has a corresponding firmware, and each firmware may be preset at a design stage of the corresponding chip to be tested. When testing software to be tested using the platform chip 100, first, target firmware is loaded through the virtual hardware layer 101. The software to be tested can be understood as software designed for the chip to be tested, for example, the chip to be tested is a communication chip, and then the software to be tested can be software with a communication function. After the target firmware is loaded, the platform chip 100 may configure the hardware resources 102 according to the target firmware, so that the platform chip 100 can simulate the hardware resources configured on the chip to be tested. Wherein the virtual hardware layer 101 is connected to the hardware resources 102 so that the hardware resources 102 can be configured according to the target firmware. As shown in fig. 5, the hardware resources 102 may include one or more processors, one or more memories, and one or more expansion interfaces (not labeled) corresponding to the interfaces of the chip to be tested, which may be connected to the external chip 200. For example, the hardware resource 102 may include two processors, two memories, and two expansion interfaces, i.e., a processor 11021, a processor 21022, and a memory 11023, a memory 21024, an expansion interface a, and an expansion interface B. The Processor may be, for example, a CPU (Central Processing Unit), a DSP (Digital Signal Processor), an NPU (Digital-network Processing Unit), an FPGA (Field Programmable Gate Array), a Memory such as a RAM (Random Access Memory), a chinese Random Access Memory, a ROM (Read-Only Memory), a Flash (Flash Memory), and an expansion interface such as an I/O port, an external chip (e.g., a radio frequency chip, an image Processing chip, and the like). Each processor, memory, and expansion interface in the hardware resources 102 are connected to the bus, respectively, so that the virtual hardware layer can configure the hardware resources 102 through the target firmware.

The configuration of the hardware resource 102 according to the target firmware may be to configure the hardware resource 102 to be turned on or off, or to configure a read/write clock of the hardware resource 102. For example, the hardware resources of the platform chip 100 include four CPUs, one DSP, four RAMs, two ROMs, and two expansion interfaces (for example, an interface of a radio frequency chip and an interface of an image processing chip), and the chip to be tested is provided with two CPUs, three RAMs, and an interface for connecting the radio frequency chip, so that two of the four CPUs on the platform chip 100 may be turned on, three RAMs may be turned on, interfaces of the radio frequency chip in the two expansion interfaces may be turned on, and other devices may be turned off according to the target firmware, so that the hardware resources configured on the platform chip 100 and the chip to be tested are kept consistent. The expansion Interface may be an I/O Interface, such as a Serial port, a USB (Universal Serial Bus, chinese) Interface, an SPI Interface, an I2C (Inter-Integrated Circuit Bus, chinese) Interface, a DigRF (Digital Radio Frequency, chinese) Interface, and the like.

And the processor runs the software to be tested corresponding to the chip to be tested.

The virtual hardware layer 101 receives a control instruction sent by the software to be tested through a preset virtual interface, and maps a virtual address of the control instruction according to the target firmware when receiving the control instruction, so as to implement the control instruction.

For example, the processor in the hardware resource 102 runs the software to be tested corresponding to the chip to be tested, and the processor may be any one of the processors in the hardware resource 102 or a specified one of the processors. The software to be tested can be downloaded to the processor through a preset interface (a serial port or a USB interface). When testing a chip to be tested, software to be tested can send a control instruction to the virtual hardware layer 101 through a preset virtual interface, and then the virtual hardware layer 101 receives the control instruction through the virtual interface. The virtual interface may be a pre-packaged interface between the virtual hardware layer 101 and a processor for running software to be tested, and is used to transmit a control instruction of the software to be tested to the virtual hardware layer 101. When receiving the control instruction, the virtual hardware layer 101 maps the virtual address of the control instruction according to the target firmware to obtain the physical address of the memory corresponding to the control instruction or the register address of the processor corresponding to the control instruction, thereby implementing the control instruction. The physical address of the memory (or the register address of the processor) corresponding to each virtual address may be one or more. The mapping relationship between each virtual address and the physical address of the memory (or the register address of the processor) is determined according to the target firmware, for example, a relationship table storing the mapping relationship may be included in the target firmware. In another implementation, an address mapping module preset in the virtual hardware layer 101 may be configured according to the target firmware, and then the mapping of the virtual address is implemented by the address mapping module.

It should be noted that, when the platform chip 100 is used to test the software to be tested, it is not necessary to rely on the research and development of the chip to be tested, and the platform chip 100 is only used to simulate the hardware resources configured on the chip to be tested and load the target firmware corresponding to the chip to be tested, so as to complete the test of the software to be tested, thereby improving the efficiency of software development and maintenance. Furthermore, after the software to be tested is successfully tested on the platform chip 100, the software to be tested can be directly used for testing the chip to be tested, so that the problem of repeated modification in the process of testing the software to be tested by using the chip to be tested is solved, and the efficiency of chip development and maintenance is improved.

In summary, the platform chip in the present disclosure includes: the hardware resource comprises a processor, a memory and an expansion interface, the expansion interface corresponds to the interface of the chip to be tested one by one, target firmware for realizing the function of the chip to be tested is loaded on the virtual hardware layer, the hardware resource can be configured according to the target firmware, the software to be tested corresponding to the chip to be tested runs on the processor, the virtual hardware layer receives a control instruction sent by the software to be tested through a preset virtual interface, and when the control instruction is received, a virtual address of the control instruction is mapped according to the target firmware so as to realize the control instruction. According to the method and the device, the firmware corresponding to the chip to be tested is loaded on the virtual hardware layer, so that the platform chip can replace the chip to be tested, the test of the software to be tested is realized, the association degree between the software and the chip can be reduced, the development and maintenance efficiency is improved, and the cost is reduced.

Fig. 2 is a block diagram illustrating another platform chip according to an example embodiment, and as shown in fig. 2, the virtual hardware layer 101 includes: a first Flash memory Flash 1011 and a first random access memory RAM 1012.

The target firmware is stored in the first Flash 1011.

When the platform chip 100 is running, the first RAM1012 acquires target firmware from the first Flash 1011 and loads the target firmware.

For example, the virtual hardware layer 101 may include: the first Flash 1011 and the first RAM1012, one or more firmware may be stored in the first Flash 1011 in advance, and when testing software to be tested of a chip to be tested, firmware corresponding to the chip to be tested, that is, target firmware, may be determined according to the chip to be tested, or after determining the chip to be tested, the target firmware may be downloaded to the first Flash 1011. Then, when the platform chip 100 is running, the first RAM1012 obtains and loads the target firmware from the first Flash 1011. Further, the first RAM1012 may also retrieve the target firmware from a memory provided outside the platform chip 100. For example, the target firmware is stored in the second Flash disposed outside the platform chip 100, and the first RAM1012 may obtain and load the target firmware from the second Flash through a preset serial port to complete the test of the software to be tested.

FIG. 3 is a block diagram illustrating another platform chip according to an example embodiment, and as shown in FIG. 3, the virtual hardware layer 101 includes: a power module 1013 and a clock module 1014.

The power module 1013 is connected to a power control terminal of the hardware resource 102 to configure the power of the hardware resource 102 according to the target firmware. In a scenario where there are multiple hardware resources, the power module 1013 may be connected to the power control end of each hardware resource 102 to configure the power of the hardware resource 102 to be in an on state or an off state according to the target firmware.

The clock module 1014 interfaces with a clock control terminal of the hardware resource 102 to configure the clock of the hardware resource 102 in accordance with the target firmware. In a scenario where there are multiple hardware resources, a clock module 1014 may be connected to the clock control terminal of each hardware resource 102 to configure the frequency of the processor's clock in accordance with the target firmware.

For example, when testing the software to be tested, the power supply module 1013 in the virtual hardware layer 101 may control the power supply of the whole hardware resource 102. For example, the power module 1013 may be connected to a general power control terminal of all the hardware resources 102, and if the target firmware indicates that the power of all the hardware resources 102 is configured to be in the on state, the power module 1013 may set the power of all the hardware resources 102 to be in the on state when the platform chip 100 operates. Likewise, the frequency of the clocks of all the hardware resources 102 can be uniformly controlled by the clock module 1014 in the virtual hardware layer 101. For example, the clock module 1014 may be connected to the overall clock control terminal of all the hardware resources 102, and if the target firmware instructs to set the frequency of the clocks of all the hardware resources 102 to 350MHz, the clock module 1014 may set the frequency of the clocks of all the hardware resources 102 to 350MHz when the platform chip 100 is running.

In another implementation, the power module 1013 and the clock module 1014 in the virtual hardware layer 101 can respectively configure the power and the clock of each of the hardware resources 102, where the hardware resources 102 include at least one processor and at least one memory. Specifically, the power module 1013 may be connected to the power control terminal of each hardware resource 102. For example, the hardware resource 102 includes a processor 11021, a processor 21022, a memory 11023, and a memory 21024, the power module 1013 is connected to the power control terminals of the processor 11021, the processor 21022, the memory 11023, and the memory 21024, respectively, if the target firmware instructs to set the power of the processor 11021, the processor 21022, and the memory 11023 to the on state and set the power of the memory 21024 to the off state, when the platform chip 100 runs, the power module 1013 may set the power of the processor 11021, the processor 21022, and the memory 11023 to the on state and set the power of the memory 21024 to the off state. In this way, the power module 1013 controls the power of each hardware resource 102 to be turned on or off, so that each hardware resource 102 can be freely combined, thereby achieving the purpose of cutting out redundant hardware resources 102.

Similarly, a clock module 1014 may be coupled to a clock control terminal of each hardware resource 102. For example, if the clock module 1014 is connected to the clock control terminals of the processor 11021, the processor 21022, the memory 11023 and the memory 21024 respectively, and the target firmware indicates that the clock frequency of the processor 11021 is 320MHz and the clock frequency of the processor 21022 is 350MHz, the clock module 1014 may set the clock frequency of the processor 11021 to 320MHz and the clock frequency of the processor 21022 to 350MHz when the platform chip 100 is running. In this way, the clock module 1014 configures the frequency of the clock for each hardware resource 102, thereby enabling independent control of each hardware resource 102.

Fig. 4 is a block diagram illustrating another platform chip according to an example embodiment, and as shown in fig. 4, the virtual hardware layer 101 includes: an address mapping module 1015.

The address mapping module 1015 receives the control instruction from the virtual interface, and maps the virtual address of the control instruction to the register address of the processor according to the target firmware, so as to implement the read-write operation of the register address of the processor by the control instruction.

For example, an address mapping module 1015 may be provided in the virtual hardware layer 101, and a mapping relationship between each virtual address indicated by the target firmware and a register address of the processor is stored in the address mapping module 1015 in advance, and the mapping relationship may be as shown in table 1, for example.

TABLE 1

Address coding	Hardware resources
		0x30000000-0x30001000	Processor 0
0x40000000-0x40001000	Processor 1

When the software to be tested sends a control instruction to the virtual hardware layer 101 through the virtual interface, the address mapping module 1015 receives the control instruction from the virtual interface, and determines the register address of the corresponding processor according to the virtual address of the control instruction, so that the platform chip 100 can implement the read-write operation of the register address of the processor by the control instruction through the address mapping module 1015, thereby implementing the control instruction. The virtual address of each control instruction may correspond to one or more register addresses of the processor. Further, the address mapping module 1015 may also store a mapping relationship between each extended interface indicated by the target firmware and the register address of the processor in advance, for example, as shown in table 2, where the extended interface may be, for example, a UART (Universal Asynchronous Receiver/Transmitter, chinese) interface.

TABLE 2

Address coding	Hardware resources
		0x50000000-0x50001000	UART0

Optionally, the virtual hardware layer 101 includes: an address mapping module 1015.

The address mapping module 1015 receives the control instruction from the virtual interface, and maps the virtual address of the control instruction to the physical address of the memory according to the target firmware, so as to implement the read-write operation of the control instruction on the physical address of the memory.

In another implementation scenario, the address mapping module 1015 stores a mapping relationship between each virtual address included in the target firmware and a physical address of the memory in advance, and the mapping relationship may be as shown in table 3, for example.

TABLE 3

Address coding	Hardware resources
		0x000000000-0x0FFFFFFF	RAM0
0x100000000-0x1FFFFFFF	RAM1
		0x200000000-0x2FFFFFFF	Flash

When the software to be tested sends a control instruction to the virtual hardware layer 101 through the virtual interface, the address mapping module 1015 receives the control instruction from the virtual interface, and determines the physical address of the corresponding memory according to the virtual address of the control instruction, so that the platform chip 100 can implement the read-write operation of the control instruction on the physical address of the memory through the address mapping module 1015, thereby implementing the control instruction. The physical address of the memory corresponding to the virtual address of each control instruction may be one or more.

Fig. 5 is a block diagram illustrating another platform chip according to an exemplary embodiment, and as shown in fig. 5, an expansion interface is connected to a predetermined external chip 200.

When receiving the signal sent by the external chip 200, the expansion interface sends the signal to the hardware resource 102 according to the target firmware.

For example, the expansion interface may be used to connect a preset external chip 200, the number of the expansion interfaces may be one or multiple, each expansion interface is connected to one external chip 200, the expansion interfaces correspond to the interfaces of the chip to be tested one to one, and each expansion interface is packaged according to the target firmware. For example, the expansion interface may include a radio frequency chip interface, an image processing chip interface, and the like. According to the requirement of the software to be tested, the external chip 200 can be connected through the expansion interface so as to test the software to be tested. For example, when testing the software to be tested, the function of the radio frequency chip needs to be utilized, then the radio frequency chip interface in the expansion interface may be connected to the radio frequency chip, and when the expansion interface receives a signal sent by the radio frequency chip, the signal may be sent to the hardware resource 102 according to the target firmware, so as to implement the test of the software to be tested.

Fig. 6 is a block diagram of another platform chip according to an exemplary embodiment, and as shown in fig. 6, the processor includes one or more of a central processing unit CPU, a field programmable gate array FPGA, a digital signal processor DSP, an embedded neural network processor NPU, and a hardware accelerator.

The memory includes: one or more of RAM, ROM and Flash.

For example, the hardware resource 102 includes a processor and a memory, and the processor may include one or more of a CPU, an FPGA, a DSP, an NPU, and a hardware accelerator, and may also be another type of processor, where the hardware accelerator is used for performing data processing together with another processor, so as to increase the speed of data processing. The memory may include one or more of RAM, ROM, Flash, and other types of processors, which are not limited in this disclosure. When testing the software to be tested corresponding to the chip to be tested, the corresponding target firmware may be loaded according to the chip to be tested, and then different hardware resources in the hardware resources 102 may be configured according to the target firmware.

The present disclosure also provides a chip verification platform, which includes: a chip under test and the platform chip 100 of any one of the first aspects of the embodiments of the present disclosure.

The virtual hardware layer 101 of the platform chip 100 is loaded with target firmware, and the target firmware is used for realizing the functions of the chip to be tested.

The processor of the platform chip 100 is loaded with the software to be tested corresponding to the chip to be tested.

Optionally, the chip verification platform further comprises: is externally connected with the chip 200.

The platform chip 100 is connected to the external chip 200 through an expansion interface, and when receiving a signal sent by the external chip 200, the expansion interface sends the signal to the hardware resource 102 of the platform chip 100 according to the target firmware.

Regarding the chip verification platform in the above embodiments, the specific manner in which the platform chip 100 tests the software to be tested has been described in detail in the above embodiments related to the platform chip 100, and will not be described in detail here. It should be noted that, after the software to be tested is successfully tested on the platform chip 100, the chip to be tested may be further tested by the software to be tested to verify the function of the chip to be tested, so as to avoid the problem of repeated modification in the process of testing the software to be tested by using the chip to be tested, thereby improving the research and development efficiency of the chip to be tested.

Although the preferred embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited to the specific details of the embodiments, and other embodiments of the present disclosure can be easily conceived by those skilled in the art within the technical spirit of the present disclosure after considering the description and practicing the present disclosure, and all fall within the protection scope of the present disclosure.

It should be noted that the various technical features described in the above embodiments can be combined in any suitable way without contradiction, and in order to avoid unnecessary repetition, the disclosure does not need to be separately described in various possible combinations, and should be considered as the disclosure of the disclosure as long as the concepts of the disclosure are not violated.

Claims

1. A platform chip, comprising: hardware resources and virtual hardware layers; the virtual hardware layer is connected with the hardware resources, and the hardware resources comprise: the system comprises a processor, a memory and expansion interfaces, wherein the expansion interfaces correspond to interfaces of a chip to be tested one by one;

2. The platform chip of claim 1, wherein the virtual hardware layer comprises: a first Flash and a first RAM;

the target firmware is stored in the first Flash;

3. The platform chip of claim 1, wherein the virtual hardware layer comprises: the power supply module and the clock module;

4. The platform chip of claim 3, wherein the hardware resources comprise at least one processor and at least one memory;

5. The platform chip of claim 1, wherein the virtual hardware layer comprises: an address mapping module;

6. The platform chip of claim 1, wherein the virtual hardware layer comprises: an address mapping module;

7. The platform chip according to claim 1, wherein the expansion interface is connected to a predetermined external chip;

8. The platform chip according to any of claims 1 to 7, wherein the processor comprises one or more of a Central Processing Unit (CPU), a Field Programmable Gate Array (FPGA), a Digital Signal Processor (DSP), an embedded neural Network Processor (NPU), and a hardware accelerator;

the memory includes: one or more of RAM, ROM and Flash.

9. A chip verification platform, the chip verification platform comprising: a chip to be tested and the platform chip of any one of claims 1-8;

10. The chip verification platform of claim 9, further comprising: connecting a chip externally;