CN106897114B - A kind of digital analog interface and its driving method of the real-time simulator based on FPGA - Google Patents
A kind of digital analog interface and its driving method of the real-time simulator based on FPGA Download PDFInfo
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- CN106897114B CN106897114B CN201710101014.6A CN201710101014A CN106897114B CN 106897114 B CN106897114 B CN 106897114B CN 201710101014 A CN201710101014 A CN 201710101014A CN 106897114 B CN106897114 B CN 106897114B
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45504—Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators
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- G06F13/40—Bus structure
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Abstract
The embodiment provides the digital analog interfaces and its driving method of a kind of real-time simulator based on FPGA, it is related to real-time simulator technical field, solves the problems, such as that the interface generality between real-time simulator in the prior art and between real-time simulator and external equipment is lower, information exchange speed is lower.The digital analog interface, including, dual rate random access memory, floating number fixed-point number conversion module, digital-to-analogue conversion board, the first register, the second register and address generation module.Manufacture of the embodiment of the present invention for the digital analog interface of real-time simulator.
Description
Technical field
The present invention relates to real-time simulator technical fields more particularly to a kind of digital-to-analogue of the real-time simulator based on FPGA to connect
Mouth and its driving method.
Background technique
In recent years, as distributed power generation and micro-capacitance sensor technology, flexible AC distribution technique and intelligence match multiplexe electric technology
Continuous development and application, power distribution network is changed into multi-source complication system by traditional passive network, and dynamic process is also because numerous new
Element, new technology addition and become more complicated, it is all in many ways in planning and designing, traffic control, control protection, simulation analysis etc.
Face is faced with bigger challenge, therefore, it is necessary to understand the operation of active power distribution network in depth by accurately and efficiently transient emulation
Mechanism and behavioral characteristics.
Different from offline electromagnetic transient simulation, the temporary of more truly simulation system is capable of in active power distribution network real-time simulation
State process, and have the ability of hardware-in-loop simulation, by real-time simulator is connected with actual physical device can carry out it is various
The exploitation and test job of control and protection device, both can with illumination simulation and wind speed variation, Voltage Drop, short trouble, get rid of
Active power distribution network complexity transient process under a variety of Run-time scenarios such as load, and research and development and experimentation cost can be effectively reduced, it keeps away
Exempt from influence of the Devices to test to real system, therefore, active power distribution network planning and designing, Optimized Operation, fault automatic location and
Removing, network self-healing, frequency analysis, actual physics system test with verifying etc. play an important role.
Currently, include real-time digital simulator (full name in English: Real Time Digital Simulator, referred to as:
RTDS), all-digital real-time simulation device (full name in English: Hypersim The Fully Digital Real-Time
Commercialization real-time simulator including Simulator, referred to as: HYPERSIM) etc. is in Operation of Electric Systems and protection, distributed
The fields such as power-supply controller of electric design, power electronics equipment research and development have been widely used, the continuous increasing of active power distribution network scale
The device models such as big and distributed generation resource it is increasingly sophisticated, in the prior art between real-time simulator and real-time simulator and outside
The interface generality of portion's equipment room is lower, information exchange speed is lower, and how to improve between real-time simulator and real-time
The speed of interface generality, information exchange between emulator and external equipment becomes a urgent problem to be solved.
Summary of the invention
The embodiment provides the digital analog interface and its driving method of a kind of real-time simulator based on FPGA, solutions
The interface generality determined between real-time simulator in the prior art and between real-time simulator and external equipment is lower, information is handed over
The lower problem of mutual speed.
In order to achieve the above objectives, the embodiment of the present invention adopts the following technical scheme that
First aspect, the embodiment of the present invention provide a kind of digital analog interface of real-time simulator based on FPGA, comprising: double speed
Rate random access memory, floating number fixed-point number conversion module, address conversion module and digital-to-analogue conversion board；
The output end of real-time simulator of the input terminal connection based on FPGA of floating number fixed-point number conversion module, floating number are fixed
The input terminal of the output end connection dual rate random access memory of points conversion module；
The input terminal connection floating number fixed-point number conversion module and address conversion module of dual rate random access memory,
The output end of dual rate random access memory connects digital-to-analogue conversion plate card；
Address conversion module input terminal connection the real-time simulator based on FPGA output end, address conversion module it is defeated
The input terminal of outlet connection dual rate random access memory；
Digital-to-analogue conversion board input terminal connection dual rate random access memory output end, digital-to-analogue conversion board it is defeated
Analog machine outside outlet connection；
Wherein,
Real-time simulator based on FPGA, for generating driving clock clk-sim, the digital-to-analogue of real-time simulator in FPGA
Convert the driving clock clk-da of the board and enable signal oe-da of digital-to-analogue conversion board；And it is initialized before emulation starts
The simulation parameter of real-time simulator based on FPGA is generated in each simulation step length and is corresponded to according to the simulation parameter of initialization
The simulation result out-ch of 64 double-precision floating points forms of the step-length；
Floating number fixed-point number conversion module, 64 double-precision floating points for will be exported based on the real-time simulator of FPGA
The simulation result out-ch of form is converted to the simulation result da-input of 64 fixed-point number forms；
Dual rate random access memory, for according to the writing address signal addr-w in driving clock clk-sim, storage
The simulation result da-input of 64 fixed-point number forms of floating number fixed-point number conversion module conversion；
Address conversion module, for the writing address signal addr-w in clock clk-sim will to be driven to be converted to driving clock
Read address signal addr-r in clk-da；
Dual rate random access memory, the read address signal addr-r for being generated according to address conversion module read 64
The simulation result da-input of position fixed-point number form, and will be in the simulation result da-input of 64 fixed-point number forms of reading
N to N-M+1 are converted to the simulation result da-out of M offset binary codes, in the digital-to-analogue conversion board being output to；
The simulation result da- for continuing working state and exporting M offset binary codes is according to enable signal oe-da
The corresponding analog signal of out is to external analog machine.
Specifically, initializing simulation parameter before emulation starts, comprising:
The simulation type of real-time simulator output based on FPGA, and the value of the output data according to simulation type are set
The cut position ginseng of the digital analog interface of the real-time simulator of range and the setting of the digit of digital-to-analogue conversion plate card digital signal end based on FPGA
Number N and M；
It is clk-sim by the clock setting of writing of dual rate random access memory, and by dual rate random access memory
Write address be set as recurrent state；
Real-time simulator starting emulation based on FPGA is set, simulation time t=0 is initialized；And when default emulation is set
Long TN and simulation time step delta t；Wherein, when tested between t when being equal to default emulation duration TN, stop the reality based on FPGA
When emulator emulation, TN be greater than Δ t, Δ t be greater than 0.
Specifically, initializing simulation parameter before emulation starts, comprising: the emulation for generating real-time simulator in FPGA is opened
Beginning signal sta；
Address conversion module includes: the first register, the second register and address generation module；
The output end of real-time simulator of the input terminal connection based on FPGA of first register, the output end of the first register
Connect the input terminal of the second register；
The input terminal of second register connects the output end of the first register, and the output end link address of the second register is raw
At the input terminal of module；
The input terminal of address generation module connects the output end of the second register, and the output end connection of address generation module is double
The input terminal of Rate Random Access memory；
Wherein,
First register, for being believed according to the write address in the selected current driving clock clk-sim of emulation commencing signal sta
Number addr-w；
Second register, the writing address signal addr-w in driving clock clk-sim for selecting the first register
The ini_addr_r signal being converted into the clock domain of driving clock clk-sim；
Address generation module, the ini_ in the clock domain for driving clock clk-sim for generating the second register
Addr_r signal is assigned to the read address signal addr-r in the driving clock clk-da of digital-to-analogue conversion board.
Second aspect, the embodiment of the present invention provide a kind of real-time simulation of any one based on FPGA provided such as first aspect
The driving method of the digital analog interface of device, comprising:
Generate driving clock clk-sim, driving clock clk-da and enable signal oe-da；
Simulation parameter is initialized before emulation starts, and according to the simulation parameter of initialization, it is raw in each simulation step length
In pairs should step-length 64 double-precision floating points forms simulation result out-ch；
The simulation result out-ch of 64 double-precision floating points forms is converted to the simulation result of 64 fixed-point number forms
da-input；
According to the writing address signal addr-w in driving clock clk-sim, the simulation result of 64 fixed-point number forms is stored
da-input；
The writing address signal addr-w in clock clk-sim will be driven to be converted to the read address letter in driving clock clk-da
Number addr-r；
The simulation result da-input of 64 fixed-point number forms is read according to read address signal addr-r, and by the 64 of reading
N in the simulation result da-input of position fixed-point number form are converted to the emulation of M offset binary codes to N-M+1
As a result da-out；
The simulation result da- for continuing working state and exporting M offset binary codes is according to enable signal oe-da
The corresponding analog signal of out.
Specifically,
Simulation parameter is initialized before emulation starts, comprising:
Simulation type is set, and according to section of the value range of the output data of simulation type and digit setting digital analog interface
Position parameter N and M；
It is clk-sim by the clock setting of writing of digital analog interface, and sets recurrent state for the write address of digital analog interface；
Starting emulation, initializes simulation time t=0；And default emulation duration TN and simulation time step delta t is set；
Wherein, when tested between t when being equal to default emulation duration TN, stop emulation, TN is greater than Δ t, and Δ t is greater than 0.
Specifically,
Simulation parameter is initialized before emulation starts, comprising: generates emulation commencing signal sta；
The writing address signal addr-w in clock clk-sim will be driven to be converted to the read address letter in driving clock clk-da
Number addr-r, comprising:
According to the writing address signal addr-w in the selected current driving clock clk-sim of emulation commencing signal sta；
The writing address signal addr-w in clock clk-sim will be driven to be converted into the clock domain of driving clock clk-sim
Ini_addr_r signal；
Ini_addr_r signal in the clock domain for driving clock clk-sim is assigned to the reading in driving clock clk-da
Address signal addr-r.
The digital analog interface and its driving method of real-time simulator provided in an embodiment of the present invention based on FPGA, pass through utilization
FPGA generates the driving clock clk-sim of real-time simulator, the driving clock clk-da of digital-to-analogue conversion board and digital-to-analogue conversion
The enable signal oe-da of board；And the simulation parameter of the real-time simulator based on FPGA is initialized before emulation starts, according to first
The simulation parameter of beginningization generates the simulation result of 64 double-precision floating points forms of the corresponding step-length in each simulation step length
Out-ch ensure that the versatility of output result；The driving clock clk-sim of real-time simulator is turned using address conversion module
It is changed to the driving clock clk-da of digital-to-analogue conversion board；The unification to real-time simulator and digital-to-analogue conversion board time domain is realized,
It ensure that the real-time of the simulation result of output；Dual rate random access memory writes ground according in driving clock clk-sim
Location signal addr-w, reads the simulation result da-input of 64 fixed-point number forms, and by 64 fixed-point number forms of reading
N to N-M+1 in simulation result da-input are converted to the simulation result da-out of M offset binary codes, warp
By digital-to-analogue conversion board by the corresponding analog signal output of simulation result da-out of M offset binary codes to the mould to outside
Propose it is standby, the digital analog interface of the real-time simulator provided in an embodiment of the present invention based on FPGA given full play to FPGA interface money
Source advantage and the parallel technical advantage of hardware configuration, in the communication speed and versatility for guaranteeing the digital analog interface of real-time simulator
Meanwhile realizing real-time simulator simulation result high speed, effective output；To solve in the prior art real-time simulator it
Between and interface generality between real-time simulator and external equipment is lower, information exchange speed is lower problem.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
It obtains other drawings based on these drawings.
Fig. 1 is the structural schematic diagram of the digital analog interface of the real-time simulator provided in an embodiment of the present invention based on FPGA；
Fig. 2 is the digital analog interface another kind structural representation of the real-time simulator provided in an embodiment of the present invention based on FPGA
Figure；
Fig. 3 is the driving method signal of the digital analog interface of the real-time simulator provided in an embodiment of the present invention based on FPGA
Figure；
Fig. 4 is the active power distribution network structural schematic diagram of the photovoltaic generating system containing monopole；
Fig. 5 is the simulation result schematic diagram that photovoltaic generating system exports electric current；
Fig. 6 is the oscilloscope display result schematic diagram that photovoltaic generating system exports electric current；
Fig. 7 is the simulation result schematic diagram that photovoltaic generating system exports faulted phase voltage；
Fig. 8 is the oscilloscope display result schematic diagram of photovoltaic generating system faulted phase voltage.
Appended drawing reference:
The digital analog interface -10 of real-time simulator based on FPGA；
Dual rate random access memory -101；
Floating number fixed-point number conversion module -102；
Address conversion module -103；First register -1030；Second register -1031；Address generation module -1032；
Digital-to-analogue conversion board -104.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
Embodiment one, the embodiment of the present invention provide a kind of based on field programmable gate array (full name in English: Field-
Programmable Gate Array, referred to as: FPGA) real-time simulator digital analog interface 10, as shown in Figure 1 include: double speed
Rate random access memory 101, floating number fixed-point number conversion module 102, address conversion module 103 and digital-to-analogue conversion board
104。
The input terminal connection floating number fixed-point number conversion module 102 of dual rate random access memory 101 and address turn
Block 103 is changed the mold, the output end of dual rate random access memory 101 connects digital-to-analogue conversion plate card 104.
The output end of real-time simulator 10 of the input terminal connection based on FPGA of floating number fixed-point number conversion module 102, is floated
The input terminal of the output end connection dual rate random access memory 101 of points fixed-point number conversion module 102.
The output end of real-time simulator 10 of the input terminal connection based on FPGA of address conversion module 103, address conversion mould
The input terminal of the output end connection dual rate random access memory 101 of block 103.
The output end of the input terminal connection dual rate random access memory 101 of digital-to-analogue conversion board 104, digital-to-analogue conversion plate
Analog machine outside the output end connection of card 104.
Wherein,
Real-time simulator 10 based on FPGA, for generating driving clock clk-sim, the number of real-time simulator in FPGA
Mould converts the driving clock clk-da of the board 1030 and enable signal oe-da of digital-to-analogue conversion board 104；And start in emulation
The simulation parameter of preceding real-time simulator of the initialization based on FPGA, according to the simulation parameter of initialization, in each simulation step length
Generate the simulation result out-ch of 64 double-precision floating points forms of the corresponding step-length.
Floating number fixed-point number conversion module 102, for floating 64 double precisions of the real-time simulator output based on FPGA
The simulation result out-ch of points form is converted to the simulation result da-input of 64 fixed-point number forms.
Dual rate random access memory 101, for according to driving clock clk-sim in writing address signal addr-w,
Store the simulation result da-input for 64 fixed-point number forms that floating number fixed-point number conversion module 102 is converted.
Address conversion module 103, when for the writing address signal addr-w in clock clk-sim will to be driven to be converted to driving
Read address signal addr-r in clock clk-da.
Dual rate random access memory 101, the read address signal addr-r for being generated according to address conversion module 103
Read the simulation result da-input of 64 fixed-point number forms, and by the simulation result da- of 64 fixed-point number forms of reading
N to N-M+1 in input are converted to the simulation result da-out of M offset binary codes.
Digital-to-analogue conversion board 104 continues working state for being according to enable signal oe-da, and exports M offsets two
The corresponding analog signal of simulation result da-out of ary codes is to external analog machine.
The digital analog interface of real-time simulator provided in an embodiment of the present invention based on FPGA, it is real-time by being generated using FPGA
Driving clock clk-sim, the driving clock clk-da of digital-to-analogue conversion board and the enabled letter of digital-to-analogue conversion board of emulator
Number oe-da；And the simulation parameter of the real-time simulator based on FPGA is initialized before emulation starts, joined according to the emulation of initialization
Number generates the simulation result out-ch of 64 double-precision floating points forms of the corresponding step-length in each simulation step length, guarantees
The versatility of output result；The driving clock clk-sim of real-time simulator digital-to-analogue is converted to using address conversion module to turn
Change the driving clock clk-da of board；The unification to real-time simulator and digital-to-analogue conversion board time domain is realized, ensure that output
Simulation result real-time；Dual rate random access memory is according to the writing address signal addr- in driving clock clk-sim
W, reads the simulation result da-input of 64 fixed-point number forms, and by the simulation result da- of 64 fixed-point number forms of reading
N to N-M+1 in input are converted to the simulation result da-out of M offset binary codes, via digital-to-analogue conversion plate
Card is by the corresponding analog signal output of simulation result da-out of M offset binary codes to the analog machine to outside, this hair
The digital analog interface for the real-time simulator based on FPGA that bright embodiment provides has given full play to the interface resource advantage of FPGA and hard
The parallel technical advantage of part structure is realized while guaranteeing the communication speed and versatility of digital analog interface of real-time simulator
Real-time simulator simulation result high speed, effective output；To solve between real-time simulator in the prior art and real
When emulator and external equipment between interface generality is lower, problem that information exchange speed is lower.
Embodiment two, the present invention implement to provide a kind of digital analog interface 10 based on FPGA, include: as shown in Figure 2
Dual rate random access memory 101, floating number fixed-point number conversion module 102, the first register 1030, second are posted
Storage 1031, address generation module 1032 and digital-to-analogue conversion board 104.
Wherein, the input terminal connection floating number fixed-point number conversion module 102 and ground of dual rate random access memory 101
The output end of location generation module 1032, dual rate random access memory 101 connects digital-to-analogue conversion plate card 104.
The output end of real-time simulator of the input terminal connection based on FPGA of floating number fixed-point number conversion module 102, floating-point
The input terminal of the output end connection dual rate random access memory 101 of number fixed-point number conversion module 102.
The output end of real-time simulator 10 of the input terminal connection based on FPGA of first register 1030, the first register
1030 output end connects the input terminal of the second register 1031.
The input terminal of second register 1031 connects the output end of the first register 1030, the output of the second register 1031
Hold the input terminal of link address generation module 1032.
The input terminal of address generation module 1032 connects the output end of the second register 1031, address generation module 1032
The input terminal of output end connection dual rate random access memory 101.
The output end of the input terminal connection dual rate random access memory 101 of digital-to-analogue conversion board 104, digital-to-analogue conversion plate
Analog machine outside the output end connection of card 104.
Wherein,
Real-time simulator 10 based on FPGA, for generating driving clock clk-sim, the number of real-time simulator in FPGA
Mould converts the enable signal oe-da and emulation commencing signal of the driving clock clk-da of board 1030, digital-to-analogue conversion board 104
sta；And the simulation parameter of the real-time simulator based on FPGA is initialized before emulation starts, according to the simulation parameter of initialization,
The simulation result out-ch of 64 double-precision floating points forms of the corresponding step-length is generated in each simulation step length.
Floating number fixed-point number conversion module 102, for floating 64 double precisions of the real-time simulator output based on FPGA
The simulation result out-ch of points form is converted to the simulation result da-input of 64 fixed-point number forms.
Dual rate random access memory 101, for according to driving clock clk-sim in writing address signal addr-w,
Store the simulation result da-input for 64 fixed-point number forms that floating number fixed-point number conversion module 102 is converted.
First register 1030, for writing ground according in the selected current driving clock clk-sim of emulation commencing signal sta
Location signal addr-w.
Second register 1031, the write address in driving clock clk-sim for selecting the first register 1030 are believed
Number addr-w is converted into the ini_addr_r signal in the clock domain of driving clock clk-sim.
Address generation module 1032, for by the second register 1031 generate driving clock clk-sim clock domain in
Ini_addr_r signal be assigned to digital-to-analogue conversion board driving clock clk-da in read address signal addr-r.
Dual rate random access memory 101, the read address signal addr- for being generated according to address generation module 1032
R reads the simulation result da-input of 64 fixed-point number forms, and by the simulation result da- of 64 fixed-point number forms of reading
N to N-M+1 in input are converted to the simulation result da-out of M offset binary codes.
Digital-to-analogue conversion board 104 continues working state for being according to enable signal oe-da, and exports M offsets two
The corresponding analog signal of simulation result da-out of ary codes is to external analog machine.
Specifically, initializing simulation parameter before emulation starts, comprising:
The simulation type that real-time simulator 10 based on FPGA exports, and taking according to the output data of simulation type are set
It is worth the digital analog interface of real-time simulator 10 of the digit setting based on FPGA of range and 104 digital signal end of digital-to-analogue conversion plate card
Cut position parameter N and M.
It is clk-sim by the clock setting of writing of dual rate random access memory 101, and by dual rate random access storage
The write address of device 101 is set as recurrent state.
It needs, the write address of dual rate random access memory is arranged to recurrent state here, can make
The simulation result of real-time simulator output based on FPGA is constantly written in dual rate random access memory.
The starting emulation of real-time simulator 10 based on FPGA is set, simulation time t=0 is initialized；And default emulation is set
Duration TN and simulation time step delta t；Wherein, when tested between t when being equal to default emulation duration TN, stop based on FPGA's
The emulation of real-time simulator 10, TN are greater than Δ t, and Δ t is greater than 0.
The digital analog interface of real-time simulator provided in an embodiment of the present invention based on FPGA, it is real-time by being generated using FPGA
Driving clock clk-sim, the driving clock clk-da of digital-to-analogue conversion board and the enabled letter of digital-to-analogue conversion board of emulator
Number oe-da；And the simulation parameter of the real-time simulator based on FPGA is initialized before emulation starts, joined according to the emulation of initialization
Number generates the simulation result out-ch of 64 double-precision floating points forms of the corresponding step-length in each simulation step length, guarantees
The versatility of output result；It is synchronous with the second register progress clock using the first register, by the driving of real-time simulator
The problem of clock clk-sim is converted to the driving clock clk-da of digital-to-analogue conversion board, avoids the occurrence of timing, then passes through address
When ini_addr_r signal in the clock domain for driving clock clk-sim is assigned to the driving of digital-to-analogue conversion board by generation module
Read address signal addr-r in clock clk-da realizes the unification to real-time simulator and digital-to-analogue conversion board time domain, guarantees
The real-time of the simulation result of output；Dual rate random access memory is believed according to the write address in driving clock clk-sim
Number addr-w, reads the simulation result da-input of 64 fixed-point number forms, and by the emulation of 64 fixed-point number forms of reading
As a result N to N-M+1 in da-input are converted to the simulation result da-out of M offset binary codes, via number
Mould converts board and sets the corresponding analog signal output of simulation result da-out of M offset binary codes to external simulation
Standby, the interface resource that the digital analog interface of the real-time simulator provided in an embodiment of the present invention based on FPGA has given full play to FPGA is excellent
Gesture and the parallel technical advantage of hardware configuration, in the same of the communication speed and versatility for guaranteeing the digital analog interface of real-time simulator
When, realize real-time simulator simulation result high speed, effective output；To solve between real-time simulator in the prior art
And the problem that interface generality between real-time simulator and external equipment is lower, information exchange speed is lower.
Embodiment three, the embodiment of the present invention provide a kind of driving side of the digital analog interface of real-time simulator based on FPGA
Method includes: as shown in Figure 3
S101, driving clock clk-sim, driving clock clk-da and enable signal oe-da are generated.
S102, simulation parameter is initialized before emulation starts, and according to the simulation parameter of initialization, generate 64 double precisions
The simulation result out-ch of floating number form.
It should be noted that the simulation result of the emulator output based on FPGA is in actual application as shown in Figure 2
It is indicated with out-ch.
S103, the emulation that the simulation result out-ch of 64 double-precision floating points forms is converted to 64 fixed-point number forms
As a result da-input.
S104, according to driving clock clk-sim in writing address signal addr-w, store the emulation of 64 fixed-point number forms
As a result da-input.
S105, the writing address signal addr-w in clock clk-sim will be driven to be converted to the reading in driving clock clk-da
Address signal addr-r.
S106, the simulation result da-input that 64 fixed-point number forms are read according to read address signal addr-r, and will read
N to N-M+1 in the simulation result da-input of the 64 fixed-point number forms taken are converted to M offset binary codes
Simulation result da-out.
It should be noted that as shown in Figure 2 via digital-to-analogue conversion board by the simulation result da- of M offset binary codes
Analog machine of the corresponding analog signal output of out to extremely outside.
S107, the simulation result for continuing working state and exporting M offset binary codes is according to enable signal oe-da
The corresponding analog signal of da-out.
It should be noted that the active power distribution network of the photovoltaic generating system containing monopole as shown in Figure 4, executes FPGA development board
For A Ertela (full name in English: Altera) company530 official's development board of IV GX FPGA；Development board is furnished with
Stratix IV Series FPGA EP4SGX530KH40C2N, the chip include 744 I/O；Test digital-to-analogue conversion plate card model
DAC900, resolution ratio are 10, and highest supports the conversion rate of 165MHz；The model Tyke MDO3104 of test scope, most
Height supports the signal sampling rate of 2GS/s.
Test example is the active power distribution network containing photovoltaic generating system, and simulation step length is set as 3 μ s, as shown in Figure 4.In photovoltaic
In generator unit, inverter is controlled using Vdc, and photovoltaic voltage reference value Vref is provided in the form of constant.Temperature setting in example
It is set as 350V for 298K, Vref, Qref is set as 0Var.Power supply and transformer are using the source-series constant impedance simulation of voltage.
Fpga chip is driven by the global clock of 100MHz, is multiplied to 135MHz by phase-locked loop pll and is inputted simulation and calculation
Part, and logarithmic mode change-over panel card is driven；The simulation result of real-time simulator via development board high speed intermediary interface the end B
Mouth is input in the digital-to-analogue conversion board of 10 bit resolutions, and board conversion rate is set as 135MHz, straight eventually by oscillograph
Display simulation result is connect, the sample rate of oscillograph is set as 25kS/s.Identical example is built and is imitated in PSCAD/EMTDC
Very, wherein the simulation step length of real-time simulator and PSCAD/EMTDC are set as 3 μ s, simulation time 4s.
In order to verify real-time simulator digital analog interface accuracy and validity, simulating scenes consider photovoltaic power generation system
The case where system output pulsation and singlephase earth fault.Wherein, under output pulsation scene, photovoltaic is sent out when emulation proceeds to 1.5s
The intensity of illumination of electric system input increases suddenly；Under fault scenes, C occurs when emulation proceeds to 1.5s at photovoltaic system outlet
Phase ground short circuit failure, failure removal after 0.2s, failure are simulated by breaker.Simulation result and PSCAD/EMTDC are imitated
It is true to compare, and synchronism output has carried out real-time display and analysis to oscillograph.
Fig. 5 gives under output pulsation scene, the real-time simulator based on FPGA and business electromagnetic transient simulation software (English
Literary full name: Power Systems Computer Aided Design, referred to as: PSCAD)/(full name in English: Electro-
Magnetic Transient in DC System, abbreviation EMTDC) in photovoltaic generating system output current simulations as a result, figure
6 give the current simulations result of the real-time simulator output shown in corresponding oscillograph；Fig. 7 gives under fault scenes,
The voltage simulation result of photovoltaic generating system output, Fig. 8 in real-time simulator and business software PSCAD/EMTDC based on FPGA
Give the faulted phase voltage waveform of the real-time simulator output shown in corresponding oscillograph.From Fig. 5 and Fig. 6 and Fig. 7 and Fig. 8
Comparison as can be seen that the voltage and current signal different for variation range, real-time simulator are realized and are connect by digital-to-analogue
Mouth is effective, high speed by simulation result to be output in external physical equipment, to demonstrate the active power distribution network based on FPGA
The correctness and validity of the digital analog interface of real-time simulator.
Specifically,
Simulation parameter is initialized before emulation starts, comprising:
Simulation type is set, and according to section of the value range of the output data of simulation type and digit setting digital analog interface
Position parameter N and M.
It is clk-sim by the clock setting of writing of digital analog interface, and sets recurrent state for the write address of digital analog interface.
Starting emulation, initializes simulation time t=0；And default emulation duration TN and simulation time step delta t is set；
Wherein, when tested between t when being equal to default emulation duration TN, stop emulation, TN is greater than Δ t, and Δ t is greater than 0.
Specifically,
Simulation parameter is initialized before emulation starts, comprising: generates emulation commencing signal sta.
The writing address signal addr-w in clock clk-sim will be driven to be converted to the read address letter in driving clock clk-da
Number addr-r, comprising:
According to the writing address signal addr-w in the selected current driving clock clk-sim of emulation commencing signal sta.
The writing address signal addr-w in clock clk-sim will be driven to be converted into the clock domain of driving clock clk-sim
Ini_addr_r signal.
Ini_addr_r signal in the clock domain for driving clock clk-sim is assigned to the reading in driving clock clk-da
Address signal addr-r.
The driving method of the digital analog interface of real-time simulator provided in an embodiment of the present invention based on FPGA is driven by generating
Dynamic clock clk-sim, driving clock clk-da and enable signal oe-da；And simulation parameter, root are initialized before emulation starts
According to the simulation parameter of initialization, the emulation of 64 double-precision floating points forms of the corresponding step-length is generated in each simulation step length
As a result out-ch ensure that the versatility of output result；Driving clock clk-sim is converted into driving clock clk-da, is realized
Unification to real-time simulator and digital-to-analogue conversion board time domain, ensure that the real-time of the simulation result of output；According to driving
Writing address signal addr-w in clock clk-sim reads the simulation result da-input of 64 fixed-point number forms, and will read
64 fixed-point number forms simulation result da-input in N to N-M+1 be converted to M offset binary codes
Da-out arrives the corresponding analog signal output of simulation result da-out of M offset binary codes via digital-to-analogue conversion board
To external analog machine, the driving method of the digital analog interface of the real-time simulator provided in an embodiment of the present invention based on FPGA,
The digital analog interface that the real-time simulator based on FPGA can effectively be driven has given full play to the interface resource advantage of FPGA and hard
The parallel technical advantage of part structure is realized while guaranteeing the communication speed and versatility of digital analog interface of real-time simulator
Real-time simulator simulation result high speed, effective output；To solve between real-time simulator in the prior art and real
When emulator and external equipment between interface generality is lower, problem that information exchange speed is lower.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can easily think of the change or the replacement, and should all contain
Lid is within protection scope of the present invention.Therefore, protection scope of the present invention should be based on the protection scope of the described claims.
Claims (6)
1. a kind of digital analog interface of the real-time simulator based on FPGA characterized by comprising dual rate random access storage
Device, floating number fixed-point number conversion module, digital-to-analogue conversion board and address conversion module；
The input terminal of the floating number fixed-point number conversion module connects the output end of the real-time simulator based on FPGA, described
The output end of floating number fixed-point number conversion module connects the input terminal of the dual rate random access memory；
The input terminal of the dual rate random access memory connects the floating number fixed-point number conversion module and the address
The output end of conversion module, the dual rate random access memory connects the digital-to-analogue conversion board；
The input terminal of the address conversion module connects the output end of the real-time simulator based on FPGA, the address conversion
The output end of module connects the input terminal of the dual rate random access memory；
The input terminal of the digital-to-analogue conversion board connects the output end of the dual rate random access memory, the digital-to-analogue conversion
Analog machine outside the output end connection of board；
Wherein,
The real-time simulator based on FPGA, for generating the driving clock clk- of the real-time simulator in the FPGA
Sim, the driving clock clk-da of the digital-to-analogue conversion board and the enable signal oe-da of the digital-to-analogue conversion board；And
Emulation initializes the simulation parameter of the real-time simulator based on FPGA before starting, according to the simulation parameter of the initialization,
The simulation result out-ch of 64 double-precision floating points forms of the corresponding step-length is generated in each simulation step length；
The floating number fixed-point number conversion module, for double smart by described 64 of the real-time simulator output based on FPGA
The simulation result out-ch of degree floating number form is converted to the simulation result da-input of 64 fixed-point number forms；
The dual rate random access memory, for according to it is described driving clock clk-sim in writing address signal addr-w,
Store the simulation result da-input of 64 fixed-point number forms of the floating number fixed-point number conversion module conversion；
The address conversion module, it is described for being converted to the writing address signal addr-w in the driving clock clk-sim
Drive the read address signal addr-r in clock clk-da；
The dual rate random access memory, the read address signal for being generated according to the address conversion module
Addr-r reads the simulation result da-input of 64 fixed-point number forms, and by 64 fixed-point number forms of reading
N to N-M+1 in simulation result da-input are converted to the simulation result da-out of M offset binary codes, defeated
Out into the digital-to-analogue conversion board；
The digital-to-analogue conversion board continues working state for being according to the enable signal oe-da, and exports M described
To the analog machine of the outside, the N and the M are the corresponding analog signal of simulation result da-out of offset binary code
The cut position parameter of the digital analog interface of the real-time simulator based on FPGA.
2. the digital analog interface of the real-time simulator according to claim 1 in FPGA, which is characterized in that
It is described to initialize simulation parameter before emulation starts, comprising:
The simulation type of the real-time simulator output based on FPGA is set, and according to the output data of the simulation type
The digital-to-analogue of the real-time simulator based on FPGA is arranged in value range and the digit of the digital-to-analogue conversion board digital signal end
Cut position the parameter N and M of interface；
It is clk-sim by the clock setting of writing of the dual rate random access memory, and the dual rate arbitrary access is deposited
The write address of storage is set as recurrent state；
The real-time simulator starting emulation based on FPGA is set, simulation time t=0 is initialized；And when default emulation is set
Long TNAnd simulation time step delta t；Wherein, when tested between t be equal to the default emulation duration TNWhen, it is based on described in stopping
The emulation of the real-time simulator of FPGA, TNIt is greater than 0 greater than Δ t, Δ t.
3. the digital analog interface of the real-time simulator according to claim 1 in FPGA, which is characterized in that
It is described to initialize simulation parameter before emulation starts, comprising: the emulation of the real-time simulator is generated in the FPGA
Commencing signal sta；
The address conversion module includes: the first register, the second register and address generation module；
The input terminal of first register connects the output end of the real-time simulator based on FPGA, first register
Output end connect the input terminal of second register；
The input terminal of second register connects the output end of first register, and the output end of second register connects
Connect the input terminal of the address generation module；
The input terminal of the address generation module connects the output end of second register, the output of the address generation module
End connects the input terminal of the dual rate random access memory；
Wherein,
First register, for being selected in presently described driving clock clk-sim according to the emulation commencing signal sta
Writing address signal addr-w；
Second register, the write address in the driving clock clk-sim for selecting first register are believed
Number addr-w is converted into the ini_addr_r signal in the clock domain of the driving clock clk-sim；
The address generation module, in the clock domain of the driving clock clk-sim for generating second register
Ini_addr_r signal be assigned to the digital-to-analogue conversion board driving clock clk-da in read address signal addr-r.
4. a kind of driving method of the digital analog interface of the real-time simulator as described in any one of claims 1-3 based on FPGA,
It is characterised by comprising:
Generate driving clock clk-sim, driving clock clk-da and enable signal oe-da；
Simulation parameter is initialized before emulation starts, and according to the simulation parameter of the initialization, it is raw in each simulation step length
In pairs should step-length 64 double-precision floating points forms simulation result out-ch；
The simulation result out-ch of 64 double-precision floating points forms is converted to the simulation result of 64 fixed-point number forms
da-input；
According to the writing address signal addr-w in driving clock clk-sim, the simulation result of 64 fixed-point number forms is stored
da-input；
With being converted to the reading in the driving clock clk-da by the writing address signal addr-w in the driving clock clk-sim
Location signal addr-r；
The simulation result da-input of 64 fixed-point number forms is read according to the read address signal addr-r, and will be read
64 fixed-point number forms simulation result da-input in N to N-M+1 be converted to M offset binaries
The simulation result da-out of code；
The simulation result for continuing working state and exporting the M offset binary code is according to the enable signal oe-da
The corresponding analog signal of da-out.
5. the driving method of the digital analog interface of the real-time simulator according to claim 4 based on FPGA, which is characterized in that
It is described to initialize simulation parameter before emulation starts, comprising:
Simulation type is set, and the digital analog interface is arranged according to the value range of the output data of the simulation type and digit
Cut position parameter N and M；
It is clk-sim by the clock setting of writing of the digital analog interface, and sets circulation shape for the write address of the digital analog interface
State；
Starting emulation, initializes simulation time t=0；And default emulation duration T is setNAnd simulation time step delta t；Wherein,
T is equal to the default emulation duration T between when testedNWhen, stop emulation, TNIt is greater than 0 greater than Δ t, Δ t.
6. the driving method of the digital analog interface of the real-time simulator according to claim 4 based on FPGA, which is characterized in that
It is described to initialize simulation parameter before emulation starts, comprising: to generate emulation commencing signal sta；
The writing address signal addr-w by the driving clock clk-sim is converted in the driving clock clk-da
Read address signal addr-r, comprising:
The writing address signal addr-w in presently described driving clock clk-sim is selected according to the emulation commencing signal sta；
Writing address signal addr-w in the driving clock clk-sim is converted into the clock domain of driving clock clk-sim
Ini_addr_r signal；
Ini_addr_r signal in the clock domain of the driving clock clk-sim is assigned in the driving clock clk-da
Read address signal addr-r.
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