CN106897114A - A kind of digital analog interface and its driving method of the real-time simulator based on FPGA - Google Patents
A kind of digital analog interface and its driving method of the real-time simulator based on FPGA Download PDFInfo
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Abstract
The embodiment provides a kind of digital analog interface and its driving method of the real-time simulator based on FPGA, it is related to real-time simulator technical field, solves the problems, such as between real-time simulator in the prior art and the interface generality between real-time simulator and external equipment is relatively low, information exchange speed is relatively low.The digital analog interface, including, dual rate random access memory (RAM), floating number fixed-point number modular converter, digital-to-analogue conversion board, the first register, the second register and address generation module.The embodiment of the present invention is used for the manufacture of the digital analog interface of real-time simulator.
Description
Technical field
Connect the present invention relates to real-time simulator technical field, more particularly to a kind of digital-to-analogue of the real-time simulator based on FPGA
Mouth and its driving method.
Background technology
In recent years, as distributed power generation and micro-capacitance sensor technology, flexible AC distribution technique and intelligence match somebody with somebody multiplexe electric technology
Continue to develop multi-source complication system be changed into by traditional passive network with application, power distribution network, its dynamic process is also because numerous new
Element, the addition of new technology and become more complicated, it is all in many ways in planning and designing, traffic control, control protection, simulation analysis etc.
Face is faced with bigger challenge, therefore, it is necessary to understand the operation of active power distribution network in depth by accurately and efficiently transient emulation
Mechanism and behavioral characteristics.
Different from offline electromagnetic transient simulation, the temporary of more truly simulation system is capable of in active power distribution network real-time simulation
State process, and possess the ability of hardware-in-loop simulation, can be carried out various by the way that real-time simulator is connected with actual physical device
Control and the exploitation and test job of protection device, both can with illumination simulation and wind speed change, Voltage Drop, short trouble, get rid of
Active power distribution network complexity transient process under various Run-time scenarios such as load, can effectively reduce research and development and experimentation cost again, keep away
Exempt from influence of the Devices to test to real system, therefore, active power distribution network planning and designing, Optimized Operation, fault automatic location and
Removing, network self-healing, frequency analysis, actual physics system test and checking etc. aspect play an important role.
At present, including real-time digital simulator (English full name：Real Time Digital Simulator, referred to as：
RTDS), all-digital real-time simulation device (English full name：Hypersim The Fully Digital Real-Time
Simulator, referred to as：) etc. HYPERSIM in interior commercialization real-time simulator in Operation of Electric Systems and protection, distributed
The fields such as power-supply controller of electric design, power electronics equipment research and development obtain a wide range of applications, the continuous increasing of active power distribution network scale
The device models such as big and distributed power source it is increasingly sophisticated, in the prior art between real-time simulator and real-time simulator and outward
The interface generality of portion's equipment room is relatively low, information exchange speed is relatively low, and how to improve between real-time simulator and in real time
The speed of interface generality, information exchange between emulator and external equipment, as a problem demanding prompt solution.
The content of the invention
The embodiment provides a kind of digital analog interface and its driving method of the real-time simulator based on FPGA, solution
Determine between real-time simulator in the prior art and the interface generality between real-time simulator and external equipment has been relatively low, information is handed over
The relatively low problem of mutual speed.
To reach above-mentioned purpose, embodiments of the invention are adopted the following technical scheme that：
First aspect, the embodiment of the present invention provide a kind of digital analog interface of the real-time simulator based on FPGA, including：Double speed
Rate random access memory (RAM), floating number fixed-point number modular converter, address conversion module and digital-to-analogue conversion board；
The output end of the input real-time simulator of the connection based on FPGA of floating number fixed-point number modular converter, floating number is fixed
The output end of points modular converter connects the input of dual rate random access memory (RAM)；
Input connection floating number fixed-point number modular converter and the address conversion module of dual rate random access memory (RAM),
The output end connection digital-to-analogue conversion board of dual rate random access memory (RAM)；
Address conversion module input connection based on FPGA real-time simulator output end, address conversion module it is defeated
Go out the input of end connection dual rate random access memory (RAM)；
The input of digital-to-analogue conversion board connects the output end of dual rate random access memory (RAM), digital-to-analogue conversion board it is defeated
The analog machine gone out outside the connection of end；
Wherein,
Real-time simulator based on FPGA, driving clock clk-sim, digital-to-analogue for generating real-time simulator in FPGA
Change the driving clock clk-da of the board and enable signal oe-da of digital-to-analogue conversion board；And initialized before emulation starts
The simulation parameter of the real-time simulator based on FPGA, according to the simulation parameter of initialization, generates correspondence in each simulation step length
The simulation result out-ch of 64 double-precision floating pointses forms of the step-length；
Floating number fixed-point number modular converter, for 64 double-precision floating pointses for exporting the real-time simulator based on FPGA
The simulation result out-ch of form is converted to 64 simulation result da-input of fixed-point number form；
Dual rate random access memory (RAM), for according to the writing address signal addr-w driven in clock clk-sim, storage
The simulation result da-input of 64 fixed-point number forms of floating number fixed-point number modular converter conversion；
Address conversion module, for the writing address signal addr-w in clock clk-sim will to be driven to be converted to driving clock
Reading address signal addr-r in clk-da；
Dual rate random access memory (RAM), the reading address signal addr-r for being generated according to address conversion module reads 64
The simulation result da-input of position fixed-point number form, and by the simulation result da-input of the 64 fixed-point number forms for reading
N to N-M+1 is converted to the M simulation result da-out of offset binary code, in the digital-to-analogue conversion board for exporting；
It is in continuous firing state and exports the M simulation result da- of offset binary code according to signal oe-da is enabled
The corresponding analog signals of out are to outside analog machine.
Specifically, simulation parameter is initialized before emulation starts, including：
Set based on FPGA real-time simulator export simulation type, and the output data according to simulation type value
The digit of scope and digital-to-analogue conversion plate card digital signal end sets the cut position ginseng of the digital analog interface of the real-time simulator based on FPGA
Number N and M；
Dual rate random access memory (RAM) is write into clock setting for clk-sim, and by dual rate random access memory (RAM)
Write address be set to recurrent state；
Real-time simulator based on FPGA is set and starts emulation, initialization simulation time t=0；And when default emulation is set
TN long and simulation time step delta t；Wherein, when tested between t when being equal to default emulation duration TN, stop the reality based on FPGA
When emulator emulation, TN be more than Δ t, Δ t be more than 0.
Specifically, simulation parameter is initialized before emulation starts, including：The emulation for generating real-time simulator in FPGA is opened
Beginning signal sta；
Address conversion module includes：First register, the second register and address generation module；
The output end of the input real-time simulator of the connection based on FPGA of the first register, the output end of the first register
Connect the input of the second register；
The input of the second register connects the output end of the first register, the output end link address life of the second register
Into the input of module；
The input of address generation module connects the output end of the second register, and the output end connection of address generation module is double
The input of Rate Random Access memory；
Wherein,
First register, for according to the selected current write address letters driven in clock clk-sim of emulation commencing signal sta
Number addr-w；
Second register, for the writing address signal addr-w driven in clock clk-sim for selecting the first register
It is converted into the ini_addr_r signals in the clock zone for driving clock clk-sim；
Address generation module, for the ini_ driven in the clock zone of clock clk-sim for generating the second register
Addr_r signals are assigned to the reading address signal addr-r driven in clock clk-da of digital-to-analogue conversion board.
Second aspect, the embodiment of the present invention provide the real-time simulation that a kind of any one provided such as first aspect is based on FPGA
The driving method of the digital analog interface of device, including：
Generation drives clock clk-sim, drives clock clk-da and enables signal oe-da；
Simulation parameter is initialized before emulation starts, and according to the simulation parameter of initialization, it is raw in each simulation step length
In pairs should step-length 64 double-precision floating pointses forms simulation result out-ch；
The simulation result out-ch of 64 double-precision floating pointses forms is converted into 64 simulation results of fixed-point number form
da-input；
According to the writing address signal addr-w driven in clock clk-sim, 64 simulation results of fixed-point number form are stored
da-input；
The writing address signal addr-w in clock clk-sim will be driven to be converted to the reading address letter driven in clock clk-da
Number addr-r；
64 simulation result da-input of fixed-point number form, and 64 for reading are read according to address signal addr-r is read
N to N-M+1 in the simulation result da-input of position fixed-point number form is converted to the M emulation of offset binary code
As a result da-out；
It is in continuous firing state and exports the M simulation result da- of offset binary code according to signal oe-da is enabled
The corresponding analog signals of out.
Specifically,
Simulation parameter is initialized before emulation starts, including：
Simulation type, and the span of output data according to simulation type and cutting for digit setting digital analog interface are set
Position parameter N and M；
Digital analog interface is write into clock setting for clk-sim, and the write address of digital analog interface is set to recurrent state；
Start emulation, initialization simulation time t=0；And default emulation duration TN and simulation time step delta t is set；
Wherein, when tested between t when being equal to default emulation duration TN, stop emulation, TN is more than Δ t, and Δ t is more than 0.
Specifically,
Simulation parameter is initialized before emulation starts, including：Generation emulation commencing signal sta；
The writing address signal addr-w in clock clk-sim will be driven to be converted to the reading address letter driven in clock clk-da
Number addr-r, including：
According to the selected current writing address signal addr-w driven in clock clk-sim of emulation commencing signal sta；
The writing address signal addr-w in clock clk-sim will be driven to be converted into the clock zone for driving clock clk-sim
Ini_addr_r signals；
Ini_addr_r signals in the clock zone for driving clock clk-sim are assigned to drive the reading in clock clk-da
Address signal addr-r.
The digital analog interface and its driving method of the real-time simulator based on FPGA provided in an embodiment of the present invention, by using
Driving clock clk-sim, the driving clock clk-da of digital-to-analogue conversion board of FPGA generation real-time simulators and digital-to-analogue conversion
The enable signal oe-da of board；And initialization is based on the simulation parameter of the real-time simulator of FPGA before emulation starts, according to first
The simulation parameter of beginningization, generated in each simulation step length to should step-length 64 simulation results of double-precision floating pointses form
Out-ch, it is ensured that the versatility of output result；The driving clock clk-sim of real-time simulator is turned using address conversion module
It is changed to the driving clock clk-da of digital-to-analogue conversion board；The unification to real-time simulator and digital-to-analogue conversion board time domain is realized,
Ensure that the real-time of the simulation result of output；Dual rate random access memory (RAM) writes ground in driving clock clk-sim
Location signal addr-w, 64 simulation result da-input of fixed-point number form of reading, and the 64 fixed-point number forms that will be read
N to N-M+1 in simulation result da-input is converted to the M simulation result da-out of offset binary code, warp
By digital-to-analogue conversion board by the M corresponding analog signal output of simulation result da-out of offset binary code to the mould to outside
Propose standby, the digital analog interface of the real-time simulator based on FPGA provided in an embodiment of the present invention has given full play to the interface money of FPGA
Source advantage and the parallel technical advantage of hardware configuration, are ensureing the communication speed and versatility of the digital analog interface of real-time simulator
Meanwhile, realize real-time simulator simulation result and at a high speed, effectively export；So as to solve in the prior art real-time simulator it
Between and the interface generality between real-time simulator and external equipment is relatively low, information exchange speed is relatively low problem.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
The accompanying drawing to be used needed for having technology description is briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can be with
Other accompanying drawings are obtained according to these accompanying drawings.
Fig. 1 is the structural representation of the digital analog interface of the real-time simulator based on FPGA provided in an embodiment of the present invention；
Fig. 2 is the digital analog interface another kind structural representation of the real-time simulator based on FPGA provided in an embodiment of the present invention
Figure；
Fig. 3 is that the driving method of the digital analog interface of the real-time simulator based on FPGA provided in an embodiment of the present invention is illustrated
Figure；
Fig. 4 is the active power distribution network structural representation containing monopole photovoltaic generating system；
Fig. 5 is the simulation result schematic diagram of photovoltaic generating system output current；
Fig. 6 is the oscilloscope display result schematic diagram of photovoltaic generating system output current；
Fig. 7 is the simulation result schematic diagram that photovoltaic generating system exports faulted phase voltage；
Fig. 8 is the oscilloscope display result schematic diagram of photovoltaic generating system faulted phase voltage.
Reference：
The digital analog interface -10 of the real-time simulator based on FPGA；
Dual rate random access memory (RAM) -101；
Floating number fixed-point number modular converter -102；
Address conversion module -103；First register -1030；Second register -1031；Address generation module -1032；
Digital-to-analogue conversion board -104.
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than whole embodiments.It is based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under the premise of creative work is not made
Embodiment, belongs to the scope of protection of the invention.
The embodiment one, embodiment of the present invention provides a kind of based on field programmable gate array (English full name：Field-
Programmable Gate Array, referred to as：The digital analog interface 10 of real-time simulator FPGA), includes as shown in Figure 1：Double speed
Rate random access memory (RAM) 101, floating number fixed-point number modular converter 102, address conversion module 103 and digital-to-analogue conversion board
104。
The input connection floating number fixed-point number modular converter 102 of dual rate random access memory (RAM) 101 and address turn
Mold changing block 103, the output end connection digital-to-analogue conversion board 104 of dual rate random access memory (RAM) 101.
The output end of the input real-time simulator 10 of the connection based on FPGA of floating number fixed-point number modular converter 102, floats
The input of the output end connection dual rate random access memory (RAM) 101 of points fixed-point number modular converter 102.
The output end of the input real-time simulator 10 of the connection based on FPGA of address conversion module 103, address conversion mould
The input of the output end connection dual rate random access memory (RAM) 101 of block 103.
The output end of the input connection dual rate random access memory (RAM) 101 of digital-to-analogue conversion board 104, digital-to-analogue conversion plate
Analog machine outside the output end connection of card 104.
Wherein,
Real-time simulator 10 based on FPGA, driving clock clk-sim, number for generating real-time simulator in FPGA
The driving clock clk-da of the mould conversion board 1030 and enable signal oe-da of digital-to-analogue conversion board 104；And start in emulation
The simulation parameter of preceding real-time simulator of the initialization based on FPGA, according to the simulation parameter of initialization, in each simulation step length
Generate to should step-length 64 double-precision floating pointses forms simulation result out-ch.
Floating number fixed-point number modular converter 102, for 64 double precisions that the real-time simulator based on FPGA is exported to be floated
The simulation result out-ch of points form is converted to 64 simulation result da-input of fixed-point number form.
Dual rate random access memory (RAM) 101, for the writing address signal addr-w in driving clock clk-sim,
The simulation result da-input of 64 fixed-point number forms of the conversion of storage floating number fixed-point number modular converter 102.
Address conversion module 103, during for the writing address signal addr-w in clock clk-sim will to be driven to be converted to driving
Reading address signal addr-r in clock clk-da.
Dual rate random access memory (RAM) 101, for the reading address signal addr-r generated according to address conversion module 103
Read 64 simulation result da-input of fixed-point number form, and will read 64 fixed-point number forms simulation result da-
N to N-M+1 in input is converted to the M simulation result da-out of offset binary code.
Digital-to-analogue conversion board 104, for being in continuous firing state according to enable signal oe-da, and exports M skew two
The corresponding analog signals of simulation result da-out of ary codes are to outside analog machine.
The digital analog interface of the real-time simulator based on FPGA provided in an embodiment of the present invention, it is real-time by using FPGA generations
The enable letter for driving clock clk-sim, the driving clock clk-da of digital-to-analogue conversion board and digital-to-analogue conversion board of emulator
Number oe-da；And initialization is based on the simulation parameter of the real-time simulator of FPGA before emulation starts, the emulation ginseng according to initialization
Number, generated in each simulation step length to should step-length 64 double-precision floating pointses forms simulation result out-ch, it is ensured that
The versatility of output result；The driving clock clk-sim of real-time simulator is converted into digital-to-analogue using address conversion module to turn
Change the driving clock clk-da of board；Realize the unification to real-time simulator and digital-to-analogue conversion board time domain, it is ensured that output
Simulation result real-time；Dual rate random access memory (RAM) is according to the writing address signal addr- driven in clock clk-sim
W, read 64 simulation result da-input of fixed-point number form, and will read 64 fixed-point number forms simulation result da-
N to N-M+1 in input is converted to the M simulation result da-out of offset binary code, via digital-to-analogue conversion plate
Block the M corresponding analog signal output of simulation result da-out of offset binary code to the analog machine to outside, this hair
The digital analog interface of the real-time simulator based on FPGA that bright embodiment is provided has given full play to the interface resource advantage of FPGA and hard
The parallel technical advantage of part structure, while the communication speed and versatility of digital analog interface of real-time simulator is ensured, realizes
Real-time simulator simulation result at a high speed, effective output；It is between real-time simulator in the prior art and real so as to solve
When the problem that interface generality is relatively low, information exchange speed is relatively low between emulator and external equipment.
Embodiment two, the present invention implement to provide a kind of digital analog interface 10 based on FPGA, include as shown in Figure 2：
Dual rate random access memory (RAM) 101, floating number fixed-point number modular converter 102, the first register 1030, second are posted
Storage 1031, address generation module 1032 and digital-to-analogue conversion board 104.
Wherein, the input connection floating number fixed-point number modular converter 102 and ground of dual rate random access memory (RAM) 101
Location generation module 1032, the output end connection digital-to-analogue conversion board 104 of dual rate random access memory (RAM) 101.
The output end of the input real-time simulator of the connection based on FPGA of floating number fixed-point number modular converter 102, floating-point
The input of the output end connection dual rate random access memory (RAM) 101 of number fixed-point number modular converter 102.
The output end of the input real-time simulator 10 of the connection based on FPGA of the first register 1030, the first register
1030 output end connects the input of the second register 1031.
The input of the second register 1031 connects the output end of the first register 1030, the output of the second register 1031
Hold the input of link address generation module 1032.
The input of address generation module 1032 connects the output end of the second register 1031, address generation module 1032
The input of output end connection dual rate random access memory (RAM) 101.
The output end of the input connection dual rate random access memory (RAM) 101 of digital-to-analogue conversion board 104, digital-to-analogue conversion plate
Analog machine outside the output end connection of card 104.
Wherein,
Real-time simulator 10 based on FPGA, driving clock clk-sim, number for generating real-time simulator in FPGA
Driving clock clk-da, the enable signal oe-da of digital-to-analogue conversion board 104 and emulation commencing signal of mould conversion board 1030
sta；And initialization is based on the simulation parameter of the real-time simulator of FPGA before emulation starts, according to the simulation parameter of initialization,
Generated in each simulation step length to should step-length 64 double-precision floating pointses forms simulation result out-ch.
Floating number fixed-point number modular converter 102, for 64 double precisions that the real-time simulator based on FPGA is exported to be floated
The simulation result out-ch of points form is converted to 64 simulation result da-input of fixed-point number form.
Dual rate random access memory (RAM) 101, for the writing address signal addr-w in driving clock clk-sim,
The simulation result da-input of 64 fixed-point number forms of the conversion of storage floating number fixed-point number modular converter 102.
First register 1030, for writing ground in the selected current driving clock clk-sim of emulation commencing signal sta
Location signal addr-w.
Second register 1031, for the selected write address driven in clock clk-sim of the first register 1030 to be believed
Number addr-w is converted into the ini_addr_r signals in the clock zone for driving clock clk-sim.
Address generation module 1032, drives in the clock zone of clock clk-sim for generate the second register 1031
Ini_addr_r signals be assigned to the reading address signal addr-r driven in clock clk-da of digital-to-analogue conversion board.
Dual rate random access memory (RAM) 101, for the reading address signal addr- generated according to address generation module 1032
R read 64 simulation result da-input of fixed-point number form, and will read 64 fixed-point number forms simulation result da-
N to N-M+1 in input is converted to the M simulation result da-out of offset binary code.
Digital-to-analogue conversion board 104, for being in continuous firing state according to enable signal oe-da, and exports M skew two
The corresponding analog signals of simulation result da-out of ary codes are to outside analog machine.
Specifically, simulation parameter is initialized before emulation starts, including：
The simulation type that real-time simulator 10 based on FPGA is exported, and taking according to the output data of simulation type are set
The digit of value scope and the digital signal end of digital-to-analogue conversion plate card 104 sets the digital analog interface of the real-time simulator 10 based on FPGA
Cut position parameter N and M.
Dual rate random access memory (RAM) 101 is write into clock setting for clk-sim, and by dual rate random access storage
The write address of device 101 is set to recurrent state.
Need to say, the write address of dual rate random access memory (RAM) is arranged to recurrent state here, can cause
The simulation result of the real-time simulator output based on FPGA is constantly written in dual rate random access memory (RAM).
Real-time simulator 10 based on FPGA is set and starts emulation, initialization simulation time t=0；And default emulation is set
Duration TN and simulation time step delta t；Wherein, when tested between t when being equal to default emulation duration TN, stop based on FPGA
The emulation of real-time simulator 10, TN is more than Δ t, and Δ t is more than 0.
The digital analog interface of the real-time simulator based on FPGA provided in an embodiment of the present invention, it is real-time by using FPGA generations
The enable letter for driving clock clk-sim, the driving clock clk-da of digital-to-analogue conversion board and digital-to-analogue conversion board of emulator
Number oe-da；And initialization is based on the simulation parameter of the real-time simulator of FPGA before emulation starts, the emulation ginseng according to initialization
Number, generated in each simulation step length to should step-length 64 double-precision floating pointses forms simulation result out-ch, it is ensured that
The versatility of output result；Enter that row clock is synchronous using the first register and the second register, by the driving of real-time simulator
Clock clk-sim is converted to the driving clock clk-da of digital-to-analogue conversion board, it is to avoid the problem of sequential occur, then by address
When ini_addr_r signals in the clock zone for driving clock clk-sim are assigned to the driving of digital-to-analogue conversion board by generation module
Reading address signal addr-r in clock clk-da, realizes the unification to real-time simulator and digital-to-analogue conversion board time domain, it is ensured that
The real-time of the simulation result of output；Dual rate random access memory (RAM) is according to the write address letter driven in clock clk-sim
Number addr-w, reads 64 simulation result da-input of fixed-point number form, and 64 emulation of fixed-point number form that will be read
As a result N to N-M+1 in da-input is converted to the M simulation result da-out of offset binary code, via number
Mould changes board and the M corresponding analog signal output of simulation result da-out of offset binary code is set to outside simulation
Standby, the interface resource that the digital analog interface of the real-time simulator based on FPGA provided in an embodiment of the present invention has given full play to FPGA is excellent
Gesture and the parallel technical advantage of hardware configuration, ensure real-time simulator digital analog interface communication speed and versatility it is same
When, realize real-time simulator simulation result and at a high speed, effectively export；So as to solve between real-time simulator in the prior art
And the problem that interface generality is relatively low, information exchange speed is relatively low between real-time simulator and external equipment.
The embodiment three, embodiment of the present invention provides a kind of driving side of the digital analog interface of the real-time simulator based on FPGA
Method, includes as shown in Figure 3：
S101, generation drive clock clk-sim, drive clock clk-da and enable signal oe-da.
S102, simulation parameter is initialized before emulation starts, and according to the simulation parameter of initialization, generate 64 double precisions
The simulation result out-ch of floating number form.
It should be noted that the simulation result that the emulator based on FPGA is exported as shown in Figure 2 is in actual application
Represented with out-ch.
S103, the simulation result out-ch of 64 double-precision floating pointses forms is converted into 64 emulation of fixed-point number form
As a result da-input.
S104, the writing address signal addr-w in driving clock clk-sim, store 64 emulation of fixed-point number form
As a result da-input.
S105, the writing address signal addr-w in clock clk-sim will be driven to be converted to the reading driven in clock clk-da
Address signal addr-r.
S106,64 simulation result da-input of fixed-point number form are read according to reading address signal addr-r, and will read
N to N-M+1 in the simulation result da-input of the 64 fixed-point number forms for taking is converted to M offset binary code
Simulation result da-out.
It should be noted that as shown in Figure 2 via digital-to-analogue conversion board by the M simulation result da- of offset binary code
Analog machine of the corresponding analog signal outputs of out to extremely outside.
S107, it is in continuous firing state and exports the M simulation result of offset binary code according to enabling signal oe-da
The corresponding analog signals of da-out.
It should be noted that the active power distribution network containing monopole photovoltaic generating system as shown in Figure 4, performs FPGA development boards
It is A Ertela (English full name：Altera) companyThe official's development boards of IV GX FPGA 530；Development board is furnished with
Stratix IV Series FPGA EP4SGX530KH40C2N, the chip includes 744 I/O；Test digital-to-analogue conversion plate card model
DAC900, resolution ratio is 10, and highest supports the switching rate of 165MHz；The model Tyke MDO3104 of test scope, most
Height supports the signal sampling rate of 2GS/s.
Test example is the active power distribution network containing photovoltaic generating system, and simulation step length is set to 3 μ s, as shown in Figure 4.In photovoltaic
In generator unit, inverter is given using Vdc controls, photovoltaic voltage reference value Vref in constant form.Temperature setting in example
It is 298K, Vref is set to 350V, and Qref is set to 0Var.Power supply and transformer are using the source-series constant impedance simulation of voltage.
Fpga chip is driven by the global clock of 100MHz, and simulation and calculation is input into by phase-locked loop pll frequency multiplication to 135MHz
Part, and logarithmic mode change-over panel card is driven；The simulation result of real-time simulator via development board high speed intermediary interface B ends
Mouth is input in the digital-to-analogue conversion board of 10 bit resolutions, and board switching rate is set to 135MHz, straight eventually through oscillograph
Display simulation result is connect, the sample rate of oscillograph is set to 25kS/s.Identical example is built and is imitated in PSCAD/EMTDC
Very, wherein, the simulation step length of real-time simulator and PSCAD/EMTDC is set as 3 μ s, and simulation time is 4s.
In order to verify the accuracy and validity of the digital analog interface of real-time simulator, simulating scenes consider photovoltaic generation system
System output pulsation and the situation of singlephase earth fault.Wherein, under output pulsation scene, photovoltaic hair when emulation proceeds to 1.5s
The intensity of illumination of electric system input increases suddenly；Under fault scenes, there is C when emulation proceeds to 1.5s at photovoltaic system outlet
Phase ground short circuit failure, failure removal after 0.2s, failure is simulated by breaker.Simulation result is imitated with PSCAD/EMTDC
Really compare, and synchronism output has carried out real-time display and analysis to oscillograph.
Fig. 5 is given under output pulsation scene, the real-time simulator based on FPGA and business electromagnetic transient simulation software (English
Literary full name：Power Systems Computer Aided Design, referred to as：PSCAD)/(English full name：Electro-
Magnetic Transient in DC System, abbreviation EMTDC) in photovoltaic generating system output current simulations result, figure
The 6 current simulations results for giving the real-time simulator output shown in correspondence oscillograph；Fig. 7 is given under fault scenes,
The voltage simulation result that real-time simulator based on FPGA is exported with photovoltaic generating system in business software PSCAD/EMTDC, Fig. 8
Give the faulted phase voltage waveform of the real-time simulator output shown in correspondence oscillograph.From Fig. 5 and Fig. 6 and Fig. 7 and Fig. 8
Contrast as can be seen that voltages and current signal different for excursion, real-time simulator is realized and connect by digital-to-analogue
Mouthful by simulation result effectively, in the output of high speed to outside physical equipment, so as to demonstrate the active power distribution network based on FPGA
The correctness and validity of the digital analog interface of real-time simulator.
Specifically,
Simulation parameter is initialized before emulation starts, including：
Simulation type, and the span of output data according to simulation type and cutting for digit setting digital analog interface are set
Position parameter N and M.
Digital analog interface is write into clock setting for clk-sim, and the write address of digital analog interface is set to recurrent state.
Start emulation, initialization simulation time t=0；And default emulation duration TN and simulation time step delta t is set；
Wherein, when tested between t when being equal to default emulation duration TN, stop emulation, TN is more than Δ t, and Δ t is more than 0.
Specifically,
Simulation parameter is initialized before emulation starts, including：Generation emulation commencing signal sta.
The writing address signal addr-w in clock clk-sim will be driven to be converted to the reading address letter driven in clock clk-da
Number addr-r, including：
According to the selected current writing address signal addr-w driven in clock clk-sim of emulation commencing signal sta.
The writing address signal addr-w in clock clk-sim will be driven to be converted into the clock zone for driving clock clk-sim
Ini_addr_r signals.
Ini_addr_r signals in the clock zone for driving clock clk-sim are assigned to drive the reading in clock clk-da
Address signal addr-r.
The driving method of the digital analog interface of the real-time simulator based on FPGA provided in an embodiment of the present invention, is driven by generating
Dynamic clock clk-sim, driving clock clk-da and enable signal oe-da；And simulation parameter, root are initialized before emulation starts
According to initialization simulation parameter, generated in each simulation step length to should step-length 64 emulation of double-precision floating pointses form
As a result out-ch, it is ensured that the versatility of output result；Clock clk-sim will be driven to be converted to driving clock clk-da, realized
Unification to real-time simulator and digital-to-analogue conversion board time domain, it is ensured that the real-time of the simulation result of output；According to driving
Writing address signal addr-w in clock clk-sim, reads 64 simulation result da-input of fixed-point number form, and will read
64 fixed-point number forms simulation result da-input in N to N-M+1 be converted to M offset binary code
Da-out, arrives the corresponding analog signal outputs of simulation result da-out of M offset binary code via digital-to-analogue conversion board
Extremely outside analog machine, the driving method of the digital analog interface of the real-time simulator based on FPGA provided in an embodiment of the present invention,
The digital analog interface of the real-time simulator based on FPGA can be effectively driven, the interface resource advantage of FPGA and hard has been given full play to
The parallel technical advantage of part structure, while the communication speed and versatility of digital analog interface of real-time simulator is ensured, realizes
Real-time simulator simulation result at a high speed, effective output；It is between real-time simulator in the prior art and real so as to solve
When the problem that interface generality is relatively low, information exchange speed is relatively low between emulator and external equipment.
The above, specific embodiment only of the invention, but protection scope of the present invention is not limited thereto, and it is any
Those familiar with the art the invention discloses technical scope in, change or replacement can be readily occurred in, should all contain
Cover within protection scope of the present invention.Therefore, protection scope of the present invention should be based on the protection scope of the described claims.
Claims (6)
1. a kind of digital analog interface of the real-time simulator based on FPGA, it is characterised in that including：Dual rate random access storage
Device, floating number fixed-point number modular converter, digital-to-analogue conversion board and address conversion module；
The output end of the input connection real-time simulator based on FPGA of the floating number fixed-point number modular converter, it is described
The output end of floating number fixed-point number modular converter connects the input of the dual rate random access memory (RAM)；
Input connection the floating number fixed-point number modular converter and the address of the dual rate random access memory (RAM)
Modular converter, the output end of the dual rate random access memory (RAM) connects the digital-to-analogue conversion board；
The output end of the input connection real-time simulator based on FPGA of the address conversion module, the address conversion
The output end of module connects the input of the dual rate random access memory (RAM)；
The input of the digital-to-analogue conversion board connects the output end of the dual rate random access memory (RAM), the digital-to-analogue conversion
Analog machine outside the output end connection of board；
Wherein,
The real-time simulator based on FPGA, the driving clock clk- for generating the real-time simulator in the FPGA
The driving clock clk-da and the enable signal oe-da of the digital-to-analogue conversion board of sim, the digital-to-analogue conversion board；And
Emulation initializes the simulation parameter of the real-time simulator based on FPGA before starting, according to the simulation parameter of the initialization,
Generated in each simulation step length to should step-length 64 double-precision floating pointses forms simulation result out-ch；
The floating number fixed-point number modular converter, for double smart by described 64 of the real-time simulator output based on FPGA
The simulation result out-ch for spending floating number form is converted to 64 simulation result da-input of fixed-point number form；
The dual rate random access memory (RAM), for the writing address signal addr-w in the driving clock clk-sim,
Store the simulation result da-input of 64 fixed-point number forms of the floating number fixed-point number modular converter conversion；
The address conversion module, it is described for the writing address signal addr-w in the driving clock clk-sim to be converted to
Drive the reading address signal addr-r in clock clk-da；
The dual rate random access memory (RAM), for the reading address signal generated according to the address conversion module
The simulation result da-input of addr-r readings 64 fixed-point number forms, and the 64 fixed-point number forms that will be read
N to N-M+1 in simulation result da-input is converted to the M simulation result da-out of offset binary code, defeated
Go out in described digital-to-analogue conversion board；
The digital-to-analogue conversion board, for being in continuous firing state according to the enable signal oe-da, and exports described M
The corresponding analog signals of simulation result da-out of offset binary code to the outside analog machine.
2. the digital analog interface of the real-time simulator in FPGA according to claim 1, it is characterised in that
It is described to initialize simulation parameter before emulation starts, including：
The simulation type that the real-time simulator based on FPGA is exported is set, and according to the output data of the simulation type
The digit of span and the digital-to-analogue conversion board digital signal end sets the digital-to-analogue of the real-time simulator based on FPGA
Cut position the parameter N and M of interface；
The dual rate random access memory (RAM) is write into clock setting for clk-sim, and the dual rate arbitrary access is deposited
The write address of storage is set to recurrent state；
The real-time simulator based on FPGA is set and starts emulation, initialization simulation time t=0；And when default emulation is set
T longNAnd simulation time step delta t；Wherein, when the testing time t is equal to the default emulation duration TNWhen, stop described
The emulation of the real-time simulator based on FPGA, TNMore than Δ t, Δ t is more than 0.
3. the digital analog interface of the real-time simulator in FPGA according to claim 1, it is characterised in that
It is described to initialize simulation parameter before emulation starts, including：The emulation of the real-time simulator is generated in the FPGA
Commencing signal sta；
The address conversion module includes：First register, the second register and address generation module；
The output end of the input connection real-time simulator based on FPGA of first register, first register
Output end connect the input of second register；
The input of second register connects the output end of first register, and the output end of second register connects
Connect the input of the address generation module；
The input of the address generation module connects the output end of second register, the output of the address generation module
The input of the end connection dual rate random access memory (RAM)；
Wherein,
First register, in selecting presently described driving clock clk-sim according to the emulation commencing signal sta
Writing address signal addr-w；
Second register, for the write address in the selected driving clock clk-sim of first register to be believed
Number addr-w is converted into the ini_addr_r signals in the clock zone of the driving clock clk-sim；
The address generation module, in the clock zone of the driving clock clk-sim for generating second register
Ini_addr_r signals be assigned to the reading address signal addr-r driven in clock clk-da of the digital-to-analogue conversion board.
4. the driving method of the digital analog interface of a kind of real-time simulator based on FPGA as described in claim any one of 1-3,
It is characterised in that it includes：
Generation drives clock clk-sim, drives clock clk-da and enables signal oe-da；
Simulation parameter is initialized before emulation starts, and according to the simulation parameter of the initialization, it is raw in each simulation step length
In pairs should step-length 64 double-precision floating pointses forms simulation result out-ch；
The simulation result out-ch of 64 double-precision floating pointses forms is converted into 64 simulation results of fixed-point number form
da-input；
According to the writing address signal addr-w driven in clock clk-sim, the simulation result of 64 fixed-point number forms is stored
da-input；
Writing address signal addr-w in the driving clock clk-sim is converted into the reading ground in the driving clock clk-da
Location signal addr-r；
The simulation result da-input of 64 fixed-point number forms is read according to the reading address signal addr-r, and will be read
64 fixed-point number forms simulation result da-input in N to N-M+1 be converted to M offset binary
The simulation result da-out of code；
Continuous firing state is according to the enable signal oe-da and the simulation result of the M offset binary code is exported
The corresponding analog signals of da-out.
5. the driving method of the digital analog interface of the real-time simulator based on FPGA according to claim 4, it is characterised in that
It is described to initialize simulation parameter before emulation starts, including：
Simulation type is set, and the digital analog interface is set according to the span and digit of the output data of the simulation type
Cut position parameter N and M；
The digital analog interface is write into clock setting for clk-sim, and the write address of the digital analog interface is set to circulate shape
State；
Start emulation, initialization simulation time t=0；And default emulation duration T is setNAnd simulation time step delta t；Wherein,
When the testing time t is equal to the default emulation duration TNWhen, stop emulation, TNMore than Δ t, Δ t is more than 0.
6. the driving method of the digital analog interface of the real-time simulator based on FPGA according to claim 4, it is characterised in that
It is described to initialize simulation parameter before emulation starts, including：Generation emulation commencing signal sta；
The writing address signal addr-w by the driving clock clk-sim is converted in the driving clock clk-da
Read address signal addr-r, including：
Writing address signal addr-w in presently described driving clock clk-sim is selected according to the emulation commencing signal sta；
Writing address signal addr-w in the driving clock clk-sim is converted into the clock zone for driving clock clk-sim
Ini_addr_r signals；
Ini_addr_r signals in the clock zone of the driving clock clk-sim are assigned in the driving clock clk-da
Reading address signal addr-r.
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