CN209198615U - A kind of timing and waveform generating - Google Patents
A kind of timing and waveform generating Download PDFInfo
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- CN209198615U CN209198615U CN201821733157.5U CN201821733157U CN209198615U CN 209198615 U CN209198615 U CN 209198615U CN 201821733157 U CN201821733157 U CN 201821733157U CN 209198615 U CN209198615 U CN 209198615U
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Abstract
The utility model proposes a kind of timing and waveform generatings.Utility model device includes a vector generator, multiple groups timing and waveform processing unit；Wherein, every group of timing and waveform processing unit are made of a clock generator and a waveshape monitor；Vector generator is connect with multiple groups timing sequencer respectively；The clock generator is connect with the waveshape monitor；The vector generator is for providing test vector and timing information；The clock generator is used to generate timing edge according to timing information；The waveshape monitor is used to that the test vector to be converted into waveform signal according to timing edge.The utility model solves the problems, such as that automatic test equipment output timing precision is low.
Description
Technical field
The utility model belongs to digital integrated electronic circuit testing field, more particularly, to a kind of timing and waveform generating.
Background technique
It is integrated can be divided into simulation by its function, the difference of structure for integrated circuit (Integrated Circuits, IC)
Circuit, digital integrated electronic circuit and hydrid integrated circuit three classes.Digital integrated electronic circuit have small in size, low in energy consumption, high reliablity, at
The advantages that this is low and easy to use.It has obtained widely answering in fields such as automatic control, measuring instrument, communication and electronic computers
With.
IC test is an important component of IC industry, is to guarantee performance of integrated circuits, the key of quality
One of link.Digital IC functional test is for guaranteeing that test device can be correctly completed its expected function.In order to reach test
Purpose can generally utilize test vector (Test Pattern, TP), to detect the internal fault of measured device.Test vector is
The Serial No. of a string continuous " 0 " and " 1 " composition.It, will be required by chip under test functional analysis before functional test
The vector that test vector and timing requirements download to automatic test equipment (Automatic Test Equipment, ATE) occurs
In device (Pattern Generator, PG), after test macro starting, vector generator send test vector according to certain sequence
To timing waveform generator, most it is sent on the correspondence pin of chip through driving circuit afterwards.
ATE is the important tool of IC test.With the development of very large scale integration technology, IC integrated level is increasingly
Height, function become increasingly complex, high density, and high-speed chip continuously emerges.And the performance requirement of test equipment is much higher than chip under test,
Therefore to test equipment, higher requirements are also raised, it is desirable that more independent test channels (several hundred or even thousands of roads) is provided,
High-precision timing sequence generating circuit (picosecond), biggish test vector memory space etc..
A kind of digital IC testing system is disclosed in the Chinese patent application that application publication number is CN202014257U
Timing sequence generating circuit, the timing sequence generating circuit in the patent are fairly simple mainly by one 32 programmable counters and 2
32 bit comparators composition generates waveform timing accuracy and is determined completely by clock signal frequency.The patent only has 2 comparators, institute
2 variations can only at most occur in signal period with the signal of generation, more complicated waveform can not be generated.The patent can only mention
It is arranged for 8 groups of independent clocks, it can be not enough in the more complex chip of test sequence.
A kind of number of automatic test equipment is disclosed in the Chinese patent application that application publication number is CN101512362A
Character waveform generates and measurement method, and the digital waveform generator in the patent is mainly made of storage device and high speed SERDES,
It will wish that the waveform exported presses the Periodic decomposition of SERDES, is then store in memory before test.Parallel from storage when test
Device takes out data, is sent into high speed SERDES and carries out parallel-serial conversion, generates digital waveform.But when test period very little and test
Between it is longer when, the scheme which provides needs biggish storage space, as the reading speed that becomes larger of memory space can become
Slowly, the speed for reading memory access can be unable to catch up with the conversion speed of SERDES, become the bottleneck of output waveform speed.In addition picosecond
Timing need the professional high speed SERDES (speed be greater than 1G) using FPGA, generally only high-end FPGA just has, and not only counts
Electrical limitation that is limited, and having special is measured, before input equipment under test (Device Under Test, DUT) needs that complexity is added
Peripheral circuit carry out signal condition.In addition SERDES power consumption is higher, and the complexity for also resulting in design improves.
It is disclosed in the Chinese patent application that application publication number is CN108471303A a kind of programmable based on FPGA
Nanosecond timing accuracy impulse generator, using the OSERDES control module of xilinx spartan6 FPGA, timing accuracy is only
It can accomplish nanosecond rank.
A kind of high-speed, high precision number arteries and veins is disclosed in the Chinese patent application of authorization Publication No. CN105656456B
Circuit and pulse generating method occur for punching, which first passes through register control circuit, configure pulse parameter (period, arteries and veins
It is wide), enabling signal is then issued, pulse generating circuit generates the pulse in period according to configuration later.Although the patent can produce
Raw high-precision digit pulse, but only store a kind of timing setting (register configuration).It is general in digital IC functional test
It needs a variety of timing to be arranged, and is required to change timing (Time On Fly, TOF) in real time, which can not adapt to.
Programmable digital pulse is disclosed in the Chinese patent application that application publication number is CN101907881A
Device, the patent at most exportable 16 road pulse signal, and modern semiconductor testing apparatus generally requires output road arteries and veins up to a hundred
Punching output.In addition the chip that the patent uses compares low side, and timing accuracy can not be made too high.
Digital IC functional test timing and the core of Waveform generating method are the generations of high-precision programmable pulse signal.State
The patent of the interior production method about high-precision programmable pulse signal is relatively more, but for digital IC functional test applied field
Scape is all unsuitable.And the patent about digital IC functional test timing and Waveform generating method does not have substantially.
Utility model content
In order to solve the above-mentioned technical problem, the utility model proposes a kind of timing and waveform generatings.
The technical solution of the utility model is a kind of timing and waveform generating, comprising: vector generator, a multiple groups
Timing and waveform processing unit；Wherein, every group of timing and waveform processing unit are controlled by a clock generator and a waveform
Device is constituted；Vector generator is connect with multiple groups timing sequencer respectively；The clock generator is connect with the waveshape monitor；
The vector generator is used to provide test vector and timing information for the multiple groups timing and waveform processing unit；The timing
Generator is used to generate timing edge according to timing information；The waveshape monitor is used to be converted the test vector according to timing edge
At waveform signal.
Preferably, the vector generator is stored by a vector memory, a sequence controller and a timing
Device is constituted；Vector memory, sequence controller and the sequential memory is sequentially connected.
Further, the vector memory is for storing test needed for the multiple groups timing and waveform processing unit testing
Vector；Time sequence configuration information needed for the timing reservoir is used to store multiple groups timing and the test of waveform processing Elementary Function；
Sequence controller is read from the vector memory and the sequential memory with the beat of test period according to testing process and is surveyed
Examination vector sum corresponds to timing.
Further, the timing reservoir provides 32 groups of independent timing and matches for every group of timing and waveform processing unit
It sets.
Preferably, the vector generator supports timing and the quantity of waveform processing unit testing is N, N >=256, and N
For positive integer.
Preferably, the clock generator is by 8 groups of identical structures and independent timing is constituted along generation circuit, it is described fixed
When along generation circuit be 3 grades of timing circuits, it is programmable by a programmable counter, a high speed parallel-to-serial converter and one
Time delay chain is constituted；Programmable counter, high speed parallel-to-serial converter and the programmable delay chain is sequentially connected.
Further, for the programmable counter for realizing thick timing, thick timing accuracy is а and а > 5ns；The height
For fast parallel-to-serial converter for realizing thin timing, thin timing accuracy is а/4；Programmable delay chain for realizing smart timing, it is described can
Programming time delay chain includes 32 grades of delay units, and smart timing accuracy is а/128.
Further, the programmable counter, the high speed parallel-to-serial converter and the programmable delay chain have
Period control interface timeset and compensation control interface offset, timeset are used to be arranged the timing of current period along the moment,
Offset be used for be arranged this periodically edge delay deviation compensation.
Preferably, the waveshape monitor is made of a signal distributor and a pattern formatter；The signal
Distributor is connected with pattern formatter.
Further, each timing is assigned to the corresponding sub- place of the pattern formatter along signal by the signal distributor
Manage unit；The pattern formatter has multiple independent subprocessing units, and the pattern formatter binding test vector sum is fixed
When along output timing waveform.
Preferably, every group of timing and waveform processing unit further include a driver, the driver and the wave
The connection of shape controller；The driver is used to carry out level modulation to output waveform.
The purpose of this utility model is that proposing a kind of timing and waveform generating.Using clock generator and waveform control
The scheme of device processed.Clock generator includes 3 grades of time delay adjustment circuits, is responsible for generating high precision timing edge.Waveshape monitor according to
The corresponding timing of code selection is exported along generation waveform.And each channel configures independent clock generator and waveform control
Device facilitates extension.By the way that this method solve automatic test equipment (Automatic Test Equipment, ATE) test machines
Output timing precision is not high enough, generates waveform and does not enrich, and output channel number is few and is not easy the difficult points such as extension.
Utility model has the advantages that providing a picosecond rank timing accuracy using 3 grades of time delay adjustment circuits；Every channel
Independent 32 groups of timing setting is provided, and supports change timing (Time On Fly, TOF) function in real time；Every channel provides many
In 8 timing edges, timing control is more flexible；Each channel is furnished with independent waveform generator, supports the common output pattern of ATE；
Delay compensation function is provided, measuring accuracy is further increased, reduces test error.
Detailed description of the invention
Fig. 1: the system block diagram of the utility model；
Fig. 2: the vector generator functional block diagram of the utility model；
Fig. 3: the clock generator functional block diagram of the utility model；
Fig. 4: the clock generator timing diagram of the utility model；
Fig. 5: the waveshape monitor functional block diagram of the utility model；
Fig. 6: the waveshape monitor timing diagram of the utility model.
Specific embodiment
The utility model is understood and implemented for the ease of those of ordinary skill in the art, it is right with reference to the accompanying drawings and embodiments
The utility model is described in further detail, it should be understood that implementation example described herein is only used for describing and explaining this
Utility model is not used to limit the utility model.
The system block diagram of timing and Waveform generating apparatus in the functional test of the utility model is as shown in Figure 1, a vector
Generator, multiple groups timing and waveform processing unit；Wherein, every group of timing and waveform processing unit are by a clock generator and one
A waveshape monitor is constituted；Vector generator is connect with multiple groups timing sequencer respectively；The clock generator and the waveform
Controller connection；The vector generator is used to provide test vector and timing letter for the multiple groups timing and waveform processing unit
Breath；The clock generator is used to generate timing edge according to timing information；The waveshape monitor is used for should according to timing edge
Test vector is converted into waveform signal.
The vector generator is made of a vector memory, a sequence controller and a sequential memory；Institute
Vector memory, sequence controller and the sequential memory stated are sequentially connected.
The vector memory is for test vector needed for storing the multiple groups timing and waveform processing unit testing；It is described
Time sequence configuration information needed for timing reservoir is used to store multiple groups timing and the test of waveform processing Elementary Function；Sequence controller
According to testing process with the beat of test period from the vector memory and the sequential memory read test vector sum pair
Answer timing.
The timing reservoir provides 32 groups of independent timing configurations for every group of timing and waveform processing unit.
It is positive integer that the vector generator support timing and the quantity of waveform processing unit testing, which are N, N >=256, and N,.
The clock generator is by 8 groups of identical structures and independent timing is constituted along generation circuit, and the timing is along generation
Circuit is 3 grades of timing circuits, by a programmable counter, a high speed parallel-to-serial converter and a programmable delay chain structure
At；Programmable counter, high speed parallel-to-serial converter and the programmable delay chain is sequentially connected.
For the programmable counter for realizing thick timing, thick timing accuracy is а and а > 5ns；The high speed parallel-serial conversion
For device for realizing thin timing, thin timing accuracy is а/4；Programmable delay chain is for realizing smart timing, the programmable delay chain
Including 32 grades of delay units, smart timing accuracy is а/128.
The programmable counter, the high speed parallel-to-serial converter and the programmable delay chain have period control to connect
Mouth timeset and compensation control interface offset, timeset are used to be arranged the timing of current period along the moment, and offset is used for
Be arranged this periodically edge delay deviation compensation.
The waveshape monitor is made of a signal distributor and a pattern formatter；The signal distributor and code
The connection of type formatter.
Each timing is assigned to the corresponding subprocessing unit of the pattern formatter along signal by the signal distributor；Institute
Pattern formatter is stated with multiple independent subprocessing units, when the pattern formatter binding test vector sum timing is along output
Sequence waveform.
Every group of timing and waveform processing unit further include a driver, and the driver and the waveshape monitor connect
It connects；The driver is used to carry out level modulation to output waveform.
In a kind of specific embodiment, 1 vector generator, N group timing and the waveform processing unit are being less than
Fpga chip equal to 28nm technique is realized.N=256 indicates that the vector generator supports the number of timing and waveform processing unit
Amount, a=8ns indicate thick timing adjustment precision.The MAX9972 four-way 300Mbps Pin of driver selection Maxim
Electronics chip.
The embodiments of the present invention is introduced below with reference to Fig. 1 to Fig. 6.
Fig. 2 is the vector generator functional block diagram of the utility model, and the vector generator is by vector memory, sequence control
Device and sequential memory processed are constituted, vector memory, sequence controller and the sequential memory in the vector generator according to
Secondary connection；The vector memory is for storing test vector needed for each channel function is tested；The timing reservoir is used to deposit
Time sequence configuration information needed for storing up each channel function test, each channel have 32 groups of independent timing configurations；Sequence control
Device corresponds to timing from vector memory and sequential memory read test vector sum with the beat of test period according to testing process；
Vector generator supports the quantity N=256 of timing and waveform processing unit.
Fig. 3 is the clock generator functional block diagram of the utility model, and the clock generator is by 8 groups of identical structures and independence
Timing along generation circuit constitute, the timing along generation circuit be 3 grades of timing circuits, by programmable counter, high speed and go here and there
Converter and programmable delay chain are constituted；Programmable counter, high speed parallel-to-serial converter and the programmable delay chain
It is sequentially connected；For the programmable counter for realizing thick timing, thick timing accuracy is а and а > 5ns；The high speed and string turn
For parallel operation for realizing thin timing, thin timing accuracy is а/4；Programmable delay chain is for realizing smart timing, the programmable delay
Chain includes 32 grades of delay units, and smart timing accuracy is а/128.When a=8ns, then final timing is along degree of regulation up to 8ns ÷ 4
÷ 32=62.5ps.
Programmable counter, high speed parallel-to-serial converter and the programmable delay chain has period control interface
Timeset and compensation control interface offset, timeset are used to be arranged the timing of current period along the moment, and offset is for setting
Set this periodically edge delay deviation compensation；
For further illustrate the utility model clock generator working principle, timing shown in Figure 4 generates
Device timing diagram.Here by taking the generation on 1 timing edge as an example, it is assumed that counter cycle 8ns, current period are set by timeset
It is set to 8ns*10+2ns+3*62.5ps, deviation channel compensation control interface is set as 2*62.5ps, therefore final timing is along position
For 8ns*10+2ns+ (3+2) * 62.5ps.
Fig. 5 is the waveshape monitor functional block diagram of the utility model, and i-th waveshape monitor is by signal distributor and code
Type formatter is constituted, and the vector generator supports that the quantity of TCH test channel is N=256；The signal distributor and the code
The connection of type formatter；Each timing is assigned to the corresponding subprocessing list of the pattern formatter along signal by the signal distributor
Member；The pattern formatter has multiple independent subprocessing units, and the vector sum timing of pattern formatter binding test is along output
Timing waveform.Such as NRZ pattern processing unit only needs timing_edge_1 timing edge, and RZ pattern processing unit needs
Timing_edge_2 and timing_edge_3 timing edge.Pattern formatter has multiple independent subprocessing units, pattern lattice
The vector sum timing of formula device binding test is along output timing waveform.
For further illustrate the utility model waveshape monitor working principle, waveform control shown in Figure 6
Device timing diagram.In the 1st test period, test vector is " 1 " pattern for using for NRZ, therefore in the upper of timing_edge_1
Edge is risen, WAVE output becomes 1 from 0.In the 2nd test period, test vector is " 2 " pattern for using for NRZ, therefore
The rising edge of timing_edge_1, WAVE output become 0 from 1.In the 3rd test period, test vector is the code that " 1 " uses
Type is RZ, therefore in the rising edge of timing_edge_2, and WAVE output becomes 1 from 0, in the rising edge of timing_edge_3,
WAVE output becomes 0 from 1.
Although this specification has more used vector generator, timing and waveform processing unit, clock generator, waveform
Controller, driver, vector memory, sequence controller, sequential memory, periodically along generation circuit, programmable counter, height
The terms such as fast parallel-to-serial converter, programmable delay chain, signal distributor, pattern formatter, but be not precluded and use other terms
A possibility that.The use of these items is only for more easily describing the essence of the utility model, it is construed as any
The additional limitation of one kind is all contrary to the spirit of the present invention.
It should be understood that the part that this specification does not elaborate belongs to the prior art.
It should be understood that the above-mentioned description for preferred embodiment is more detailed, can not therefore be considered to this
The limitation of utility model patent protection scope, those skilled in the art are not departing under the enlightenment of the utility model
Under ambit protected by the claims of this utility model, replacement or deformation can also be made, the utility model is each fallen within
Within protection scope, the utility model is claimed range and should be determined by the appended claims.
Claims (11)
1. a kind of timing and waveform generating characterized by comprising a vector generator, respectively with the vector occur
The multiple groups timing and waveform processing unit of device connection；Every group of timing and waveform processing unit are by a clock generator and a wave
Shape controller is constituted, and clock generator is connect with waveshape monitor；
The vector generator is used to provide test vector and timing information for the multiple groups timing and waveform processing unit；
The clock generator is used to generate timing edge according to timing information；
The waveshape monitor is used to that the test vector to be converted into waveform signal according to timing edge.
2. timing according to claim 1 and waveform generating, which is characterized in that the vector generator from one to
Memory, a sequence controller and a sequential memory is measured to constitute；Vector memory, sequence controller and the timing
Memory is sequentially connected.
3. timing according to claim 2 and waveform generating, which is characterized in that the vector memory is for storing
Test vector needed for the multiple groups timing and waveform processing unit testing；The sequential memory is used to store multiple groups timing and wave
Time sequence configuration information needed for shape processing unit functional test；Sequence controller according to testing process with the beat of test period from
The vector memory and the sequential memory read test vector sum correspond to timing.
4. timing according to claim 3 and waveform generating, which is characterized in that when the sequential memory is every group
Sequence and waveform processing unit provide 32 groups of independent timing configurations.
5. timing according to claim 1 and waveform generating, which is characterized in that the vector generator supports timing
And it is positive integer that the quantity of waveform processing unit testing, which is N, N >=256, and N,.
6. timing according to claim 1 and waveform generating, which is characterized in that the clock generator is by 8 groups of phases
With structure and independent timing is constituted along generation circuit, and the timing is 3 grades of timing circuits along generation circuit, programmable by one
Counter, a high speed parallel-to-serial converter and a programmable delay chain are constituted；The programmable counter, high speed are simultaneously gone here and there
Converter and programmable delay chain are sequentially connected.
7. timing according to claim 6 and waveform generating, which is characterized in that the programmable counter is for real
Now thick timing, thick timing accuracy are а and а > 5ns；The high speed parallel-to-serial converter is for realizing thin timing, thin timing accuracy
а/4；Programmable delay chain includes 32 grades of delay units for realizing smart timing, the programmable delay chain, and smart timing accuracy is
а/128。
8. timing according to claim 7 and waveform generating, it is characterised in that: the programmable counter, described
High speed parallel-to-serial converter and the programmable delay chain have period control interface timeset and compensation control interface
Offset, timeset are used to be arranged the timing of current period along the moment, and the delay deviation that offset is used to be arranged the periodically edge is mended
It repays.
9. timing according to claim 1 and waveform generating, it is characterised in that: the waveshape monitor is believed by one
Number distributor and a pattern formatter are constituted；The signal distributor is connected with pattern formatter.
10. timing according to claim 9 and waveform generating, it is characterised in that: the signal distributor will be each
Timing is assigned to the corresponding subprocessing unit of the pattern formatter along signal；The pattern formatter has multiple independent sons
Processing unit, the pattern formatter binding test vector sum timing is along output timing waveform.
11. timing according to claim 1 and waveform generating, it is characterised in that: at every group of timing and waveform
Managing unit further includes a driver, and the driver is connect with the waveshape monitor；The driver is used for output waveform
Carry out level modulation.
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| CN201821733157.5U CN209198615U (en) | 2018-10-24 | 2018-10-24 | A kind of timing and waveform generating |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109143045A (en) * | 2018-10-24 | 2019-01-04 | 武汉精鸿电子技术有限公司 | A kind of timing and waveform generating and method |
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2018
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109143045A (en) * | 2018-10-24 | 2019-01-04 | 武汉精鸿电子技术有限公司 | A kind of timing and waveform generating and method |
| CN109143045B (en) * | 2018-10-24 | 2024-02-13 | 武汉精鸿电子技术有限公司 | Time sequence and waveform generation device and method |
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