CN109143045B - Time sequence and waveform generation device and method - Google Patents
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Abstract
The invention provides a time sequence and waveform generation device and method. The device comprises a vector generator, a plurality of groups of time sequences and waveform processing units; each group of time sequence and waveform processing units consists of a time sequence generator and a waveform controller; the vector generators are respectively connected with the plurality of groups of time sequence generators; the time sequence generator is connected with the waveform controller; the vector generator is used for providing test vectors and time sequence information; the time sequence generator is used for generating a timing edge according to the time sequence information; the waveform controller is configured to convert the test vector into a waveform signal according to a timing edge. The method of the invention distributes the timing edge signal to the code pattern of the sub-processing unit through the distributor in the waveform controller; the test vector received by the code pattern formatter in the waveform controller selects a corresponding timing edge signal according to the code pattern of the test vector in each test period to generate a waveform. The invention solves the problem of low output time sequence precision of automatic test equipment.
Description
Technical Field
The present invention relates to the field of digital integrated circuit testing, and more particularly, to a timing and waveform generation apparatus and method.
Background
Integrated circuits (Integrated Circuits, ICs) can be classified into analog integrated circuits, digital integrated circuits, and hybrid integrated circuits, depending on their functions and structures. The digital integrated circuit has the advantages of small volume, low power consumption, high reliability, low cost, convenient use and the like. The method is widely applied to the fields of automatic control, measuring instruments, communication, electronic computers and the like.
IC testing is an important component of the integrated circuit industry, and is one of the key links in ensuring the performance and quality of integrated circuits. Digital IC functional testing is used to ensure that the test device is able to properly perform its intended function. To achieve the purpose of testing, test Pattern (TP) is generally used to detect internal faults of the device under Test. The test vector is a series of consecutive numbers consisting of "0" and "1". Before functional test, the required test vectors and time sequence requirements are downloaded into a vector generator (Pattern Generator, PG) of automatic test equipment (Automatic Test Equipment, ATE) through functional analysis of the tested chip, after a test system is started, the vector generator sends the test vectors to a time sequence waveform generator according to a certain sequence, and finally the test vectors are sent to corresponding pins of the chip through a driving circuit.
ATE is an important tool for IC testing. With the development of ultra-large scale integrated circuit technology, the Integrated Circuit (IC) has higher and higher integration level, more and more complex functions, high density and high speed chips are continuously appeared. The performance requirements of the test equipment are far higher than those of the tested chip, so that higher requirements are also put on the test equipment, more independent test channels (hundreds or even thousands of paths) are required to be provided, a high-precision time sequence generating circuit (picosecond level) and a larger test vector storage space are required to be provided.
In chinese patent application CN202014257U, a timing generation circuit of a digital IC test system is disclosed, and the timing generation circuit in the patent is relatively simple and mainly comprises a 32-bit programmable counter and 2 32-bit comparators, and the timing precision of the generated waveform is completely determined by the frequency of the clock signal. This patent has only 2 comparators, so the signal generated can only change 2 times at most in a single period, and cannot generate more complex waveforms. This patent can only provide 8 sets of independent clock settings and may not be sufficient for testing chips with more complex timing.
In chinese patent application CN101512362a, a method for generating and measuring digital waveforms of automatic test equipment is disclosed, in which the digital waveform generator is mainly composed of a storage device and a high-speed SERDES, and the waveforms desired to be output are decomposed according to the period of the SERDES before the test, and then stored in the storage device. And during testing, data are taken out of the memory in parallel, and are sent into the high-speed SERDES for parallel-serial conversion, so that digital waveforms are generated. However, when the test period is very short and the test time is long, the scheme provided by the patent needs a relatively large memory space, the reading speed is reduced along with the increase of the memory space, and the speed of the reading accessor can not catch up with the conversion speed of the SERDES, so that the bottleneck of the output waveform speed is formed. In addition, the timing of picosecond level requires special high-speed SERDES (speed is greater than 1G) using FPGA, and generally only high-end FPGA has limited quantity and special electrical limitation, and complex peripheral circuits are required to be added for signal conditioning before input into the tested equipment (Device Under Test, DUT). In addition, higher SERDES power consumption also results in increased design complexity.
An FPGA-based programmable nanosecond timing precision pulse generator is disclosed in Chinese patent application with the application publication number of CN108471303A, and an OSERDES control module of a xilinx spartan6 FPGA is adopted, so that the timing precision can only achieve the nanosecond level.
In chinese patent application CN105656456B, a high-speed and high-precision digital pulse generating circuit and pulse generating method are disclosed, and the patent requires that pulse parameters (period and pulse width) are configured by a register control circuit, then a start signal is sent out, and then the pulse generating circuit generates periodic pulses according to the configuration. This patent, although producing digital pulses with high accuracy, stores only one timing setting (register configuration). Digital IC functional testing typically requires multiple timing settings and requires the ability to change timing (Time On Fly, TOF) in real Time, which cannot be accommodated.
A programmable digital pulse generator is disclosed in chinese patent application publication No. CN101907881a, which can output up to 16 pulse signals, and modern semiconductor test equipment generally requires hundreds of pulse outputs. In addition, the chip used in the patent is relatively low-end, and the timing precision cannot be made too high.
The core of the digital IC function test time sequence and waveform generation method is the generation of high-precision programmable pulse signals. There are many domestic patents on the method for generating the high-precision programmable pulse signal, but the method is not suitable for the application scene of the digital IC function test. While there is little patent about digital IC functional test timing and waveform generation methods.
Disclosure of Invention
In order to solve the above technical problems, the present invention provides a timing and waveform generation device and method.
The technical scheme of the device is a time sequence and waveform generating device, which comprises the following components: a vector generator, a plurality of sets of time sequence and waveform processing units; each group of time sequence and waveform processing units consists of a time sequence generator and a waveform controller; the vector generators are respectively connected with the plurality of groups of time sequence generators; the time sequence generator is connected with the waveform controller; the vector generator is used for providing test vectors and time sequence information for the plurality of groups of time sequence and waveform processing units; the time sequence generator is used for generating a timing edge according to the time sequence information; the waveform controller is configured to convert the test vector into a waveform signal according to a timing edge.
Preferably, the vector generator is composed of a vector memory, a sequence controller and a time sequence memory; the vector memory, the sequence controller and the sequence memory are sequentially connected.
Further, the vector memory is used for storing the test vectors required by the test of the plurality of groups of time sequences and waveform processing units; the time sequence storage is used for storing a plurality of groups of time sequence and time sequence configuration information required by the function test of the waveform processing unit; the sequence controller reads the test vector and the corresponding time sequence from the vector memory and the time sequence memory according to the test flow in the beat of the test period.
Further, the timing store provides 32 independent sets of timing configurations for each set of timing and waveform processing units.
Preferably, the number of the vector generator supporting the time sequence and the waveform processing unit test is N, N is more than or equal to 256, and N is a positive integer.
Preferably, the timing generator is composed of 8 groups of timing edge generating circuits which are of the same structure and are independent, the timing edge generating circuits are 3-level timing circuits and are composed of a programmable counter, a high-speed parallel-serial converter and a programmable delay chain; the programmable counter, the high-speed parallel-serial converter and the programmable delay chain are sequentially connected.
Further, the programmable counter is used for realizing coarse timing, and the coarse timing precision is a and a is more than 5ns; the high-speed parallel-serial converter is used for realizing fine timing, and the fine timing precision is a/4; the programmable delay chain is used for realizing fine timing, and comprises 32 stages of delay units, wherein the fine timing precision is a/128.
Further, the programmable counter, the high-speed parallel-serial converter and the programmable delay chain are provided with a period control interface timer and a compensation control interface offset, wherein the timer is used for setting the timing edge moment of the current period, and the offset is used for setting delay deviation compensation of the timing edge.
Preferably, the waveform controller is composed of a signal distributor and a pattern formatter; the signal distributor is connected with the pattern formatter.
Further, the signal distributor distributes each timing edge signal to a sub-processing unit corresponding to the code pattern formatter; the pattern formatter has a plurality of independent sub-processing units, and the pattern formatter outputs a timing waveform in combination with a test vector and a timing edge.
Preferably, each set of timing and waveform processing units further comprises a driver, and the driver is connected with the waveform controller; the driver is used for level modulating the output waveform.
The technical scheme of the method is a time sequence and waveform generation method, which is characterized by comprising the following steps:
step 1: the signal distributor distributes each timing edge signal to the corresponding sub-processing unit code pattern of the code pattern formatter;
step 2: the code pattern formatter receives the test vectors provided by the vector generator, and generates waveforms according to the test period code patterns of the test vectors in each test period and the timing edge signals corresponding to the code patterns of the sub-processing units.
Preferably, the number of the corresponding sub-processing unit patterns in step 1 is M, and each sub-processing unit pattern corresponds to at least one timing edge signal.
Preferably, the test vector in step 2 is pata j Represents the j-th test vector, j E [1, N]；
The test period is T, and the test vector pata j The code pattern in the kth test period is code j,k ；code j,k And (3) generating waveforms by combining the timing edge signals corresponding to the code patterns of the sub-processing units in the step 1.
The invention aims to provide a time sequence and waveform generation device. A scheme of a timing generator and a waveform controller is adopted. The timing generator comprises a 3-stage delay adjusting circuit and is responsible for generating high-precision timing edges. The waveform controller selects the corresponding timing edge to generate a waveform according to the output code pattern. And each channel is provided with an independent time sequence generator and a waveform controller, so that the expansion is convenient. The method solves the problems that the output time sequence precision of an automatic test equipment (Automatic Test Equipment, ATE) tester is not high enough, the generated waveforms are not rich, the number of output channels is small, the expansion is not easy, and the like.
The invention has the advantages that: a 3-level delay adjusting circuit is adopted to provide picosecond-level timing precision; providing independent 32 sets of timing settings per channel and supporting a real-Time On Fly (TOF) function; each channel provides not less than 8 timing edges, so that the time sequence control is more flexible; each channel is provided with an independent waveform generator for supporting the common output code pattern of ATE; the time delay compensation function is provided, the test precision is further improved, and the test error is reduced.
Drawings
Fig. 1: the system block diagram of the present invention;
fig. 2: the vector generator functional block diagram of the present invention;
fig. 3: the timing generator functional block diagram of the present invention;
fig. 4: the timing generator timing diagram of the present invention;
fig. 5: the waveform controller of the present invention is a functional block diagram;
fig. 6: the waveform controller timing diagram of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The system block diagram of the time sequence and waveform generating device in the function test of the invention is shown in figure 1, and a vector generator and a plurality of groups of time sequence and waveform processing units are shown; each group of time sequence and waveform processing units consists of a time sequence generator and a waveform controller; the vector generators are respectively connected with the plurality of groups of time sequence generators; the time sequence generator is connected with the waveform controller; the vector generator is used for providing test vectors and time sequence information for the plurality of groups of time sequence and waveform processing units; the time sequence generator is used for generating a timing edge according to the time sequence information; the waveform controller is configured to convert the test vector into a waveform signal according to a timing edge.
The vector generator consists of a vector memory, a sequence controller and a time sequence memory; the vector memory, the sequence controller and the sequence memory are sequentially connected.
The vector memory is used for storing the test vectors required by the test of the plurality of groups of time sequences and the waveform processing units; the time sequence storage is used for storing a plurality of groups of time sequence and time sequence configuration information required by the function test of the waveform processing unit; the sequence controller reads the test vector and the corresponding time sequence from the vector memory and the time sequence memory according to the test flow in the beat of the test period.
The timing memory provides 32 sets of independent timing configurations for each set of timing and waveform processing units.
The number of the vector generators supporting time sequence and waveform processing unit tests is N, N is more than or equal to 256, and N is a positive integer.
The timing generator consists of 8 groups of timing edge generating circuits which are of the same structure and are independent, wherein the timing edge generating circuit is a 3-level timing circuit and consists of a programmable counter, a high-speed parallel-serial converter and a programmable delay chain; the programmable counter, the high-speed parallel-serial converter and the programmable delay chain are sequentially connected.
The programmable counter is used for realizing coarse timing, and the coarse timing precision is alpha and alpha is more than 5ns; the high-speed parallel-serial converter is used for realizing fine timing, and the fine timing precision is a/4; the programmable delay chain is used for realizing fine timing, and comprises 32 stages of delay units, wherein the fine timing precision is a/128.
The programmable counter, the high-speed parallel-serial converter and the programmable delay chain are provided with a period control interface timer and a compensation control interface offset, wherein the timer is used for setting the timing edge moment of the current period, and the offset is used for setting the delay deviation compensation of the timing edge.
The waveform controller consists of a signal distributor and a code pattern formatter; the signal distributor is connected with the pattern formatter.
The signal distributor distributes each timing edge signal to a sub-processing unit corresponding to the code pattern formatter; the pattern formatter has a plurality of independent sub-processing units, and the pattern formatter outputs a timing waveform in combination with a test vector and a timing edge.
Each set of time sequence and waveform processing unit further comprises a driver, and the driver is connected with the waveform controller; the driver is used for level modulating the output waveform.
In a specific embodiment, the 1 vector generator, the N groups of time sequences and the waveform processing units are implemented on an FPGA chip with the process of less than or equal to 28 nm. N=256 denotes the number of timing and waveform processing units supported by the vector generator, and a=8ns denotes coarse timing adjustment accuracy. The driver selects MAX9972 four-channel 300Mbps Pin Electronics chip from the meixin company.
Embodiments of the present invention are described below with reference to fig. 1 to 6.
FIG. 2 is a functional block diagram of a vector generator of the present invention, the vector generator is composed of a vector memory, a sequence controller and a time sequence memory, the vector memory, the sequence controller and the time sequence memory in the vector generator are connected in sequence; the vector memory is used for storing test vectors required by functional tests of all channels; the time sequence storage is used for storing time sequence configuration information required by the function test of each channel, and each channel is provided with 32 groups of independent time sequence configurations; the sequence controller reads the test vector and the corresponding time sequence from the vector memory and the time sequence memory according to the test flow and with the beat of the test period; the vector generator supports the number of timing and waveform processing units n=256.
FIG. 3 is a functional block diagram of a timing generator of the present invention, consisting of 8 sets of identically structured and independent timing edge generation circuits, which are 3-stage timing circuits, consisting of programmable counters, high-speed parallel-to-serial converters, and programmable delay chains; the programmable counter, the high-speed parallel-serial converter and the programmable delay chain are connected in sequence; the programmable counter is used for realizing coarse timing, and the coarse timing precision is alpha and alpha is more than 5ns; the high-speed parallel-serial converter is used for realizing fine timing, and the fine timing precision is a/4; the programmable delay chain is used for realizing fine timing, and comprises 32 stages of delay units, wherein the fine timing precision is a/128. a=8ns, the final timing edge adjustment accuracy can reach 8 ns/4/32=62.5 ps.
The programmable counter, the high-speed parallel-serial converter and the programmable delay chain are provided with a period control interface timer and a compensation control interface offset, wherein the timer is used for setting the timing edge moment of the current period, and the offset is used for setting the delay deviation compensation of the timing edge;
for further explanation of the operation principle of the timing generator of the present invention, please refer to the timing diagram of the timing generator shown in fig. 4. Here, taking the generation of 1 timing edge as an example, assuming that the counter period is 8ns, the current period is set to 8ns×10+2ns+3×62.5ps by the timer, and the offset channel compensation control interface is set to 2×62.5ps, so that the final timing edge position is 8ns×10+2ns+ (3+2) ×62.5ps.
Fig. 5 is a functional block diagram of a waveform controller according to the present invention, where the ith waveform controller is composed of a signal divider and a pattern formatter, and the number of support test channels of the vector generator is n=256; the signal distributor is connected with the code pattern formatter; the signal distributor distributes each timing edge signal to a sub-processing unit corresponding to the code pattern formatter; the pattern formatter has a plurality of independent sub-processing units, and combines the test vectors and the timing edges to output timing waveforms. For example, NRZ pattern processing units only need timing_edge_1 timing edges, while RZ pattern processing units need timing_edge_2 and timing_edge_3 timing edges. The pattern formatter has a plurality of independent sub-processing units, and the pattern formatter outputs a timing waveform in combination with the test vector and the timing edge.
To further explain the operation principle of the waveform controller of the present invention, please refer to the timing diagram of the waveform controller shown in fig. 6. In test cycle 1, test vector "1" employs a pattern NRZ, so on the rising edge of time_edge_1, the WAVE output changes from 0 to 1. In test cycle 2, test vector "2" employs a pattern NRZ, so on the rising edge of time_edge_1, the WAVE output changes from 1 to 0. In test cycle 3, the test vector is "1" and the code pattern is RZ, so the WAVE output changes from 0 to 1 on the rising edge of time_edge_2 and from 1 to 0 on the rising edge of time_edge_3.
The following describes a timing and waveform generation method according to the present invention with reference to fig. 1 to 6, which is characterized by comprising:
step 1: the signal distributor distributes each timing edge signal to the corresponding sub-processing unit code pattern of the code pattern formatter;
step 2: the code pattern formatter receives the test vectors provided by the vector generator, and generates waveforms according to the test period code patterns of the test vectors in each test period and the timing edge signals corresponding to the code patterns of the sub-processing units.
The number of the corresponding sub-processing unit code patterns in step 1 is 2, namely an NRZ code pattern and an RZ code pattern, wherein the NRZ code pattern processing unit needs a timing_edge_1 timing edge signal, and the RZ code pattern processing unit needs a timing_edge_2 timing edge signal and a timing_edge_3 timing edge signal;
the test vector in step 2 is pata j J∈ {1,2}; test vector "1", pata 1 Test vector "2", pata 2 ；
The test period is T=8ns, and the test vector pat1 1 In test period 1, the test vector is pat1 1 The pattern used is NRZ, so on the rising edge of time_edge_1, the WAVE output goes from 0 to 1. In the 2 nd test period, the test vector is pat1 2 The code pattern used is NRZ, so on the rising edge of time_edge_1, WAVE is output from1 becomes 0. In the 3 rd test period, the test vector is pat1 1 The pattern used is RZ, so the WAVE output goes from 0 to 1 on the rising edge of time_edge_2 and from 1 to 0 on the rising edge of time_edge_3.
Although terms of vector generators, timing and waveform processing units, timing generators, waveform controllers, drivers, vector memories, sequence controllers, timing memories, timing edge generation circuits, programmable counters, high-speed parallel-to-serial converters, programmable delay chains, signal splitters, pattern formatters, etc., are used more herein, the possibility of using other terms is not precluded. These terms are only used to facilitate a more complete description of the nature of the invention and should be construed as requiring no additional limitations whatsoever.
It should be understood that the foregoing description of the preferred embodiments is not intended to limit the scope of the invention, but rather to limit the scope of the claims, and that those skilled in the art can make substitutions or modifications without departing from the scope of the invention as set forth in the appended claims.
Claims (3)
1. A timing and waveform generation method based on a timing and waveform generation device, characterized in that:
the timing and waveform generation device includes: a vector generator, a plurality of groups of time sequence and waveform processing units respectively connected with the vector generator; each group of time sequence and waveform processing units consists of a time sequence generator and a waveform controller, and the time sequence generator is connected with the waveform controller;
the vector generator is used for providing test vectors and time sequence information for the plurality of groups of time sequence and waveform processing units;
the time sequence generator is used for generating a timing edge according to the time sequence information;
the waveform controller is used for converting the test vector into a waveform signal according to the timing edge;
the vector generator consists of a vector memory, a sequence controller and a time sequence memory; the vector memory, the sequence controller and the sequence memory are sequentially connected;
the vector memory is used for storing the test vectors required by the test of the plurality of groups of time sequences and the waveform processing units; the time sequence storage is used for storing a plurality of groups of time sequence and time sequence configuration information required by the function test of the waveform processing unit; the sequence controller reads test vectors and corresponding time sequences from the vector memory and the time sequence memory according to a test flow in the beat of a test period;
the time sequence storage provides 32 groups of independent time sequence configurations for each group of time sequence and waveform processing units;
the number of the vector generators supporting time sequence and waveform processing unit tests is N, N is more than or equal to 256, and N is a positive integer;
the timing generator consists of 8 groups of timing edge generating circuits which are of the same structure and are independent, wherein the timing edge generating circuit is a 3-level timing circuit and consists of a programmable counter, a high-speed parallel-serial converter and a programmable delay chain; the programmable counter, the high-speed parallel-serial converter and the programmable delay chain are connected in sequence;
the programmable counter is used for realizing coarse timing, and the coarse timing precision is alpha and alpha is more than 5ns; the high-speed parallel-serial converter is used for realizing fine timing, and the fine timing precision is a/4; the programmable delay chain is used for realizing precise timing, and comprises 32 stages of delay units, wherein the precise timing precision is a/128;
the programmable counter, the high-speed parallel-serial converter and the programmable delay chain are provided with a period control interface timer and a compensation control interface offset, wherein the timer is used for setting the timing edge moment of the current period, and the offset is used for setting the delay deviation compensation of the timing edge;
the waveform controller consists of a signal distributor and a code pattern formatter; the signal distributor is connected with the code pattern formatter;
the signal distributor distributes each timing edge signal to a sub-processing unit corresponding to the code pattern formatter; the code formatter is provided with a plurality of independent sub-processing units, and combines the test vector and the timing edge to output a time sequence waveform;
each set of time sequence and waveform processing unit further comprises a driver, and the driver is connected with the waveform controller; the driver is used for carrying out level modulation on the output waveform;
the waveform generation method comprises the following steps:
step 1: the signal distributor distributes each timing edge signal to the corresponding sub-processing unit code pattern of the code pattern formatter;
step 2: the code pattern formatter receives the test vectors provided by the vector generator, and generates waveforms according to the test period code patterns of the test vectors in each test period and the timing edge signals corresponding to the code patterns of the sub-processing units.
2. The timing and waveform generation method based on the timing and waveform generation apparatus of claim 1, wherein the timing edge signals in step 1 are timing_edge_1, timing_edge_2, timing_edge_8, i.e. 8 kinds of timing edge signals;
the number of the corresponding sub-processing unit code patterns in step 1 is M, and each sub-processing unit code pattern corresponds to at least one timing edge signal.
3. The method of generating time sequence and waveform based on time sequence and waveform generating apparatus as claimed in claim 2, wherein said test vector in step 2 is pata j Represents the j-th test vector, j E [1, N]；
The test period is T, and the test vector pata j The code pattern in the kth test period is code j,k ；
code j,k And (3) generating waveforms by combining the timing edge signals corresponding to the code patterns of the sub-processing units in the step 1.
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| CN104965169A (en) * | 2015-07-29 | 2015-10-07 | 江苏杰进微电子科技有限公司 | Full-automatic IC electric signal test device and test method |
| CN108181575A (en) * | 2017-12-28 | 2018-06-19 | 南京国睿安泰信科技股份有限公司 | The digital waveform test system and production method of integrated circuit tester |
| CN209198615U (en) * | 2018-10-24 | 2019-08-02 | 武汉精鸿电子技术有限公司 | A kind of timing and waveform generating |
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