CN104965169A - Full-automatic IC electric signal test device and test method - Google Patents
Full-automatic IC electric signal test device and test method Download PDFInfo
- Publication number
- CN104965169A CN104965169A CN201510453805.6A CN201510453805A CN104965169A CN 104965169 A CN104965169 A CN 104965169A CN 201510453805 A CN201510453805 A CN 201510453805A CN 104965169 A CN104965169 A CN 104965169A
- Authority
- CN
- China
- Prior art keywords
- signal
- module
- jump
- test
- automatic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
The invention provides a full-automatic IC electric signal test device. The full-automatic IC electric signal test device is used for testing an IC device. The full-automatic IC electric signal test device comprises an image generation module generating a test image used for stipulating a test signal supplied to an IC device, a sequence signal generation module generating a sequential signal representing a time sequence supplying the test signal to the IC device, a filtering module filtering the test image and outputting a control signal corresponding to the test image, a fluctuation processing module delaying the sequential signal according to the control signal and applying jump to the sequential signal, and an oscillogram with the sequential signal applied by jump as a reference and generating the test signal forming the test image.
Description
Technical field
The present invention relates to field of semiconductor device test, particularly a kind of full-automatic IC electric signal measuring apparatus and method of testing.
Background technology
As everyone knows, waveform processing device comprises variable delay module test signal being postponed according to digital controlled signal.Applying control module of jumping comprises the random number data generator producing random data and the sine-wave producer producing sinusoidal wave data.And, jump and apply control module according to the data exported from random number data generator and sine-wave producer, export the digital controlled signal of expression random skip and represent the sinusoidal wave digital controlled signal jumped.IC device can be given, to test the jump performance of this IC device by the test signal being applied with random skip or sinusoidal wave jump.
But, for the jump added by the signal transmission transmitted between device, it is well known that the jump produced by transmission line loss and the jump etc. produced by intersymbol interference.Comparatively ideal, electric signal measuring apparatus can be applied with the test signal of the jump caused by transmission line loss etc. to device input, and tests the jump performance of this device.But there is following problem: the size of the jump caused by transmission line loss can dissimilate because of the waveform image of signal transmission that transmits between device.
Therefore, the object of the invention aspect comprised in this instructions is to provide a kind of full-automatic IC electric signal measuring apparatus that can solve the problems of the technologies described above and method of testing.This object is realized by the Feature Combination described in the independent claims in claims.Further, dependent claims defines more favorably concrete example of the present invention.
Summary of the invention
In order to solve the problem, an object of the present invention is to provide a kind of full-automatic IC electric signal measuring apparatus, it is the full-automatic IC electric signal measuring apparatus tested IC device, comprising: Computer image genration module, produces the test pattern for specifying the test signal that should be supplied to IC device; Clock signal generation module, produces the clock signal representing sequential test signal being supplied to IC device; Filtration module, carries out filtering to test pattern, exports and represents control signal corresponding with test pattern; Fluctuation processing module, makes according to control signal clock signal postpone, whereby jump is applied to clock signal; And oscillogram, to be applied with the clock signal of jump for benchmark, generate the test signal having defined test pattern.
The technical scheme of one of the object of the invention is realized by following content, and described full-automatic IC electric signal measuring apparatus comprises: signal output module, test signal is exported to above-mentioned IC device; Signal input module, inputs according to test signal from the output signal that IC device exports; Computer image genration module, produces the desired value image for specifying the output signal that should export from IC device; Clock signal generation module, produces and represents desired value image and the gating signal outputing signal the sequential compared; Filtration module, carries out filtering to desired value image, exports and represents control signal corresponding with desired value image; Fluctuation processing module, makes according to control signal gating signal postpone, makes jump be applied to gating signal with this; And comparison module, to be applied with the sequential of the gating signal of jump, output signal and desired value image are compared.
In addition, two of object of the present invention is to provide a kind of method of testing, and it is the method for testing of testing IC device, comprising: in the stage producing test pattern, this test pattern is for specifying the test signal that should be supplied to IC device; Produce the stage of clock signal, this clock signal represents sequential test signal being supplied to IC device; Filtering is carried out to test pattern, and exports the stage representing control signal corresponding with test pattern; Make according to control signal clock signal postpone, will jump the stage being applied to clock signal whereby; And with the clock signal being applied with jump for benchmark, generate the stage having defined the test signal of test pattern.
The technical scheme of the object of the invention two is realized by following content, and described IC device carries out the method for testing of testing, and comprising: stage test signal being exported to IC device; In the stage of input/output signal, this output signal is from the signal that IC device exports according to test signal; Produce the stage of desired value image, this desired value image is for specifying the output signal that should export from IC device; Produce the stage of gating signal, this gating signal represents the sequential compared with output signal desired value image; Filtering is carried out to desired value image, and exports the stage representing control signal corresponding with desired value image; The delaying strobe signal according to control signal, makes jump be applied to the stage of gating signal with this; And with the sequential of the gating signal being applied with jump, to the stage that output signal and desired value image compare.
Foregoing invention summary does not list all essential feature of the present invention, and the secondary combination of these syndromes also can become invention.
Accompanying drawing explanation
Fig. 1 and IC device 100 represents the formation of the full-automatic IC electric signal measuring apparatus 20 that embodiments of the present invention relate to together.
Fig. 2 represents the jump control module 26 of embodiments of the present invention and the formation of fluctuation processing module 28.
Fig. 3 represents an example of the formation of the variable delay module 42 of embodiments of the present invention.
Fig. 4 represents through the high signal waveform of the logic inversion frequency before transmission line and the high signal waveform of the logic inversion frequency after transmission line.
Fig. 5 represents the waveform through the low signal waveform of the logic inversion frequency before transmission line and the low signal of the logic inversion frequency after transmission line.
Fig. 6 represents the generation probability of the random waveform jump signal that the display sine wave that the random waveform generation module 58 related to by embodiments of the present invention generates jumps.
Fig. 7 represents an example of the formation of the probability flux module 60 of embodiments of the present invention.
Fig. 8 represents the generation probability of the random skip signal generated by the probability flux module 60 of embodiments of the present invention.
Fig. 9 represents the generation probability by sinusoidal wave for the display random waveform jump signal of jump and the jump signal of random skip signal plus gained.
Figure 10 and IC device 100 represents the formation of the full-automatic IC electric signal measuring apparatus 20 of the 1st variation of embodiments of the present invention together.
Figure 11 represents formation and the jump control module 26 of the clock signal generation module 24 of the 2nd variation that embodiments of the present invention relate to.
Description of reference numerals: 20: full-automatic IC electric signal measuring apparatus
,22: Computer image genration module
,24: clock signal generation module
,26: jump control module
,28: fluctuation processing module
,30: oscillogram
,32,44: signal output module
,34,40: signal input module
,36: comparison module
,42: variable delay module
,56: filtration module
,58: random waveform generation module
,60: probability flux module
,62:AD converter
,64,302: summation module
, 66: gain control module
,68: apply control module
,70: outer module clock load module
,72: inner module clock generating module
,74: clock selection module
,100:IC device
,200: delay element
,202: selector switch
,204: selector switch control module
,300:LFSR
,304: ask differential mode block
,306: probability output module
,310: shift register
,402: the 1 summitors
,404: the 2 summitors
,406: accumulator module
,408: latch
,410: the 3 summitors
,412: coarse delay circuit
,414: fine delay circuit
,416: jump and apply handover module.
Embodiment
According to working of an invention mode, the present invention will be described below, but following embodiment does not limit the invention of claim, and the combination of feature illustrated in embodiments, and non-fully module is necessary in invention solution.
Fig. 1 represents formation and the IC device 100 of the full-automatic IC electric signal measuring apparatus 20 of embodiments of the present invention.Full-automatic IC electric signal measuring apparatus 20 exports the test signal being applied with jump to IC device 100, and compares the output signal exported from IC device 100 and desired value according to this test signal, comes whereby to test IC device 100.Full-automatic IC electric signal measuring apparatus 20 comprises Computer image genration module 22, clock signal generation module 24, jump control module 26, fluctuation processing module 28, waveform Figure 30, signal output module 32, signal input module 34 and comparison module 36.
Computer image genration module 22 produces the test pattern for specifying the test signal that should be supplied to IC device 100.As an example of Computer image genration module 22, the test pattern of the waveform for specifying the test signal that should be supplied to IC device 100 can be produced.More specifically, as an example of Computer image genration module 22, can produce a kind of test pattern in the test period of each regulation, this test pattern is used to specify the retardation of the retardation of the rising edge distance benchmark sequential of test signal and the drop edge distance benchmark sequential of test signal.In addition, Computer image genration module 22 produces the desired value image of a kind of output signal of regulation, and this output signal should export from IC device 100 according to the supply of test signal.Such as, Computer image genration module 22 can produce the desired value image of the logical value for specifying the output signal that export from IC device 100.
Clock signal generation module 24 produces clock signal, and this clock signal represents sequential test signal being supplied to IC device 100.As an example, clock signal generation module 24 can produce the clock signal of the benchmark sequential represented in test period.In addition, clock signal generation module 24 produces gating signal, and this gating signal represents the sequential compared with output signal desired value image.
Jump control module 26 exports control signal, and this control signal represents the jump that should be applied to test signal.As an example, jump control module 26 can export digital value and be used as control signal, and this digital value represents the size of the jump that should be applied to test signal.Fluctuation processing module 28 makes clock signal postpone according to control signal, whereby jump is applied to clock signal.As an example of fluctuation processing module 28, can, in each test period, the clock signal produced by clock signal generation module 24 be made to postpone the value represented by control signal.Then, the clock signal being applied with jump is supplied to waveform Figure 30 by the processing module 28 that fluctuates.
Waveform Figure 30, to be applied with the clock signal of jump for benchmark, generates the test signal having defined test pattern.That is, waveform Figure 30 is to be applied with the clock signal of jump for benchmark, generates by the test signal of the waveform of test pattern defined.As an example of waveform Figure 30, the retardation of the rising edge can specified by test pattern makes to be applied with the clock signal delay of jump, and generates the test signal of rising with the sequential of this clock signal postponed.Again, as an example of waveform Figure 30, the retardation of the drop edge can specified by test pattern makes to be applied with the clock signal delay of jump, and generates the test signal of decline with the sequential of this clock signal postponed.
Signal output module 32 exports the test signal generated by waveform Figure 30 to IC device 100.Signal input module 34 inputs the output signal exported from IC device 100 according to test signal.
Comparison module 36, in the sequential of the gating signal produced by clock signal generation module 24, compares the output signal inputted by signal input module 34 and the desired value image produced by Computer image genration module 22.As an example of comparison module 36, can according to the sequential of gating signal, to the logical value of output signal with compared by the logical value of desired value image specification.Then, the comparative result of comparison module 36 output signal output and desired value image.
Fig. 2 represents the formation of jump control module 26 of the present embodiment and fluctuation processing module 28.Fluctuation processing module 28 comprises signal input module 40, variable delay module 42 and signal output module 44.
Signal input module 40 inputs the clock signal produced by clock signal generation module 24, and inputted clock signal is supplied to variable delay module 42.Variable delay module 42 makes the clock signal inputted by variable delay module 42 postpone following retardation: this retardation is corresponding with the size of the jump specified by the control signal supplied by jump control module 26.Whereby, according to variable delay module 42, the jump of the size of being specified by control signal can be applied to clock signal.The clock signal being applied with jump by variable delay module 42 is supplied to waveform Figure 30 by signal output module 44.
Jump control module 26 comprises filtration module 56, random waveform generation module 58, probability flux module 60, AD converter 62, summation module 64, gain control module 66, applies control module 68, outer module clock load module 70, inner module clock generating module 72 and clock selection module 74.Filtration module 56 carries out filtering to the test pattern produced by Computer image genration module 22, generates the relevant jump signal of image of the jump representing corresponding to test pattern.More specifically, filtration module 56 carries out filtering by test pattern, generates and represents that the image depending on the jump of the waveform of test signal is correlated with jump signal.
Random waveform generation module 58 produces the random waveform jump signal of the jump representing random waveform.As an example of random waveform generation module 58, can export and represent the sinusoidal wave random waveform jump signal jumped.Probability flux module 60 produces the random skip signal representing random skip.AD converter 62 samples the simulating signal that the simulation signal generator by outer module produces, and exports the simulation jump signal of the jump representing corresponding with the simulating signal obtained.
Summation module 64 is used as control signal output from the image that filtration module 56 exports jump signal of being correlated with.Whereby, summation module 64 can export and represent control signal corresponding with test pattern.
Further, summation module 64 can also according to the phase increase control signal of kind being used to specify the jump that should be applied to test signal, select at least one in random waveform jump signal, random skip signal and simulation jump signal, and exporting following control signal, this control signal is the signal being added by relevant to image for selected jump signal jump signal and obtaining.That is, as an example of summation module 64, can will represent the jump variety classes signal corresponding with test pattern, correspond to test pattern control signal with expression and be added.Summation module 64 can from input phase increase control signals such as the controllers of such as Computer image genration module 22 and this full-automatic IC electric signal measuring apparatus 20.
In addition, as an example of summation module 64, any one signal that can export in random waveform jump signal, random skip signal and simulation jump signal is used as control signal.In addition, as an example of summation module 64, also can export following signal and be used as control signal: this signal is added and the signal that obtains any more than 2 or 2 in random waveform jump signal, random skip signal and simulation jump signal.
Gain control module 66, according to gain control signal, makes the control signal exported from summation module 64 amplify or decay.Above-mentioned gain control signal specifies the gain of the jump that should be applied to test signal.As an example of gain control module 66, when by binary code representation control signal, control signal can be amplified or decay by shift operation.Gain control module 66 such as can from input gain control signals such as the controllers of image generating module 22 and this full-automatic IC electric signal measuring apparatus 20.
Apply control module 68 input and apply control signal, this applying control signal is used to specify whether jump is applied to clock signal, when appointment does not apply to jump, control signal is set to the value not applying to jump.That is, when applying control module 68 and not applied to jump by the appointment of applying control signal, control signal is set to the value that clock signal can not be postponed by variable delay module 42.Whereby, according to applying control module 68, can control whether jump is applied to test signal in real time.Apply control module 68 and can apply control signal from inputs such as the controllers of such as Computer image genration module 22 and this full-automatic IC electric signal measuring apparatus 20.
Outer module clock load module 70 inputs the outer module clock signal synchronous with the clock signal that fluctuation processing module 28 inputs, that is, the outer module clock signal of the system clock synchronization of input and this full-automatic IC electric signal measuring apparatus 20.Then, inputted outer module clock signal is supplied to clock selection module 74 by outer module clock load module 70.
Inner module clock generating module 72 produces and the nonsynchronous inner module clock signal of clock signal inputing to the processing module 28 that fluctuates.That is, the nonsynchronous inner module clock signal of system clock with this full-automatic IC electric signal measuring apparatus 20 is produced.As an example, inner module clock generating module 72 can be crystal oscillator etc.In addition, produced inner module clock signal is supplied to clock selection module 74 by inner module clock generating module 72.
Signal selected by clock selection module 74 input clock, and this clock selection signal specifies any one signal in outer module clock signal or inner module clock signal.Clock selection module 74, according to clock selection signal, exports any one signal in outer module clock signal and inner module clock signal as clock signal.Clock selection module 74 can select signal from input clocks such as the controllers of such as Computer image genration module 22 and this full-automatic IC electric signal measuring apparatus 20.
Clock signal is supplied to random waveform generation module 58, probability flux module 60 and AD converter 62 by clock selection module 74.Then, random waveform generation module 58 produces the random waveform jump signal of the clock signal synchronization selecting module 74 to export with self-clock.Probability flux module 60 produces the random skip signal of the clock signal synchronization selecting module 74 to export with self-clock.AD converter 62 is sampled simulating signal by the clock signal exported from clock selection module 74.
Therefore, clock selection module 74 random waveform of the system clock synchronization with this full-automatic IC electric signal measuring apparatus 20 can be jumped, random skip and corresponding jump is applied to clock signal with simulating signal.Again, clock selection module 74 can by not jumping with the random waveform of the system clock synchronization of this full-automatic IC electric signal measuring apparatus 20, random skip and the jump corresponding with simulating signal be applied to clock signal.
According to jump control module 26 as above and fluctuation processing module 28, the jump corresponding with test pattern can be applied to test signal.And, by jump control module 26 and fluctuation processing module 28, except can applying the jump corresponding with test pattern, can also irrelevant with test pattern by random waveform jump, random skip, the jumps corresponding with simulating signal etc. such as sine wave jumps, the jump caused by other reasons is applied to test signal.
Fig. 3 represents an example of the formation of the variable delay module 42 of present embodiment.Variable delay module 42 comprises multiple delay elements 200 of series arrangement, the multiple selector switchs 202 arranged corresponding to multiple delay element 200 and selector switch control module 204.After each of multiple delay element 200 makes inputted clock signal postpone according to each retardation respectively, export these clock signals.
In multiple delay element 200, the delay element 200 of first section makes the clock signal inputted by signal input module 40 postpone.Delay element 200 beyond first section makes the clock signal exported by the selector switch 202 that the delay element 200 with leading portion is corresponding postpone.The delay element 200 of latter end exports clock signal to outer module via signal output module 44.
Each of multiple selector switch 202 selects any one signal in the clock signal through phase delay element 200 or the clock signal without phase delay element 200 (that is, the clock signal from the selector switch 202 corresponding with the delay element 200 of leading portion exports).Then, multiple selector switch 202 each export selected by clock signal.
Selector switch control module 204 controls each of multiple selector switch 202 according to the control signal exported from jump control module 26, to select the clock signal through phase delay element 200, or selects the clock signal without phase delay element 200.More specifically, selector switch control module 204 controls multiple selector switch 202, make the total delay amount till signal input module 40 to signal output module 44, become the value corresponding with the size of the jump represented by the control signal exported from jump control module 26.Whereby, according to variable delay module 42, clock signal can be made to postpone the retardation corresponding with the size of the jump represented by control signal.
In addition, as an example of variable delay module 42, can with comprising analog variable delay circuit and D/A conversion module replaces multiple delay element 200, multiple selector switch 202 and selector switch control module 204.Analog variable delay circuit makes clock signal postpone the retardation corresponding with analog control signal.
As an example of analog variable delay circuit, the output capacity of buffer circuit can be made according to analog control signal to change, make the clock signal through this buffer circuit postpone whereby.Again, as an example of analog variable delay circuit, the drive current being applied to buffer circuit can be made according to analog control signal to change, make the clock signal through this buffer circuit postpone whereby.
Analog control signal is given analog variable delay circuit by D/A conversion module, and this analog control signal is the signal carrying out DA conversion to control signal and obtain.According to this kind of variable delay module 42, can trickleer and control lag amount at high speed.
In addition, variable delay module 42, except can comprising multiple delay element 200, multiple selector switch 202 and selector switch control module 204, more can comprise analog variable delay circuit and D/A conversion module.When this situation, analog variable delay circuit is such as connected to the back segment of multiple delay element 200 in series.Again, the digital signal exported from selector switch control module 204 is carried out DA conversion and the analog control signal that obtains gives analog variable delay circuit by D/A conversion module.
The digital controlled signal that selector switch control module 204 will input from jump control module 26, be divided into two kinds of following digital signals, namely represent the digital signal of the coarse delay amount postponed by multiple delay element 200, and represent by the digital signal of the fine delay of analog variable delay circuit delay amount.And selector switch control module 204 is according to representing that the digital signal of coarse delay amount switches multiple selector switch 202.Selector switch control module 204 will represent that the digital signal of fine delay amount gives D/A conversion module.
Fig. 4 represents the waveform through the waveform of the high signal of the logic inversion frequency before transmission line and the high signal of the logic inversion frequency after transmission line.Fig. 5 represents the waveform through the waveform of the low signal of the logic inversion frequency before transmission line and the low signal of the logic inversion frequency after transmission line.
Filtration module 56 carries out digital filtering to the test pattern exported from Computer image genration module 22, carrys out synthetic image whereby and to be correlated with jump signal, and this image jump signal of being correlated with represents waveform according to test signal and puts on the jump of this test signal.Whereby, filtration module 56 can generate the signal representing the jump produced by intersymbol interference and transmission line loss etc.
Herein, the jump that transmission line loss causes, produces because of the signal stabilization deterioration in characteristics through transmission line.But, for the high-frequency signal shown in Fig. 4, even if stability characteristic (quality) is deteriorated, also because (that is, before arriving next logic level completely) before during stabilization passing through will start next change, thus jump little.In contrast, for the signal of the occurrence logic reversion after long-time of the L level (or H level) shown in Fig. 5, directly can be reflected in jump with the stability characteristic (quality) corresponding delay that is deteriorated, therefore jump large.
Therefore, when inputting the test pattern of specifying low-frequency waveform, filtration module 56 can carry out filtering and be correlated with jump signal to increase the image that will export, when input specify the test pattern of high-frequency waveform time, this filtration module 56 can carry out filtering and be correlated with jump signal with the image reducing to export.More specifically, such as, when inputting the test pattern of any one long-continued waveform of specifying in H logical OR L logic, filtration module 56 increases the image that will export and to be correlated with jump signal.Again, such as, when input specify H logic and L logic with the test pattern of short period alternately repeated waveform time, the image that filtration module 56 reduces to export is correlated with jump signal.By this, according to filtration module 56, can generate and represent that the image of jump caused by transmission line loss is correlated with jump signal.
Fig. 6 represents the generation probability of the random waveform jump signal that the display sine wave generated by the random waveform generation module 58 of present embodiment jumps.As an example of random waveform generation module 58, can with the clock signal synchronization ground discrete value data of the jump waveform sequentially reading the expression one-period stored in advance that circulates, export the random waveform jump signal representing that random waveform is jumped whereby.Whereby, the jump that sine wave can jump by random waveform generation module 58, square wave jumps, integrated distribution represents and the jump etc. represented by binomial distribution are applied to test signal.As an example of random waveform generation module 58, can before testing, the inputs such as the first memory body from outer module and Storage Media represent the discrete value data of jump waveform.
Especially, as an example of random waveform generation module 58, can with the clock signal synchronization ground discrete value data of the sine wave signal sequentially reading the expression one-period stored in advance that circulates.Whereby, random waveform generation module 58 can export the random waveform jump signal that the expression sine wave shown by the probability distribution of Fig. 6 jumps.
Fig. 7 represents an example of the formation of the probability flux module 60 of present embodiment.Fig. 8 represents the generation probability of the random skip signal generated by the probability flux module 60 of present embodiment.
As an example of probability flux module 60, linear feedback shift register (LFSR) 300, summation module 302 can be comprised, ask differential mode block 304 and probability output module 306.LFSR300 comprises the shift register 310 of specified sections, and produces pseudorandom signal from the register of the latter end of shift register 310.More specifically, LFSR300 is by being handled as follows to produce pseudorandom signal.
First, LFSR300 carries out the nonequivalence operation of the bit value stored in a register, and this register is by the register of the irreducible function defined for generation of pseudorandom sequence in shift register 310.Secondly, the bit value in the register being stored in latter end exports as pseudorandom signal by LFSR300, is shifted to each bit value in shift register 310.Subsequently, nonequivalence operation result is stored to the register of just section by LFSR300.LFSR300 repeats above process in each clock period.Whereby, LFSR300 can produce pseudorandom signal by simply forming.
In each clock period, summation module 302 exports additive value, and this additive value is the value being added by the bit value of the multiple registers contained by the shift register 310 in LFSR300 and obtaining.Differential mode block 304 is asked to deduct the half value of the number storing multiple registers of bit value that summation module 302 adds and the half value subtraction value that obtains output from additive value.Such as, when register numerical example contained in shift register 310 is as during for n, ask differential mode block 304 to export half value subtraction value that the additive value calculated from summation module 302 deducts (n/2) and acquisition.Probability output module 306 exports the random skip signal corresponding with half value subtraction value.
Herein, in the pseudorandom signal generated by LFSR300, the generation probability of 0 (or 1) is in close proximity to 50%.Meanwhile, when shift register 310 is n section, the probability only storing 1 (or 0) in the interior register of shift register 310 is 1/ (2
n-1).Therefore, the additive value that all bit values being stored in register are added gained is reduced by half and the waveform of random skip signal that obtains, close to the normal distribution being crest with 0 as shown in Figure 8.
Thus, according to the probability flux module 60 of Fig. 7, can by simply forming the random skip signal producing and represent random skip.Moreover, as an example of LFSR300, can before testing, the inputs such as the first memory body from outer module and Storage Media represent the value of the kind of pseudorandom signal, and this value is stored to shift register 310.
Fig. 9 represents the generation probability by sinusoidal wave for the display random waveform jump signal of jump and the jump signal of random skip signal plus gained.As an example of summation module 64, following jump signal can be exported as control signal, this jump signal is the jump signal random waveform jump signal generated by random waveform generation module 58 and the random skip signal plus to be generated by probability flux module 60 obtained.
Such as, be applied in the jump of the signal transmitted between semiconductor devices, comprise the jump produced by the reason determined as sine wave jumps and the random skip produced by uncertain reason.Summation module 64 can at random jump to random waveforms such as the jump corresponding with test pattern, sinusoidal wave jump, random skip and and the corresponding jump of simulating signal combine, addition of whereby these being jumped.Therefore, according to full-automatic IC electric signal measuring apparatus 20, the jump produced by multiple reason can be reproduced, and this jump is applied to test signal.
Figure 10 represents formation and the IC device 100 of the full-automatic IC electric signal measuring apparatus 20 of the 1st variation of present embodiment.The full-automatic IC electric signal measuring apparatus 20 of this variation have employed the roughly the same formation of the assembly of symbol same as shown in Figure 1 and function, therefore hereinafter, except being described difference, omits remaining explanation.
Jump is applied to gating signal by fluctuation processing module 28, but not is applied to clock signal.That is fluctuation processing module 28, according to control signal, makes the gating signal being supplied to comparison module 36 from clock signal generation module 24 postpone, whereby jump is applied to gating signal.
Jump control module 26 exports expression should be applied to output signal control signal, but not expression should be applied to test signal control signal.And the filtration module that jump control module 26 has 56 pairs of desired value images carry out filtering, but not carry out filtering to test pattern, then export and represent control signal corresponding with desired value image.Comparison module 36, to be applied with the sequential of the gating signal of jump, compares output signal and desired value image.
The full-automatic IC electric signal measuring apparatus 20 of variation as above, by the jump corresponding with desired value image, is applied to the gating signal comparing sequential representing and output signal with desired value.Whereby, according to the full-automatic IC electric signal measuring apparatus 20 of variation, when the jump corresponding with desired value image is applied to output signal, can obtain the comparative result of output signal with desired value.Moreover full-automatic IC electric signal measuring apparatus 20 can also possess simultaneously: the clock signal generation module 24 and the jump control module 26 that the jump corresponding with test pattern are applied to the clock signal shown in Fig. 1; And the jump corresponding with desired value image is applied to clock signal generation module 24 and the jump control module 26 of the gating signal shown in Figure 10.
Figure 11 represents formation and the jump control module 26 of the clock signal generation module 24 of the 2nd variation of present embodiment.The full-automatic IC electric signal measuring apparatus 20 of this variation have employed the roughly the same formation of the assembly of symbol same as shown in Figure 1 and function, therefore hereinafter, except being described difference, omits remaining explanation.
The full-automatic IC electric signal measuring apparatus 20 of this variation does not possess fluctuation processing module 28, and the jump corresponding with control signal is applied to clock signal at inner module by clock signal generation module 24.That is, clock signal generation module 24 exports the clock signal being applied with the jump corresponding with control signal in advance.
As an example of the clock signal generation module 24 of this variation, comprise the 1st summitor 402, the 2nd summitor 404, accumulator module 406, latch 408, the 3rd summitor 410, coarse delay circuit 412 and fine delay circuit 414.In addition, the jump control module 26 of this variation mean value of jump that exports control signal and represented by this control signal.
1st summitor 402 is from representing that the ratio data of test period deducts jump mean value.Whereby, jump control module 26, relative to the sequential produced without the waveform (edge) jumped, can apply to jump in positive dirction and negative direction.
2nd summitor 404 exports Time delay control value, and this Time delay control value is value delayed data, the ratio data deducting jump mean value and control signal being added and obtaining.Delayed data represents the retardation of the benchmark sequential in the sequential distance test cycle that should produce the waveform (edge) specified by test pattern.
Accumulator module 406 exports accumulated delay controlling value, and this accumulated delay controlling value is by the Time delay control value exported from the 2nd summitor 404, is added with the value exported from the 3rd summitor 410 and the value obtained.Latch 408 makes the accumulated delay controlling value exported from accumulator module 406 postpone a test period.3rd summitor 410, is added the accumulated delay controlling value exported from latch 408 with control signal and the value that obtains, gives accumulator module 406.Whereby, accumulator module 406 can export accumulated delay controlling value, and this accumulated delay controlling value is the value of carrying out cumulative addition to the Time delay control value exported from the 2nd summitor 404 and obtaining.
Coarse delay circuit 412, according to the corresponding retardation of the value of the high order bit with accumulated delay controlling value, makes the reference clock as the benchmark of test period postpone.As coarse delay circuit 412 one example, can according to Action clock cycle unit retardation reference clock is postponed.
Fine delay circuit 414, according to the corresponding retardation of the value of the low-order bit with accumulated delay controlling value, makes to be postponed by the reference clock that coarse delay circuit 412 postpones.As an example of fine delay circuit 414, can, according to the small retardation of the Action clock of this clock signal generation module 24 not enough, reference clock be postponed.Then, fine delay circuit 414 exports as clock signal the reference clock postponed to outer module.
The control signal that the applying handover module 416 that jumps will export from jump control module 26, switches and exports the 2nd summitor 404 or accumulator module 406 to.Jump and apply the switch-over control signal of handover module 416 according to outputs such as the controllers from such as Computer image genration module 22 and this full-automatic IC electric signal measuring apparatus 20, come the output destination of switch-over control signal.
According to the clock signal generation module 24 that this kind is formed, can export following clock signal, this clock signal is applied with the jump corresponding with the control signal exported from jump control module 26 in advance.In addition, according to clock signal generation module 24, owing to control signal being applied to delayed data by the 2nd summitor 404, thus by the jump irrelevant with the jump of the waveform putting on front and back test period, the clock signal of this test period can be applied to.That is, according to clock signal generation module 24, instantaneous jump can be applied to clock signal.Whereby, according to jump control module 26, the jump produced by the reason determined that such as sine wave jumps can be applied to test signal.
Further, according to clock signal generation module 24, owing to control signal being applied to accumulated delay controlling value by the 3rd summitor 410, thus the jump through cumulative addition can be applied to clock signal.Whereby, according to jump control module 26, the jump of simulating the SSB noise produced near the centre frequency of oscillator signal can be applied to clock signal.Therefore, according to jump control module 26, the jump being major component can be applied to test signal with the phase noise of oscillatory circuit and PLL circuit etc.
Above content uses embodiment to describe the present invention; but protection scope of the present invention not limited by above-described embodiment; any person skilled in the art is clear; not departing from the purpose and scope of the invention; diversified change can be done improve; therefore, it changes or improves and is all included within protection scope of the present invention.
Claims (7)
1. a full-automatic IC electric signal measuring apparatus is the full-automatic IC electric signal measuring apparatus tested IC device, it is characterized in that described full-automatic IC electric signal measuring apparatus comprises:
Computer image genration module, produce test pattern, described test pattern specifies the test signal being supplied to above-mentioned IC device;
Clock signal generation module, produces the clock signal representing sequential test signal being supplied to above-mentioned IC device;
Filtration module, carries out filtering to described test pattern, exports and represents control signal corresponding with described test pattern;
Fluctuation processing module, makes described clock signal postpone according to described control signal, whereby jump is applied to described clock signal; And
Oscillogram, to be applied with the described clock signal of jump for benchmark, generates the test signal that oneself forms described test pattern.
2. full-automatic IC electric signal measuring apparatus according to claim 1, characterized by further comprising applying control module, its input is used to specify the applying control signal of whether jumping to described clock signal applying, when be designated do not apply jump time, described control signal is set to do not apply jump value.
3. full-automatic IC electric signal measuring apparatus according to claim 1, characterized by further comprising summation module, by the jump variety classes signal represented with correspond to test pattern, is added with described control signal.
4. full-automatic IC electric signal measuring apparatus according to claim 1, characterized by further comprising:
Probability flux module, exports the random skip signal representing random skip; And
Summation module, is added described random skip signal with described control signal,
Described probability flux module comprises:
Linear feedback shift register, comprises the shift register of specified sections, and the register of latter end produces pseudorandom signal in described shift register;
Summation module, exports additive value, and described additive value is the value being added by the bit value of multiple registers contained in described shift register and obtaining;
Ask differential mode block, export half value subtraction value, described half value subtraction value deducts the half value of multiple register number and the value that obtains from described additive value, and described multiple register is for storing the bit value be added by described summation module; And
Probability output module, exports the described random skip signal corresponding with described half value subtraction value.
5. full-automatic IC electric signal measuring apparatus according to claim 1, characterized by further comprising: signal output module, test signal is exported to described IC device;
Signal input module, inputs according to described test signal from the output signal that described IC device exports;
Computer image genration module, produces desired value image, the output signal that described desired value image specification exports from described IC device;
Clock signal generation module, produces the gating signal represented the sequential that described desired value image and described output signal compare;
Filtration module, carries out filtering to described desired value image, exports and represents and the corresponding control signal of described desired value image;
Fluctuation processing module, makes described gating signal postpone according to described control signal, with this, jump is applied to described gating signal; And
Comparison module, to be applied with the sequential of the described gating signal of jump, compares described output signal and described desired value image.
6. adopt a method of testing for the full-automatic IC electric signal measuring apparatus described in 1 to 5 any one claim, it is characterized in that: it is characterized in that described method of testing comprises:
Produce the stage of test pattern, described test pattern specifies the test signal being supplied to described IC device;
Produce the stage of clock signal, described clock signal represents sequential test signal being supplied to described IC device;
Filtering is carried out to described test pattern, and exports the stage representing control signal corresponding with described test pattern;
According to described control signal, described clock signal is postponed, will jump the stage being applied to described clock signal thus; And
To be applied with the described clock signal of jump for benchmark, generate the stage of the test signal forming described test pattern.
7. the method for testing of full-automatic IC electric signal measuring apparatus according to claim 6, is characterized in that comprising:
Test signal is exported to the stage of described IC device;
According to described test signal, input the stage of the output signal exported from described IC device;
Produce the stage of desired value image, the output signal that described desired value image specification exports from described IC device;
Produce the stage of gating signal, described gating signal represents the sequential compared described desired value image and described output signal;
Filtering is carried out to described desired value image, and exports the stage represented with the corresponding control signal of described desired value image;
According to described control signal, described gating signal is postponed, thus described gating signal is applied to the stage of jumping; And
In the sequential of described gating signal being applied with jump, to the stage that described output signal and described desired value image compare.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510453805.6A CN104965169A (en) | 2015-07-29 | 2015-07-29 | Full-automatic IC electric signal test device and test method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510453805.6A CN104965169A (en) | 2015-07-29 | 2015-07-29 | Full-automatic IC electric signal test device and test method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104965169A true CN104965169A (en) | 2015-10-07 |
Family
ID=54219212
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510453805.6A Pending CN104965169A (en) | 2015-07-29 | 2015-07-29 | Full-automatic IC electric signal test device and test method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104965169A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109143045A (en) * | 2018-10-24 | 2019-01-04 | 武汉精鸿电子技术有限公司 | A kind of timing and waveform generating and method |
| CN113311314A (en) * | 2021-05-27 | 2021-08-27 | 杭州万高科技股份有限公司 | IC time sequence verification method and device |
| TWI771122B (en) * | 2021-03-17 | 2022-07-11 | 大陸商勝達克半導體科技（上海）有限公司 | Method of amending and acquiring waveform data of arbitrary waveform generator during dynamic adjustment of chip testing equipment |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1921315A (en) * | 2006-09-12 | 2007-02-28 | 威盛电子股份有限公司 | Time-vein signal regulating method and device |
| CN101512362A (en) * | 2006-07-10 | 2009-08-19 | 阿斯特瑞昂公司 | Digital waveform generation and measurement in automated test equipment |
| CN101657731A (en) * | 2007-04-24 | 2010-02-24 | 爱德万测试株式会社 | Testing apparatus and testing method |
| CN102185729A (en) * | 2009-12-24 | 2011-09-14 | 爱德万测试株式会社 | Test apparatus, test method and test system |
| CN102204095A (en) * | 2008-12-26 | 2011-09-28 | 株式会社爱德万测试 | Timing generator, test device, and test rate control method |
-
2015
- 2015-07-29 CN CN201510453805.6A patent/CN104965169A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101512362A (en) * | 2006-07-10 | 2009-08-19 | 阿斯特瑞昂公司 | Digital waveform generation and measurement in automated test equipment |
| CN1921315A (en) * | 2006-09-12 | 2007-02-28 | 威盛电子股份有限公司 | Time-vein signal regulating method and device |
| CN101657731A (en) * | 2007-04-24 | 2010-02-24 | 爱德万测试株式会社 | Testing apparatus and testing method |
| CN102204095A (en) * | 2008-12-26 | 2011-09-28 | 株式会社爱德万测试 | Timing generator, test device, and test rate control method |
| CN102185729A (en) * | 2009-12-24 | 2011-09-14 | 爱德万测试株式会社 | Test apparatus, test method and test system |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109143045A (en) * | 2018-10-24 | 2019-01-04 | 武汉精鸿电子技术有限公司 | A kind of timing and waveform generating and method |
| CN109143045B (en) * | 2018-10-24 | 2024-02-13 | 武汉精鸿电子技术有限公司 | Time sequence and waveform generation device and method |
| TWI771122B (en) * | 2021-03-17 | 2022-07-11 | 大陸商勝達克半導體科技（上海）有限公司 | Method of amending and acquiring waveform data of arbitrary waveform generator during dynamic adjustment of chip testing equipment |
| CN113311314A (en) * | 2021-05-27 | 2021-08-27 | 杭州万高科技股份有限公司 | IC time sequence verification method and device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101657731B (en) | Testing apparatus and testing method | |
| CN105144587A (en) | Efficient time-interleaved analog-to-digital converter | |
| US6998893B2 (en) | Circuit and method for inducing jitter to a signal | |
| US9166843B2 (en) | Digital pulse width generator and method for generating digital pulse width | |
| CN104965169A (en) | Full-automatic IC electric signal test device and test method | |
| KR101254439B1 (en) | Timing generator, test device, and test rate control method | |
| US8427195B1 (en) | Digital signal generator and automatic test equipment having the same | |
| JP2004125574A (en) | Testing apparatus and testing process | |
| JP4951378B2 (en) | Waveform generator and test equipment | |
| JP5243287B2 (en) | Jitter injection circuit, pattern generator, test apparatus, and electronic device | |
| CN107271891B (en) | A kind of device that train pulse rising edge is jittered | |
| JPWO2007037314A1 (en) | Signal measuring device | |
| CN107276568B (en) | A kind of device that train pulse failing edge is jittered | |
| US20100201409A1 (en) | Frequency Divider Circuit | |
| US7539592B2 (en) | Test apparatus and electronic device | |
| US9588860B2 (en) | Systems and methods for random number generation using a fractional rate clock | |
| CN105871358B (en) | Spread spectrum clock pulse generation methods and device | |
| CN109143045B (en) | Time sequence and waveform generation device and method | |
| JP5854003B2 (en) | Digitally controlled oscillator and variable frequency oscillator | |
| CN102124357A (en) | Test device and testing method | |
| US20060155898A1 (en) | Data generator for generating data of arbitrary length | |
| JP5243340B2 (en) | Test apparatus and test method | |
| JP2013072797A (en) | Semiconductor test circuit | |
| Ko et al. | Spread spectrum clock generator for reducing electro-magnetic interference (EMI) noise in LCD driver IC | |
| CN100541612C (en) | Generation writes the method and the circuit of pulse and the device that uses this method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20151007 |
|
| WD01 | Invention patent application deemed withdrawn after publication |