CN105871358B - Method and apparatus for generating spread spectrum clock - Google Patents

Method and apparatus for generating spread spectrum clock Download PDF

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CN105871358B
CN105871358B CN201510035651.9A CN201510035651A CN105871358B CN 105871358 B CN105871358 B CN 105871358B CN 201510035651 A CN201510035651 A CN 201510035651A CN 105871358 B CN105871358 B CN 105871358B
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spread spectrum
clock
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clock signal
spectrum
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CN105871358A (en
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曾顺得
翁启舜
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Realtek Semiconductor Corp
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Abstract

本发明揭示一种展频时脉产生方法及装置,该装置包括:一多相位时脉产生单元,产生一预订数量的多个第一时脉信号,其中,该多个第一时脉信号具有实质上相同的周期及彼此不同的相位;一展频时脉控制单元,依据一第一预定展频频谱,产生一指令信号;以及一时脉选择单元,接收该指令信号,并依据该指令信号,自该多个第一时脉信号中动态地选择并输出其中一个,以产生一第一展频时脉信号;其中,该第一展频时脉信号的信号频谱对应于该第一预定展频频谱。

The present invention discloses a spread spectrum clock generation method and device, the device comprising: a multi-phase clock generation unit, generating a predetermined number of multiple first clock signals, wherein the multiple first clock signals have substantially the same period and different phases from each other; a spread spectrum clock control unit, generating a command signal according to a first predetermined spread spectrum spectrum; and a clock selection unit, receiving the command signal, and dynamically selecting and outputting one of the multiple first clock signals according to the command signal to generate a first spread spectrum clock signal; wherein the signal spectrum of the first spread spectrum clock signal corresponds to the first predetermined spread spectrum spectrum.

Description

展频时脉产生方法及装置Spread spectrum clock generation method and device

技术领域technical field

本发明关于一种展频时脉产生方法及装置,特别是一种使用展频时脉的电子装置。The invention relates to a method and device for generating a spread spectrum clock, in particular to an electronic device using a spread spectrum clock.

背景技术Background technique

时脉电路是许多电子装置中最重要的元件之一,对系统整体效能的影响相当深远。然而,时脉信号在其所在的频率上会产生很强的电磁干扰(ElectromagneticInterference,简称EMI)。业界通常会定义一个门槛值,希望时脉信号的电磁干扰都能低于这个门槛值。现今技术常使用展频时脉(spread-spectrum clock),动态地改变时脉信号的频率,使时脉信号的能量分散至不同的频率上,借以满足电磁干扰的要求。The clock circuit is one of the most important components in many electronic devices, and it has a profound impact on the overall performance of the system. However, the frequency of the clock signal will generate strong electromagnetic interference (Electromagnetic Interference, EMI for short). The industry usually defines a threshold, and it is hoped that the electromagnetic interference of the clock signal can be lower than this threshold. The current technology often uses a spread-spectrum clock to dynamically change the frequency of the clock signal, so that the energy of the clock signal is dispersed to different frequencies, so as to meet the requirements of electromagnetic interference.

然而,熟知技术是利用具有回路滤波器(loop filter)的锁相回路(phase lockedloop)所组成,其为封闭式回路(closed loop)的电路结构;当通过一展频控制器(spreadspectrum controller)来控制该锁相回路对时脉信号进行展频处理时,难以得知每一个展频命令何时开始对该锁相回路发生作用,亦无法确保该展频命令能使该锁相回路产生多少的展频时脉的相位偏移,但这些信息对于固定产出量(constant throughput)的电路系统却非常重要。因此,有必要发展新的展频时脉产生技术以对治及改善之。However, the well-known technology utilizes a phase locked loop (phase locked loop) with a loop filter (loop filter), which is a closed loop (closed loop) circuit structure; when a spread spectrum controller (spreadspectrum controller) is used to When controlling the phase-locked loop to perform spread-spectrum processing on the clock signal, it is difficult to know when each spread-spectrum command starts to act on the phase-locked loop, and it is impossible to ensure how much the spread-spectrum command can cause the phase-locked loop to generate. The phase shift of the spread spectrum clock, but this information is very important for the circuit system with constant throughput. Therefore, it is necessary to develop a new spread-spectrum clock generation technology to cure and improve it.

发明内容Contents of the invention

为达成此目的,根据本发明的一方面,一实施例提供一种展频时脉产生方法,其包含下列步骤:提供一预订数量(M)的多个第一时脉信号,其中,该多个第一时脉信号具有实质上相同的周期(T)及彼此不同的相位;依据一第一预定展频频谱,产生一指令信号;以及依据该指令信号,自该多个第一时脉信号中动态地选择并输出其中一个,以产生一第一展频时脉信号;其中,该第一展频时脉信号的信号频谱对应于该第一预定展频频谱。To achieve this purpose, according to one aspect of the present invention, an embodiment provides a method for generating a spread spectrum clock, which includes the following steps: providing a predetermined number (M) of multiple first clock signals, wherein the multiple A first clock signal has substantially the same period (T) and phases different from each other; according to a first predetermined spread spectrum, an instruction signal is generated; and according to the instruction signal, from the plurality of first clock signals One of them is dynamically selected and output to generate a first spread spectrum clock signal; wherein, the signal spectrum of the first spread spectrum clock signal corresponds to the first predetermined spread spectrum.

根据本发明的另一方面,另一实施例提供一种展频时脉产生装置,其包括:一多相位时脉产生单元,产生一预订数量的多个第一时脉信号,其中,该多个第一时脉信号具有实质上相同的周期及彼此不同的相位;一展频时脉控制单元,依据一第一预定展频频谱,产生一指令信号;以及一时脉选择单元,接收该指令信号,并依据该指令信号,自该多个第一时脉信号中动态地选择并输出其中一个,以产生一第一展频时脉信号;其中,该第一展频时脉信号的信号频谱对应于该第一预定展频频谱。According to another aspect of the present invention, another embodiment provides a spread spectrum clock generating device, which includes: a multi-phase clock generating unit for generating a predetermined number of multiple first clock signals, wherein the multiple A first clock signal has substantially the same period and different phases from each other; a spread spectrum clock control unit generates a command signal according to a first predetermined spread spectrum; and a clock selection unit receives the command signal , and according to the command signal, dynamically select and output one of the multiple first clock signals to generate a first spread spectrum clock signal; wherein, the signal spectrum of the first spread spectrum clock signal corresponds to on the first predetermined spread spectrum.

根据本发明的另一方面,另一实施例提供一种使用展频时脉的装置,其包括:一多相位时脉产生单元,产生一预订数量(M)的多个第一时脉信号,其中,该多个第一时脉信号具有实质上相同的周期(T)及彼此不同的相位;一展频时脉控制单元,依据一第一预定展频频谱及一第二预定展频频谱,分别产生一第一指令信号及一第二指令信号;一第一时脉选择单元,接收该第一指令信号,并依据该第一指令信号,自该多个第一时脉信号中动态地选择并输出其中一个,以产生一第一展频时脉信号;以及一第二时脉选择单元,接收该第二指令信号,并依据该第二指令信号,自该多个第一时脉信号中动态地选择并输出其中一个,以产生一第二展频时脉信号;其中,该第一展频时脉信号的信号频谱对应于该第一预定展频频谱,该第二展频时脉信号的信号频谱对应于该第二预定展频频谱。According to another aspect of the present invention, another embodiment provides a device using a spread spectrum clock, which includes: a multi-phase clock generating unit that generates a predetermined number (M) of a plurality of first clock signals, Wherein, the plurality of first clock signals have substantially the same period (T) and phases different from each other; a spread spectrum clock control unit, according to a first predetermined spread spectrum and a second predetermined spread spectrum, respectively generate a first command signal and a second command signal; a first clock selection unit receives the first command signal, and dynamically selects from the plurality of first clock signals according to the first command signal And output one of them to generate a first spread spectrum clock signal; and a second clock selection unit, which receives the second command signal and selects from the multiple first clock signals according to the second command signal Dynamically select and output one of them to generate a second spread spectrum clock signal; wherein, the signal spectrum of the first spread spectrum clock signal corresponds to the first predetermined spread spectrum, and the second spread spectrum clock signal The signal spectrum of corresponds to the second predetermined spread spectrum.

在一实施例中,当该多个第一时脉信号依序自1至M编号为n时,编号n与编号1的第一时脉信号之间的相位差为(n-1)×T/M。In one embodiment, when the plurality of first clock signals are numbered from 1 to M sequentially as n, the phase difference between the first clock signal numbered n and number 1 is (n-1)×T /M.

在一实施例中,该第一时脉选择单元随机自该多个第一时脉信号选出其中一个,或依序选出编号自1至M递增的第一时脉信号再依序选出编号自M至1递减的第一时脉信号。In one embodiment, the first clock selection unit randomly selects one of the plurality of first clock signals, or sequentially selects the first clock signals whose numbers are incremented from 1 to M and then sequentially selects The first clock signals are numbered in descending order from M to 1.

在一实施例中,该第二时脉选择单元随机自该多个第一时脉信号选出其中一个,或依序选出编号自1至M递增的第一时脉信号再依序选出编号自M至1递减的第一时脉信号。In one embodiment, the second clock selection unit randomly selects one of the plurality of first clock signals, or sequentially selects the first clock signals whose numbers are incremented from 1 to M and then sequentially selects The first clock signals are numbered in descending order from M to 1.

在一实施例中,该装置进一步包括一先进先出缓冲器,其中,该第一展频时脉信号与该第二展频时脉信号分别作为该先进先出缓冲器的写入时脉与读出时脉。In one embodiment, the device further includes a first-in-first-out buffer, wherein the first spread-spectrum clock signal and the second spread-spectrum clock signal serve as the write clock and the first-in-first-out buffer respectively. Read the clock.

在一实施例中,该装置进一步包含一相位差计算单元,其累计该第一展频时脉信号与依据该第一指令信号而被选择并输出的该第一时脉信号之间的相位差、以及该第二展频时脉信号与依据该第二指令信号而被选择并输出的该第一时脉信号之间的相位差。In one embodiment, the device further includes a phase difference calculation unit, which accumulates the phase difference between the first spread spectrum clock signal and the first clock signal selected and output according to the first command signal , and the phase difference between the second spread spectrum clock signal and the first clock signal selected and output according to the second command signal.

附图说明Description of drawings

图1为本发明实施例的展频时脉产生方法的流程示意图。FIG. 1 is a schematic flowchart of a method for generating a spread spectrum clock according to an embodiment of the present invention.

图2为本发明第一实施例的展频时脉产生装置的方块示意图。FIG. 2 is a schematic block diagram of a spread spectrum clock generating device according to a first embodiment of the present invention.

图3为本实施例的时脉输出单元的方块示意图。FIG. 3 is a schematic block diagram of the clock output unit of this embodiment.

图4为本发明第二实施例的使用两个展频时脉的装置的方块示意图。FIG. 4 is a schematic block diagram of an apparatus using two spread spectrum clocks according to a second embodiment of the present invention.

其中,附图标记说明如下:Wherein, the reference signs are explained as follows:

200展频时脉产生装置200 spread spectrum clock generator

210多相位时脉产生单元210 multi-phase clock generation unit

220展频时脉控制单元220 spread spectrum clock control unit

230时脉选择单元230 clock selection unit

300装置300 devices

310多相位时脉产生单元310 multi-phase clock generation unit

320展频时脉控制单元320 spread spectrum clock control unit

330第一时脉选择单元330 first clock selection unit

350第二时脉选择单元350 second clock selection unit

360先进先出缓冲器360 FIFO buffer

CK1n第一时脉信号CK1 n first clock signal

CK3第一展频时脉信号CK3 first spread spectrum clock signal

具体实施方式Detailed ways

为使贵审查委员能对本发明的特征、目的及功能有更进一步的认知与了解,现配合附图详细说明本发明的实施例如后。在所有的说明书及图示中,将采用相同的元件编号以指定相同或类似的元件。在各个实施例的说明中,所谓的“第一”、“第二”、及“第三”是用以描述不同的元素,这些元素并不因为此类表述而受到限制。为了说明上的便利和明确,附图中各元素的尺寸是以夸张或省略或概略的方式表示,且各元素的尺寸并未完全为其实际的尺寸。In order to enable your examining committee members to have a further understanding and understanding of the characteristics, purpose and functions of the present invention, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Throughout the description and drawings, the same element number will be used to designate the same or similar elements. In descriptions of various embodiments, so-called "first", "second", and "third" are used to describe different elements, and these elements are not limited by such expressions. For the convenience and clarity of illustration, the size of each element in the drawings is exaggerated or omitted or shown in a rough manner, and the size of each element is not entirely its actual size.

图1为本发明实施例的展频时脉产生方法100的流程示意图,其包含下列步骤:(步骤110)提供多个第一时脉信号,其中,该多个第一时脉信号具有实质上相同的周期及彼此不同的相位;(步骤120)依据一第一预定展频频谱,产生一指令信号;以及(步骤130)依据该指令信号,自该多个第一时脉信号中动态地选择并输出其中一个,以产生一第一展频时脉信号;其中,该第一展频时脉信号的信号频谱对应于该第一预定展频频谱。1 is a schematic flow chart of a spread spectrum clock generation method 100 according to an embodiment of the present invention, which includes the following steps: (step 110) providing a plurality of first clock signals, wherein the plurality of first clock signals have substantially The same cycle and different phases from each other; (step 120) generating a command signal according to a first predetermined spread spectrum; and (step 130) dynamically selecting from the plurality of first clock signals according to the command signal And output one of them to generate a first spread spectrum clock signal; wherein, the signal spectrum of the first spread spectrum clock signal corresponds to the first predetermined spread spectrum.

实际上,所述预定展频频谱依据应用的产品不同而有所不同,且预定展频频谱的相关设定值或程序码写入展频时脉控制单元220中,展频时脉控制单元220可以由软件、固件或是硬件所实现。In fact, the predetermined spread spectrum varies according to the applied products, and the relevant setting values or program codes of the predetermined spread spectrum are written into the spread spectrum clock control unit 220, and the spread spectrum clock control unit 220 It can be implemented by software, firmware or hardware.

举例来说,电路设计者可以将为一中心频率为100KHz,展频范围为5%的展频频谱相关的设定值或程序码写进一展频时脉控制单元220中,再通过指令信号动态地选择第一时脉信号(第一时脉信号例如为一100KHz的时脉信号),来产生第一展频时脉信号,其频率范围为95KHz-105KHz,与展频时脉控制单元220中的预定展频频谱相对应。For example, the circuit designer can write the set values or program codes related to the spread spectrum with a center frequency of 100KHz and a spread spectrum range of 5% into a spread spectrum clock control unit 220, and then pass the instruction signal Dynamically select the first clock signal (the first clock signal is, for example, a 100KHz clock signal) to generate the first spread-spectrum clock signal, the frequency range of which is 95KHz-105KHz, and the spread-spectrum clock control unit 220 Corresponds to the predetermined spread spectrum in .

首先,本方法100通过该指令信号,而在相同频率但不同相位的多个时脉信号(如上所述的第一时脉信号)中,选出欲进行展频处理的其中一个,并对它进行展频处理(而得到如上所述的第一展频时脉信号);接着,由于本方法100在该指令信号被产生之时,就已可得知该时脉信号在展频处理前后所造成的相位偏移量(phase offset),进而借以得知该指令信号的施加对该时脉信号所产生的展频效果;因此,我们可依据上述的相位偏移量,而精确地设计出一串列的指令信号,故本方法100特别适用于固定产出量(constantthroughput)的电路系统。First, the method 100 uses the command signal to select one of the multiple clock signals (the above-mentioned first clock signal) with the same frequency but different phases to be subjected to spread spectrum processing, and perform Perform spectrum spread processing (to obtain the first spread spectrum clock signal as described above); then, since the method 100 is generated when the command signal is generated, it can already be known that the clock signal is changed before and after spread spectrum processing The resulting phase offset (phase offset) can be used to know the spread spectrum effect of the clock signal when the command signal is applied; therefore, we can accurately design a The command signals are serialized, so the method 100 is especially suitable for circuit systems with constant throughput.

根据上述的方法100,以下提出两个个实施例,通过电路设计来对本发明加以实施。图2为本发明第一实施例的展频时脉产生装置200的方块示意图,该展频时脉产生装置200包括:一多相位时脉产生单元210、一展频时脉控制单元220、以及一时脉选择单元230。该多相位时脉产生单元210可产生多个第一时脉信号CK1n,提供给该时脉选择单元230作为候选时脉,由该时脉选择单元230依据一第一预定展频频谱,也就是该展频时脉产生装置200所欲产生的展频时脉态样,而自该多个候选时脉之中选出适当的时脉信号以进行展频处理;其中,该多个第一时脉信号CK1n具有实质上相同的周期及彼此不同的相位。According to the above-mentioned method 100, two embodiments are proposed below, and the present invention is implemented through circuit design. 2 is a schematic block diagram of a spread spectrum clock generating device 200 according to the first embodiment of the present invention. The spread spectrum clock generating device 200 includes: a multiphase clock generating unit 210, a spread spectrum clock control unit 220, and A clock selection unit 230 . The multi-phase clock generation unit 210 can generate a plurality of first clock signals CK1 n and provide them to the clock selection unit 230 as candidate clocks, and the clock selection unit 230 can also generate It is the pattern of the spread spectrum clock that the spread spectrum clock generating device 200 intends to generate, and an appropriate clock signal is selected from the plurality of candidate clocks for spread spectrum processing; wherein, the plurality of first The clock signals CK1 n have substantially the same period and different phases from each other.

在以下的说明书中,T将用以代表该多个第一时脉信号CK1n的周期,M用以代表该多个第一时脉信号CK1n的数量,n用以代表该多个第一时脉信号CK1n的编号;也就是说,该多个第一时脉信号CK1n可编号为自CK11至CK1M。在本实施例中,当该多个第一时脉信号依序编号为CK11~CK1M时,该多个第一时脉信号CK1n与CK11之间的相位差为(n-1)×T/M,也就是相邻的第一时脉信号的相位差为T/M。针对数量M=4的例子,该多个第一时脉信号的相邻两个(例如,CK11与CK12、CK12与CK13、CK13与CK14)之间的相位差皆为T/4,如图3所示。In the following description, T will be used to represent the period of the multiple first clock signals CK1 n , M will be used to represent the number of the multiple first clock signals CK1 n , and n will be used to represent the multiple first clock signals CK1 n. Numbering of the clock signals CK1 n ; that is, the plurality of first clock signals CK1 n may be numbered from CK1 1 to CK1 M . In this embodiment, when the multiple first clock signals are sequentially numbered as CK1 1 to CK1 M , the phase difference between the multiple first clock signals CK1 n and CK1 1 is (n-1) ×T/M, that is, the phase difference between adjacent first clock signals is T/M. For the example with the quantity M=4, the phase difference between two adjacent first clock signals (for example, CK1 1 and CK1 2 , CK1 2 and CK1 3 , CK1 3 and CK1 4 ) is T /4, as shown in Figure 3.

该展频时脉控制单元220可依据该第一预定展频频谱,产生一指令信号给该时脉选择单元230,用以控制或指示该时脉选择单元230自该多个第一时脉之中选出适当的一个,以进行展频处理。该时脉选择单元230在接收该指令信号之后,会自该多个第一时脉信号之中动态地选择并输出其中一个(换言之,时脉选择单元230轮流地输出该些不同相位的第一时脉信号),并依据该指令信号对被选出的该第一时脉信号进行展频处理,以产生一第一展频时脉信号CK3(即,展频处理后的时脉信号)。The spread-spectrum clock control unit 220 can generate an instruction signal to the clock selection unit 230 according to the first predetermined spread-spectrum spectrum, to control or instruct the clock selection unit 230 to select from among the plurality of first clocks. Select the appropriate one for spread spectrum processing. After receiving the instruction signal, the clock selection unit 230 will dynamically select and output one of the multiple first clock signals (in other words, the clock selection unit 230 outputs the first clock signals of different phases in turn. clock signal), and perform spread spectrum processing on the selected first clock signal according to the instruction signal, so as to generate a first spread spectrum clock signal CK3 (ie, the clock signal after spread spectrum processing).

此外,本发明实施例的展频时脉产生装置200可进一步包含一相位差计算单元(未图示),其可累计该第一展频时脉信号与被选出的该第一时脉信号之间的相位差。由于该多相位时脉产生单元210所产生的该多个第一时脉信号CK1n的相位为已知的信息,因此当该指令信号被发出之时,该展频时脉控制单元220就已可得知或计算出被选出的该第一时脉信号与该第一展频时脉信号CK3之间的相位差(也就是,被选出的第一时脉信号在展频处理前后的相位差异量),而该展频时脉控制单元220又据以产生下一回合的该指令信号,用以控制或指示该时脉选择单元230。此外,倘若该指令信号包含一序列的指令,该展频时脉控制单元220亦可对被选出的该第一时脉信号与该第一展频时脉信号CK3在不同时间的相位差进行累计,其结果亦作为该展频时脉控制单元220产生下一回合的指令信号的依据,以达到该展频时脉产生装置200对于最大相位差累积量的要求。In addition, the spread spectrum clock generator 200 of the embodiment of the present invention may further include a phase difference calculation unit (not shown), which can accumulate the first spread spectrum clock signal and the selected first clock signal the phase difference between. Since the phases of the plurality of first clock signals CK1 n generated by the multi-phase clock generating unit 210 are known information, when the command signal is sent out, the spread spectrum clock control unit 220 has already The phase difference between the selected first clock signal and the first spread spectrum clock signal CK3 can be known or calculated (that is, the phase difference of the selected first clock signal before and after spread spectrum processing phase difference), and the spread spectrum clock control unit 220 generates the instruction signal for the next round according to it to control or instruct the clock selection unit 230 . In addition, if the instruction signal includes a sequence of instructions, the spread spectrum clock control unit 220 can also perform phase differences between the selected first clock signal and the first spread spectrum clock signal CK3 at different times. Accumulated, the result is also used as the basis for the spread spectrum clock control unit 220 to generate the command signal for the next round, so as to meet the requirement of the spread spectrum clock generator 200 for the maximum phase difference accumulation.

图3为本实施例的时脉输出单元230的方块示意图,其是针对该多个第一时脉信号CK1n的数量M=4作为例子。在该时脉选择单元230的左方为该多相位时脉产生单元210所提供的该多个第一时脉信号CK11、CK12、CK13、CK14,其相邻的第一时脉信号(CK11与CK12、CK12与CK13、CK13与CK14)之间的相位差皆为T/4。在一实施例中,该时脉选择单元230可自该多个第一时脉信号CK11、CK12、CK13、CK14中随机选出其中的一个,以进行展频处理。在另一实施例中,该时脉选择单元230可依序选出编号自1至M递增的第一时脉信号,再依序选出编号自M至1递减的第一时脉信号;也就是如图3所示,该时脉选择单元230右方的该多个第一时脉信号依序以CK11、CK12、CK13、CK14、CK14、CK13、CK12、CK11被选出以进行展频处理,但本发明对其存续期间长短并不加以限制,各个第一时脉信号CK11、CK12、CK13、CK14作用的期间长度可以彼此不同或相同。该时脉选择单元230包含高速的多工选择器(multiplexer)的功能,可对于该多个第一时脉信号CK11、CK12、CK13、CK14进行适当的选择与切换。FIG. 3 is a schematic block diagram of the clock output unit 230 of this embodiment, which is taken as an example for the number M=4 of the plurality of first clock signals CK1 n . On the left of the clock selection unit 230 are the multiple first clock signals CK1 1 , CK1 2 , CK1 3 , CK1 4 provided by the multi-phase clock generation unit 210 , and the adjacent first clock signals The phase differences between the signals (CK1 1 and CK1 2 , CK1 2 and CK1 3 , CK1 3 and CK1 4 ) are all T/4. In one embodiment, the clock selection unit 230 can randomly select one of the plurality of first clock signals CK1 1 , CK1 2 , CK1 3 , CK1 4 for spread spectrum processing. In another embodiment, the clock selection unit 230 may sequentially select the first clock signals whose numbers are increasing from 1 to M, and then sequentially select the first clock signals whose numbers are decreasing from M to 1; As shown in FIG. 3 , the plurality of first clock signals on the right side of the clock selection unit 230 are sequentially represented by CK1 1 , CK1 2 , CK1 3 , CK1 4 , CK1 4 , CK1 3 , CK1 2 , CK1 1 are selected for spread-spectrum processing, but the present invention does not limit its duration, and the durations of the first clock signals CK1 1 , CK1 2 , CK1 3 , and CK1 4 can be different or the same. The clock selection unit 230 includes the function of a high-speed multiplexer, which can properly select and switch the plurality of first clock signals CK1 1 , CK1 2 , CK1 3 , and CK1 4 .

通过本发明的展频时脉产生方法100及装置200,对于一个使用展频时脉的电子装置而言,倘若它需要两个以上相互独立的展频时脉,则本发明只需要提供与展频时脉数量相同的时脉输出单元,而不需要如熟知技术那样还需要与展频时脉数量相同的多相位时脉产生单元,此亦可说为本发明技术的成本优势。举例来说,对于固定产出量(constantthroughput)的电路系统,其传送端与接收端(或是读取端与写入端)所约定用以收发数据的时脉可能会些许的频率差异,或是此两时脉虽然频率相同但相位却不同,此系统的介面区域通常需要一个先进先出缓冲器(first-in first-out buffer,简称FIFO)来调节或弹性控制传送端与接收端(或是读取端与写入端)之间的数据流量。而通过本发明,传送端与接收端(或是读取端与写入端)的时脉信号可通过两组独立的时脉输出单元,搭配独立的展频时脉控制指令序列即可达成;而因两时脉之间的相位差异是可被事先预估的,故先进先出缓冲器的深度(depth)就可以在电路设计阶段先决定好,而达成固定产出量的系统操作方式,且不会导致此两时脉之间相位差异不断累积而终致缓冲器满溢(overflow)。Through the spread spectrum clock generation method 100 and device 200 of the present invention, for an electronic device that uses a spread spectrum clock, if it needs more than two mutually independent spread spectrum clocks, the present invention only needs to provide and expand The clock output unit with the same number of frequency clocks does not need the multi-phase clock generation unit with the same number of spread spectrum clocks as the known technology, which can also be said to be the cost advantage of the technology of the present invention. For example, for a constant throughput circuit system, there may be a slight difference in the frequency of the clocks agreed between the transmitting end and the receiving end (or the reading end and the writing end) for sending and receiving data, or Although the frequency of the two clocks is the same, the phases are different. The interface area of this system usually requires a first-in first-out buffer (FIFO for short) to adjust or flexibly control the transmitting end and the receiving end (or is the data flow between the read end and the write end). Through the present invention, the clock signals of the transmitting end and the receiving end (or the reading end and the writing end) can be achieved through two sets of independent clock output units and independent spread spectrum clock control command sequences; Since the phase difference between the two clocks can be estimated in advance, the depth of the FIFO buffer can be determined in the circuit design stage to achieve a fixed output system operation mode. And it will not cause the phase difference between the two clocks to continuously accumulate and eventually cause the buffer to overflow.

图4为本发明第二实施例的使用两个展频时脉的装置300的方块示意图,该装置300包括:一多相位时脉产生单元310、一展频时脉控制单元320、一第一时脉选择单元330、一第二时脉选择单元350、以及一先进先出缓冲器360。该多相位时脉产生单元310相当于第一实施例的多相位时脉产生单元210,用以产生多个第一时脉信号CK1n给该第一时脉选择单元330与该第二时脉选择单元350作为候选时脉,由该第一时脉选择单元330与该第二时脉选择单元350依据该装置300所需的展频时脉态样的一第一预定展频频谱与一第二预定展频频谱,而自该多个候选时脉之中选出适当的时脉以进行展频处理;其中,该多个第一时脉信号CK1n具有相同的周期及彼此不同的相位。在本实施例中,该多个第一时脉信号CK1n依序为CK11~CK1M,该多个第一时脉信号CK1n与CK11之间的相位差为(n-1)×T/M,也就是相邻的第一时脉信号的相位差为T/M。4 is a schematic block diagram of a device 300 using two spread spectrum clocks according to a second embodiment of the present invention. The device 300 includes: a multi-phase clock generation unit 310, a spread spectrum clock control unit 320, a first clock The clock selection unit 330 , a second clock selection unit 350 , and a FIFO buffer 360 . The multi-phase clock generation unit 310 is equivalent to the multi-phase clock generation unit 210 of the first embodiment, and is used to generate a plurality of first clock signals CK1 n to the first clock selection unit 330 and the second clock The selection unit 350 is used as a candidate clock, and the first clock selection unit 330 and the second clock selection unit 350 are based on a first predetermined spread spectrum and a first spread spectrum of the spread spectrum clock pattern required by the device 300 2. Predetermining a spread spectrum, and selecting an appropriate clock from the plurality of candidate clocks for spread spectrum processing; wherein, the plurality of first clock signals CK1 n have the same period and different phases from each other. In this embodiment, the plurality of first clock signals CK1 n are sequentially CK1 1 to CK1 M , and the phase difference between the plurality of first clock signals CK1 n and CK1 1 is (n-1)× T/M, that is, the phase difference between adjacent first clock signals is T/M.

该展频时脉控制单元320相当于第一实施例的展频时脉控制单元220,可依据该装置300所需的一第一展频时脉的预定频谱,而产生一第一指令信号,并依据该装置300所欲使用的一第二展频时脉的预定频谱,而产生一第二指令信号,用以控制或指示该第一时脉选择单元330与该第二时脉选择单元350分别自该多个第一时脉CK1n之中选出适当的一个,以进行展频处理。该第一时脉输出单元330在接收该第一指令信号之后,会自该多个第一时脉信号CK1n之中选出其中一个(即,欲进行展频处理的时脉信号),并依据该第一指令信号对被选出的该第一时脉信号进行展频处理,以产生一第一展频时脉信号CK3(即,展频处理后的时脉信号)。该第二时脉选择单元350在接收该第二指令信号之后,亦会自该多个第一时脉信号CK1n之中选出其中一个(亦为欲进行展频处理的时脉信号),并依据该第二指令信号对被选出的该第一时脉信号进行展频处理,以产生一第二展频时脉信号CK5(亦为展频处理后的时脉信号)。The spread spectrum clock control unit 320 is equivalent to the spread spectrum clock control unit 220 of the first embodiment, and can generate a first instruction signal according to a predetermined frequency spectrum of a first spread spectrum clock required by the device 300, And according to the predetermined frequency spectrum of a second spread spectrum clock to be used by the device 300, a second command signal is generated to control or instruct the first clock selection unit 330 and the second clock selection unit 350 An appropriate one is selected from the plurality of first clocks CK1 n to perform spectrum spreading processing. After receiving the first instruction signal, the first clock output unit 330 will select one of the multiple first clock signals CK1 n (that is, the clock signal to be subjected to spread spectrum processing), and Spread spectrum processing is performed on the selected first clock signal according to the first instruction signal to generate a first spread spectrum clock signal CK3 (ie, the clock signal after spread spectrum processing). After receiving the second instruction signal, the second clock selection unit 350 will also select one of the multiple first clock signals CK1 n (also the clock signal to be subjected to spread spectrum processing), And according to the second command signal, spread spectrum processing is performed on the selected first clock signal to generate a second spread spectrum clock signal CK5 (also the clock signal after spread spectrum processing).

此外,本发明实施例的展频时脉产生装置200可进一步包含一相位差计算单元(未图示),其可累计该第一展频时脉信号与被选出的该第一时脉信号之间的相位差、以及该第二展频时脉信号与另一被选出的该第一时脉信号之间的相位差。由于该多相位时脉产生单元310所产生的该多个第一时脉信号CK1n的相位为已知的信息,因此当该指令信号被产生之时,该展频时脉控制单元220就已可得知或计算出被选出的该第一时脉信号与该第一展频时脉信号CK3之间的第一相位差,以及另一被选出的该第一时脉信号与该第二展频时脉信号CK5之间的第二相位差(也就是,被选出的第一时脉信号在展频处理前后的相位差异量),而该展频时脉控制单元320又可据以产生下一回合的该第一指令信号与该第二指令信号,用以分别控制或指示该第一时脉选择单元330与该第二时脉选择单元350。此外,倘若该指令信号包含一序列的指令,该展频时脉控制单元320亦可对不同时间的被选出的该第一时脉信号与该第一展频时脉信号CK3之第一相位差、以及另一被选出的该第一时脉信号与该第二展频时脉信号CK5的第二相位差进行累计,其结果亦作为该展频时脉控制单元320产生下一回合的第一指令信号与第二指令信号的依据,以达到该装置300对于最大相位差累积量的要求。In addition, the spread spectrum clock generator 200 of the embodiment of the present invention may further include a phase difference calculation unit (not shown), which can accumulate the first spread spectrum clock signal and the selected first clock signal The phase difference between, and the phase difference between the second spread spectrum clock signal and another selected first clock signal. Since the phases of the plurality of first clock signals CK1 n generated by the multi-phase clock generating unit 310 are known information, when the instruction signal is generated, the spread spectrum clock control unit 220 has already The first phase difference between the selected first clock signal and the first spread spectrum clock signal CK3, and the first phase difference between the other selected first clock signal and the first clock signal can be obtained or calculated. The second phase difference between the two spread-spectrum clock signals CK5 (that is, the phase difference of the selected first clock signal before and after the spread-spectrum processing), and the spread-spectrum clock control unit 320 can according to The first command signal and the second command signal for the next round are generated to control or instruct the first clock selection unit 330 and the second clock selection unit 350 respectively. In addition, if the instruction signal includes a sequence of instructions, the spread spectrum clock control unit 320 can also select the first phase of the first clock signal and the first spread spectrum clock signal CK3 at different times difference, and the second phase difference between the selected first clock signal and the second spread-spectrum clock signal CK5, and the result is also used as the next round of the spread-spectrum clock control unit 320 The basis of the first command signal and the second command signal is to meet the requirement of the device 300 for the maximum phase difference accumulation.

当该第一相位差与该第二相位差的差值累加达一预定值时,该展频时脉控制单元320将产生下一个第一指令信号及下一个第二指令信号,借以作出使该装置300达成最佳操作的因应措施。该第一时脉选择单元330与该第二时脉选择单元350可分别自该多个第一时脉信号CK1n中随机选出其中的一个,以进行展频处理。在另一实施例中,该第一时脉选择单元330与该第二时脉选择单元350亦可分别依序选出CK11~CK1M编号自1至M递增的第一时脉信号,再依序选出CK1M~CK11编号自M至1递减的第一时脉信号。When the difference between the first phase difference and the second phase difference reaches a predetermined value, the spread spectrum clock control unit 320 will generate the next first command signal and the next second command signal, so as to make the Apparatus 300 achieves optimal operational responses. The first clock selection unit 330 and the second clock selection unit 350 can respectively randomly select one of the plurality of first clock signals CK1 n for spread spectrum processing. In another embodiment, the first clock selection unit 330 and the second clock selection unit 350 can also sequentially select the first clock signals CK1 1 ~ CK1 M numbers increasing from 1 to M, and then The first clock signal whose number decreases from M to 1 is sequentially selected from CK1 M to CK1 1 .

如前所述,该先进先出缓冲器360是达成固定产出量的系统操作所需要的一个介面区域,用以调节其读取端与写入端之间的数据流量。在本实施例中,该第一展频时脉信号CK3与该第二展频时脉信号CK5分别作为该先进先出缓冲器360的写入时脉与读出时脉。由于该第一展频时脉信号CK3与该第二展频时脉信号CK5之间的相位差异是会被不断的累积,若无法精确得知两时脉信号之间累积相位差异并适当分别调整该第一展频时脉信号CK3与该第二展频时脉信号CK5,使累积相位差异不超过缓冲器深度,终将导致该先进先出缓冲器360的内部存储器空间发生不够用的满溢(overflow)状态。对不同时间的该第一展频时脉信号CK3与该第二展频时脉信号CK5的相位差异也会被累计,而当此相位差异累计量达到某一预定值时,该展频时脉控制单元320会针对此状况做出对该装置300能最佳操作的因应措施,例如,该展频时脉控制单元320产生下一组第一指令信号及第二指令信号,使得该第一时脉选择单元330与该第二时脉选择单元350不再继续产出相同的即时相位差异。As mentioned above, the FIFO buffer 360 is an interface area required to achieve fixed throughput system operation, and is used to regulate the data flow between the read end and the write end. In this embodiment, the first spread frequency clock signal CK3 and the second spread frequency clock signal CK5 serve as the write clock and read clock of the FIFO buffer 360 respectively. Since the phase difference between the first spread-spectrum clock signal CK3 and the second spread-spectrum clock signal CK5 will be continuously accumulated, if the cumulative phase difference between the two clock signals cannot be accurately known and adjusted accordingly The accumulated phase difference between the first spread spectrum clock signal CK3 and the second spread spectrum clock signal CK5 does not exceed the buffer depth, which will eventually cause insufficient overflow of the internal memory space of the FIFO buffer 360 (overflow) state. The phase difference between the first spread-spectrum clock signal CK3 and the second spread-spectrum clock signal CK5 at different times will also be accumulated, and when the cumulative amount of the phase difference reaches a predetermined value, the spread-spectrum clock signal The control unit 320 will take countermeasures for the optimal operation of the device 300 in response to this situation, for example, the spread spectrum clock control unit 320 generates the next set of first command signal and second command signal, so that the first time The clock selection unit 330 and the second clock selection unit 350 no longer continue to produce the same instantaneous phase difference.

以上所述,仅为本发明的较佳实施例,当不能以之限制本发明的范围。即凡依本发明权利要求所做的均等变化及修饰,仍将不失本发明的要义所在,亦不脱离本发明的精神和范围,故都应视为本发明的进一步实施状况。The above descriptions are only preferred embodiments of the present invention, and should not be used to limit the scope of the present invention. That is, all equivalent changes and modifications made according to the claims of the present invention will still not lose the gist of the present invention, nor depart from the spirit and scope of the present invention, so all should be regarded as further implementation status of the present invention.

Claims (15)

1. a kind of spread spectrum clock pulse generation methods, which is characterized in that including:
There is provided multiple first clock signals of a predetermined number M, wherein multiple first clock signal has substantially the same Cycle T and phase different from each other;
According to one first predetermined spread spectrum frequency spectrum, a command signal is generated;And
It according to the command signal, is dynamically selected from multiple first clock signal and exports one of them, to generate one the One spread spectrum clock signal;
Wherein, the signal spectrum of the first spread spectrum clock signal corresponds to the first predetermined spread spectrum frequency spectrum.
2. spread spectrum clock pulse generation methods as described in claim 1, which is characterized in that wherein, when multiple first clock signal When being sequentially n from 1 to M number, the phase difference of number n and the first clock signal of number 1 is (n-1) × T/M.
3. spread spectrum clock pulse generation methods as claimed in claim 2, which is characterized in that wherein, from multiple first clock signal In to be dynamically selected and export the step of one of them be to select one of them at random among multiple first clock signal.
4. spread spectrum clock pulse generation methods as claimed in claim 2, which is characterized in that wherein, from multiple first clock signal In to be dynamically selected and export the step of one of them be sequentially to select number from 1 to M among multiple first clock signal The first incremental clock signal, then sequentially select the first clock signal that number is successively decreased from M to 1.
5. a kind of spread spectrum clock pulse generation device comprising:
One leggy clock generating unit generates multiple first clock signals of a predetermined number M, wherein when multiple first Arteries and veins signal has substantially the same cycle T and phase different from each other;
One spread spectrum clock pulse control unit generates a command signal according to one first predetermined spread spectrum frequency spectrum;And
Timing selection unit receives the command signal, and according to the command signal, the dynamic from multiple first clock signal Ground selects and exports one of them, to generate one first spread spectrum clock signal;
Wherein, the signal spectrum of the first spread spectrum clock signal corresponds to the first predetermined spread spectrum frequency spectrum.
6. spread spectrum clock pulse generation device as claimed in claim 5, which is characterized in that wherein, when multiple first clock signal When being sequentially n from 1 to M number, the phase difference between number n and the first clock signal of number 1 is (n-1) × T/M.
7. spread spectrum clock pulse generation device as claimed in claim 6, which is characterized in that wherein, the clock pulse selecting unit is random certainly Multiple first clock signal selects one of them.
8. spread spectrum clock pulse generation device as claimed in claim 6, which is characterized in that wherein, which sequentially selects Go out number from 1 to M the first incremental clock signal, then sequentially selects the first clock signal that number is successively decreased from M to 1.
9. spread spectrum clock pulse generation device as claimed in claim 6 further includes a phase difference calculating unit, add up this Phase difference between one spread spectrum clock signal and first clock signal for being selected and being exported according to the command signal.
10. a kind of device using spread spectrum clock pulse comprising:
One leggy clock generating unit generates multiple first clock signals of a predetermined number M, wherein when multiple first Arteries and veins signal has substantially the same cycle T and phase different from each other;
One spread spectrum clock pulse control unit generates one respectively according to one first predetermined spread spectrum frequency spectrum and one second predetermined spread spectrum frequency spectrum First command signal and one second command signal;
One timing selection unit, receives first command signal, and according to first command signal, from multiple first when It is dynamically selected in arteries and veins signal and exports one of them, to generate one first spread spectrum clock signal;And
One second clock pulse selecting unit, receives second command signal, and according to second command signal, from multiple first when It is dynamically selected in arteries and veins signal and exports one of them, to generate one second spread spectrum clock signal;
Wherein, the signal spectrum of the first spread spectrum clock signal corresponds to the first predetermined spread spectrum frequency spectrum, the second spread spectrum clock pulse The signal spectrum of signal corresponds to the second predetermined spread spectrum frequency spectrum.
11. device as claimed in claim 10, which is characterized in that wherein, when multiple first clock signal is sequentially from 1 to M When number is n, the phase difference between number n and the first clock signal of number 1 is (n-1) × T/M.
12. device as claimed in claim 11, which is characterized in that wherein, the timing selection unit is at random from multiple First clock signal selects one of them, or sequentially selects number and sequentially select number again from 1 to M the first incremental clock signal The first clock signal to successively decrease from M to 1.
13. device as claimed in claim 11, which is characterized in that wherein, the second clock pulse selecting unit is at random from multiple First clock signal selects one of them, or sequentially selects number and sequentially select number again from 1 to M the first incremental clock signal The first clock signal to successively decrease from M to 1.
14. device as claimed in claim 10, which is characterized in that further comprise a first-in first-out buffer, wherein this Write-in clock pulse of the one spread spectrum clock signal as the first-in first-out buffer, the second spread spectrum clock signal is as the first in first out The reading clock pulse of buffer.
15. device as claimed in claim 10, which is characterized in that further include a phase difference calculating unit, adding up should Phase between first spread spectrum clock signal and first clock signal for being selected and being exported according to first command signal Difference and the second spread spectrum clock signal and first clock signal that is selected and exported according to second command signal it Between phase difference.
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CN109639259B (en) * 2018-12-05 2022-07-22 惠科股份有限公司 Method for spreading spectrum, chip, display panel and readable storage medium
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1434570A (en) * 2002-01-22 2003-08-06 瑞昱半导体股份有限公司 Spread spectrum PLL with adjustable spread spectrum range
CN1445949A (en) * 2002-03-18 2003-10-01 电子科技大学 New communication method of combined spread spectrum
TW200822566A (en) * 2006-11-07 2008-05-16 Via Tech Inc Methods and systems for generating a clock signal, and a phase locked loop
TWI376890B (en) * 2008-01-29 2012-11-11 Realtek Semiconductor Corp Method for generating a spread spectrum clock and apparatus thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1434570A (en) * 2002-01-22 2003-08-06 瑞昱半导体股份有限公司 Spread spectrum PLL with adjustable spread spectrum range
CN1445949A (en) * 2002-03-18 2003-10-01 电子科技大学 New communication method of combined spread spectrum
TW200822566A (en) * 2006-11-07 2008-05-16 Via Tech Inc Methods and systems for generating a clock signal, and a phase locked loop
TWI376890B (en) * 2008-01-29 2012-11-11 Realtek Semiconductor Corp Method for generating a spread spectrum clock and apparatus thereof

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