TWI376890B - Method for generating a spread spectrum clock and apparatus thereof - Google Patents

Method for generating a spread spectrum clock and apparatus thereof Download PDF

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Publication number
TWI376890B
TWI376890B TW98102495A TW98102495A TWI376890B TW I376890 B TWI376890 B TW I376890B TW 98102495 A TW98102495 A TW 98102495A TW 98102495 A TW98102495 A TW 98102495A TW I376890 B TWI376890 B TW I376890B
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period
clock
control signal
selection signal
signal
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TW98102495A
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Chinese (zh)
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TW200934149A (en
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Meng Han Hsieh
Chi Shun Weng
Ming Je Li
kai yi Fang
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Realtek Semiconductor Corp
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Priority to US12/358,261 priority Critical patent/US8094698B2/en
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1376890 六、發明說明: 【發明所屬之技術領域】 本發明有關-種產生-展_脈之方法及其相關展置,尤指一種 可決定所產生之展頻時脈切換頻率的時間點之方法與裝置。 【先前技術】 時脈電路是衫電子裝置中最重要的元件m統整體效能 的影響相當深遠。然而,時脈訊號在其所在的頻率上會產生很強的 電磁干擾(Electromagnetic Interference,EMI)。通常會定義一個門 檻值’且希望時脈訊號的電磁干擾均落在這個門檻之下。 因此’動態地改變時脈訊號的頻率,以使時脈訊號的能量分散至 不同的頻率上,此獄即稱為缝時脈產级術(啊 clock generation ) ° 【發明内容】 本發明的目的之-在於提供—種產生—展頻時脈之方法及其農 置’以解決先前技術中之問題。 、 步mrr露了一種產生一展頻時脈之方法。該方法包含 驟.祕具有一參考週期之一參考時脈;依據該 Γ=Γ之輪出時脈;依據該參考時脈與該展頻時脈產= ‘二開始一第一期間;於第一期間内,依據該第- 選擇訊號,其代表—第—财順序;於第一期 _脈==,_號之第—預定順序輸出該些相位不同之輸 時耽以目’以作為該展頻時脈;依據該參考時脈與該展頻 攄^控制訊號’並開始一第二期間;於第二期間内,依 據5亥第二控制訊號輸出—第二選擇訊號,其代表一第二預定順序, 5亥第二預定順雜該第1定順序實質上相反;以及於第二期間 内,依據該第二選擇職與該第二預定順序輸出該些她不同之輸 ㈣脈中之複數個’以作為該展頻時脈。 本發明之實施例另揭露了一種展頻時脈產生裝置,用來根據一參 考時脈來產生-展頻時脈。展頻時脈產生模組包含:—控制訊號產 生裔’用來依獅參考時脈與該展猶脈分職生控制訊號 與一第二控制訊號,並相對應地開始一第—期間與一第二期間;一 選擇訊生器’时於第—期_,依據該第-控觀號輸出代 表第-預定順序υ擇訊號,且於第二_内,依據該第二控 制訊號輸出代表第二預定順序之第二選擇訊號,其中該第二預定順 序與該第—預定順序實質上相反;-多相位時脈產生器,用來依據 該參考時脈產生複數個相位不同之輸出時脈;以及一選擇器,用來 於第-期間内’依據該第-選擇訊號之第—預定順序輪出該些相位 1376890 同之輸出時脈巾之複數個,以作為該展頻時脈,並於第二期間内, 遞該第二選擇訊號之第二預定順序輸出該些相位不同之輸出時脈 中之複數個’以作為該展頻時脈。 【實施方式】 第1圖為本發明展頻時脈產生裝置腦之實施例示意圖。如第ι 圖所示,展頻時脈產生裝置i⑻包含一參考時脈產生模組ιι〇及一 展頻時脈產生触UO。參考時脈產生餘11G提供具有—參考週 期TREF之一參考時脈CLKref,而展頻時脈產生模组12〇用來根據 參考時脈CLKr^來產生—展辦脈CLKss。展解脈產 包含一判斷與控鮮元⑽及-週期設定單元⑽,其中判斷與控 制早兀13(H系依據參考時脈CLKref與展頻時脈CLKss之差來產生 一第-選擇訊號SEL1或第二選擇訊號SEL2,藉以指示週期設定單 元140由-期間D1切換至一期間D2或相反,本實施例中判斷斑 控制單元130 參考雜CLKref與展_恤CLKss實質相差 W2時進行期間m、D2之切換’以達到一較佳之展頻效果。而 週期設定單元M0依據選擇訊號SEL1、狐2以於期間切、〇2中 分別提供具有-第-平均週期m第二平均週期τ2之展頻時脈 CLKSS。請注意’賴本實施·考時脈CL1Wu作购( cycle)等於50%,但本發明並不侷限於此。 ’ 第2圖(包含圖2A與圖2B)為第!圖所示之展頻時脈⑽ 6 1376890 的不意圖’其中圖2八係從週期 2 一延遲時間。因此,展頻時脈CLKss於期間, 考週期Tref之平均週㈣(如虛線左側=有^於參 =參考週期TREF之平均週期T2(如雜右側 在依據本說明書之揭露實施本發明時,只要期間 稽:’ 相位),本技術領域人士即可設計出各馳=積之總超則時間(或 期Τ2及其相對應之電路來實施本發明。期Τ1與各種平均週 =圖犯所示,設展頻時脈叫之頻率^,因1376890 VI. Description of the Invention: [Technical Field] The present invention relates to a method for generating and displaying a pulse, and a related display thereof, and more particularly to a method for determining a time point of a spread frequency clock switching frequency generated With the device. [Prior Art] The clock circuit is a far-reaching influence on the overall performance of the most important components of the electronic device. However, the clock signal produces a strong electromagnetic interference (EMI) at its frequency. Usually a threshold value is defined and the electromagnetic interference of the desired clock signal falls below this threshold. Therefore, 'the frequency of the clock signal is dynamically changed so that the energy of the clock signal is dispersed to different frequencies, and the prison is called a slit clock generation. [Invention] The object of the present invention It is to provide a method of generating a spread-spectrum clock and its farming to solve the problems in the prior art. Step mrr reveals a method of generating a spread spectrum clock. The method includes a reference clock having a reference period; a clock according to the Γ=Γ; according to the reference clock and the spread frequency clock production = 'two starts a first period; In the first period, according to the first-selection signal, it represents the first-first-order order; in the first period_pulse==, the _th of the first-predetermined order, the output of the different phases is outputted as the target Spreading the clock; according to the reference clock and the spread frequency control signal 'and start a second period; in the second period, according to the 5th second control signal output - the second selection signal, which represents a a second predetermined sequence, the fifth predetermined second order is substantially opposite to the first predetermined order; and in the second period, the second selected position and the second predetermined order are outputted according to the second (four) pulse A plurality of 'as the spread spectrum clock. Embodiments of the present invention further disclose a spread spectrum clock generating apparatus for generating a spread spectrum clock based on a reference clock. The spread spectrum clock generation module includes: - the control signal generation "is used to control the signal and the second control signal according to the lion reference clock and the exhibition, and correspondingly start a period - a period a second period; a selection of the signal generator 'in the first period _, according to the first control number output representative of the first-predetermined order selection signal, and in the second _, according to the second control signal output representative a second predetermined sequence of second selection signals, wherein the second predetermined sequence is substantially opposite to the first predetermined sequence; a multi-phase clock generator for generating a plurality of output clocks having different phases according to the reference clock; And a selector for rotating the plurality of phases 1376890 and the output timing pulse in the predetermined period according to the first predetermined period of the first selection signal as the spread frequency clock, and In the second period, the second predetermined sequence of the second selection signals is outputted as the plurality of output clocks having different phases as the spread-up clock. [Embodiment] FIG. 1 is a schematic view showing an embodiment of a brain of a spread spectrum clock generating apparatus of the present invention. As shown in Fig. ι, the spread spectrum clock generating device i(8) includes a reference clock generating module ιι〇 and a spread frequency clock generating touch UO. The reference clock generation remainder 11G provides a reference clock CLKref having a reference period TREF, and the spread spectrum clock generation module 12 is used to generate the pulse CLKss according to the reference clock CLKr^. The development of the pulse product includes a judgment and control unit (10) and a period setting unit (10), wherein the judgment and control is earlier than 13 (H is based on the difference between the reference clock CLKref and the spread frequency clock CLKss to generate a first selection signal SEL1 Or the second selection signal SEL2, thereby indicating that the period setting unit 140 is switched from the period D1 to the period D2 or vice versa. In the embodiment, the determination point control unit 130 performs the period m when the reference CLKref is substantially different from the sheet CLKss by W2. The switching of D2 is performed to achieve a better spread spectrum effect. The period setting unit M0 provides the spread spectrum with the second average period τ2 of the -first-average period m according to the selection signal SEL1 and the fox 2 for the period cut and the 〇2, respectively. Clock CLKSS. Please note that 'the implementation of the test time CL1Wu is equal to 50%, but the invention is not limited to this. ' Figure 2 (including Figure 2A and Figure 2B) is the first! Shows the spread-frequency clock (10) 6 1376890's not intended 'where Figure 2 is from the cycle 2 a delay time. Therefore, the spread-spectrum clock CLKss during the period, the average period of the test period Tref (four) (such as the left side of the dotted line = there is ^ Ref = the average period T2 of the reference period TREF (such as the right side In carrying out the invention in light of the disclosure of the present specification, one skilled in the art can design a total super-time (or period 2) and corresponding circuitry to implement the present invention, as long as the period: 'phase'. Period Τ1 and various average weeks = map shows, set the frequency of the spread frequency clock ^, because

;CLKss "I 錄),而於__,展㈣脈啦 在平均週期T2之相對應頻㈣(即⑽。如此-來,由於 ZCLKSS的頻率不集中在單一頻率上,故可達到分散能量與降低電 磁干擾之目的。此外,為防止展頻時脈CLKss之頻率相較於泉考 咖之頻率長時間偏快或偏慢,而導致展頻前後的資料產出 率(data th_ghput)不一致,本實施例將期_設定成等 出’以防止這種現象,然此並非本發明之限制,只要使期間^ 相:)時間(或相位)等於期間D2所累積之總超前時間(或 相位),即可防止該現象。 夂 第3圖為第1圖之判斷與控制單元13〇之-範例的示意圖。如第 7; CLKss "I recorded), and in __, exhibit (four) pulse in the average period T2 of the corresponding frequency (four) (ie (10). So - come, because the frequency of ZCLKSS is not concentrated on a single frequency, so the dispersion energy can be achieved In addition, in order to prevent the frequency of the spread spectrum clock CLKss from being too fast or slow compared to the frequency of the spring test, the data output rate (data th_ghput) before and after the spread spectrum is inconsistent, This embodiment sets the period_equal to 'to prevent this phenomenon', but this is not a limitation of the present invention, as long as the period (or phase) is equal to the total lead time (or phase) accumulated in the period D2. , to prevent this phenomenon.夂 Fig. 3 is a schematic diagram of an example of the judgment and control unit 13 of Fig. 1. As number 7

Ttotal +驟6n.,該總延遲時間可用總延遲相位來表示。 乂 ·=第二期間中’設定該展頻_具有—第二週期,i 驟606 該第二週期係小於該參考週期,且累積之總超前時間 即母個箄一週期與每個參考週期之差異累積總合)同樣 為T_ ’該總延遲時間可用總延遲相位來表示。回到步 一第:圖所示之各步驟可利用第卜3或5及4圖所示之各元件來 订/、中步驟608係由判斷與控制單元13〇執行,而步驟⑽〜 612係由週期設定單元⑽執行。各元件之詳細運作請參 此不再瞀沭。Ttotal + step 6n., the total delay time can be expressed by the total delay phase.乂·= in the second period, 'set the spread spectrum_has—the second period, i step 606, the second period is less than the reference period, and the cumulative total lead time is the parent period and each reference period The cumulative total of differences) is also T_ 'this total delay time can be expressed by the total delay phase. Returning to Step 1: The steps shown in the figure can be performed by using the components shown in Figures 3 or 5 and 4, and the step 608 is performed by the judgment and control unit 13〇, and the steps (10) to 612 are performed. It is executed by the cycle setting unit (10). Please refer to the detailed operation of each component.

第7圖為本發明展頻時脈產生裝置7GG之實施例示意圖,裝置 700之架構與第!圖的裝置1〇〇類似,兩者不同之處描述如下。在 第7圖中’判斷與控制單元,(例如—有限狀態機,咖_ machine)係、依據參和夺脈CLKref、展頻時脈CLKss以及一相位維 持訊號PH1來來產生選擇訊號SEU、弧2或SEU以決定切換至 期間D卜D2 4 D3 ’其中相位維持訊號PH1為一計時訊號,用來 指示是否達到一預定時間。本實施例中,於期間D1時,若CLFigure 7 is a schematic diagram of an embodiment of the spread spectrum clock generating device 7GG of the present invention, the architecture of the device 700 and the first! The device of the figure is similar, and the differences between the two are described below. In Fig. 7, the 'judgment and control unit, (for example, finite state machine, coffee machine), according to the reference pulse CLKref, the spread spectrum clock CLKss, and a phase sustain signal PH1 to generate the selection signal SEU, arc 2 Or SEU decides to switch to period D Bu D2 4 D3 'where phase maintaining signal PH1 is a timing signal for indicating whether a predetermined time has been reached. In this embodiment, during the period D1, if CL

SS 落後CLKREF達TREF/2時’即從D1切換至D3;當相位維持訊號PH1 指出由D1切換至D3達該預定時間時,即從D3切換至d2 ;當切 換至D2後,若CLKSS領先CLKREF達TREF/2時,即從D2切換至 D3 ;當相位維持訊號PH1指出由D2切換至D3達該預定時間時, 驗私740於期間 音圖H (包含圖8A與圖8B)為第7圖之展_脈叫s的示 ^®8A係從週期的角度來看,而圖8b則從 ”圖_示’於期間D1、D3及〇2中,展頻時脈CLK= =:T^T〜Τ2,“。摩所示, 日ί脈CLl/似%之頻率為f ’因此於期間m、仍及D2内,展頻 SS之頻率分別為fl (即f — d )、β (亦即f)及β (即f + d )。 此來’她於第2圖之實闕,本實施例可進-步分散展頻時 的頻率’以達到分散能量與降低電磁干擾之目的。此外, 貫施例中,期間D1所累積之總延遲時間(或相位)等於期間m ^累積之總超前時間(或相位),以防止展頻前後之資料產出率不 等〇 月〜雖然月’J述實施例係分別說明二個及三個期間之情形,然 .個以上之期間以實施 技術領域人士可依據本發明之揭露來利用三 本發明。 心考第9圖’第9 ®為本發明產生-展頻時脈之方法之另-操 4 I&例Uiil ’其與第6圖所示之流程圖之差別在於以下步驟: 12 1376890 :步驟91〇:==脈、該展頻時脈以及一相位維持訊號來決 . ==期間、該第二期間以及該第三期間,其中該相位 i92〇 :於=三期間中,設定該展頻時脈具有一第三週期,其 第三週期係等於該參考週期。回到步驟礙。 以及上驟^與7820之實施可利用第7圖之判斷與控制單元-•此不重覆=早實現’該些單元之詳細運作請參前述,於 例9騎示之枝料本㈣所料行的實施 下,明的限制條件’且在不違背本發明之精神的情況 步驟:適=他的中間步姆可將幾個步驟合併成單- 所傲糊1為柄明之她實糊,凡依本㈣帽專利範圍 所做之均㈣倾修飾,皆顧本發明之喊朗。 【圖式簡單說明】 第1圖為本發明展頻時脈產生裝置之第-實施例的示意圖。 第2圖(包含有圖2Α與圖2Β)為第1圖所示之展頻時脈的示意圖。 丄:)/Οδβυ •第3圖為第1圖之判斷與控制私的實施例示意圖。 .帛圖為第1圖之週期設定單元的-$!例的示意圖。 第5圖為第1圖之判斷與控制單元的另一實施例示意圖。 鲁第6圖為本發明產生一展頻時脈之方法之一操作範例的流程圖。 第7圖為本發明展頻時脈產生裝置之第二實施例的示意圖。 第8圖(包含有圖8Α與圖8Β)為第7圖所示之展頻時脈的示意圖。 第9圖為本發明產生一展頻時脈之方法之另一操作範例的流程圖。 ▲ 【主要元件符號說明】 100、700 展頻時脈產生裝置 110 參考時脈產生模組 120、720 展頻時脈產生模組 130 、 730 判斷與控制單元 140 、 740 週期設定單元 CLKREf 參考時脈 CLKSS 展頻時脈 1376890When SS lags CLKREF to TREF/2, it switches from D1 to D3. When phase hold signal PH1 indicates that D1 switches to D3 for the predetermined time, it switches from D3 to d2. When switching to D2, if CLKSS leads CLKREF. When TREF/2 is reached, it is switched from D2 to D3; when the phase maintenance signal PH1 indicates that D2 is switched to D3 for the predetermined time, the inspection 740 is in the period of the sound map H (including FIG. 8A and FIG. 8B) as the seventh diagram. The exhibition _ _ _ _ _ 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 ~Τ2,". As shown in the figure, the frequency of CLl/like % is f'. Therefore, during the period m, still and D2, the frequencies of the spread spectrum SS are fl (ie f - d ), β (ie f) and β ( That is, f + d ). Here, she is shown in Fig. 2, this embodiment can further spread the frequency at the time of spreading to achieve the purpose of dispersing energy and reducing electromagnetic interference. In addition, in the example, the total delay time (or phase) accumulated during the period D1 is equal to the total lead time (or phase) of the period m ^ accumulation, so as to prevent the data output rate before and after the spread spectrum from being different from the month to the month. The 'described embodiment' describes the situation of two and three periods, respectively. However, those skilled in the art can use the three inventions in accordance with the disclosure of the present invention. Heart Test Figure 9 '9th ® is the method of generating a spread-spectrum clock for the present invention. 4 I&Uiil' is different from the flow chart shown in Figure 6 in the following steps: 12 1376890: Step 91〇:== pulse, the spread spectrum clock, and a phase sustain signal to determine. == period, the second period, and the third period, wherein the phase i92〇: in the = three period, the spread spectrum is set The clock has a third period, and the third period is equal to the reference period. Go back to the steps. And the implementation of the above steps ^ and 7820 can use the judgment and control unit of Figure 7 - this does not repeat = early realization 'The detailed operation of these units, please refer to the above, in the case of the example of riding the branch (4) Under the implementation of the line, the explicit conditions 'and the steps that do not violate the spirit of the present invention: appropriate = his intermediate step can be combined into several steps - the proud of the 1 is the handle of her real paste, where According to the (4) cap patent range, the average (4) tilting modification is based on the invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing a first embodiment of a spread spectrum clock generating apparatus of the present invention. Fig. 2 (including Fig. 2A and Fig. 2B) is a schematic diagram of the spread spectrum clock shown in Fig. 1.丄:)/Οδβυ • Fig. 3 is a schematic diagram of an embodiment of the judgment and control of the first figure. The diagram is a schematic diagram of the -$! example of the cycle setting unit of Fig. 1. Fig. 5 is a view showing another embodiment of the judgment and control unit of Fig. 1. Lu 6 shows a flow chart of an operation example of a method for generating a spread spectrum clock according to the present invention. Figure 7 is a schematic view showing a second embodiment of the spread spectrum clock generating apparatus of the present invention. Fig. 8 (including Fig. 8A and Fig. 8A) is a schematic diagram of the spread spectrum clock shown in Fig. 7. Figure 9 is a flow chart showing another example of the operation of the method for generating a spread spectrum clock according to the present invention. ▲ [Main component symbol description] 100, 700 spread spectrum clock generation device 110 reference clock generation module 120, 720 spread spectrum clock generation module 130, 730 judgment and control unit 140, 740 cycle setting unit CLKREf reference clock CLKSS spread spectrum clock 1376890

Tref 參考週期 Ή、T2、T3 平均週期 m、D2、D3 期間 f 、 Ω 、 f2 、 β 頻率 d 差值 Td 延遲時間 310 判斷電路 320 控制訊號產生器 340 選擇訊號產生器 DR 判斷結果 SCI、SC2、SC 控制訊號 SEU、SEL2、SEL3 選擇訊號 CNT 計數訊號 410 多相位時脈產生器 420 選擇器 430 多工器 DL1 〜DLn 延遲器 CK1 〜CKn 輸出時脈 510 振盪器 520、540 計數器 530 有限狀態機 532 運算電路 CN1 振盪器計數值 15 1376890 CN2 參考時脈計數值 CN3 展頻時脈計數值 602〜612、910、920 步驟 PH1 相位維持訊號Tref reference period Ή, T2, T3 averaging period m, D2, D3 period f, Ω, f2, β frequency d difference Td delay time 310 judgment circuit 320 control signal generator 340 selects signal generator DR judgment result SCI, SC2 SC control signal SEU, SEL2, SEL3 select signal CNT count signal 410 multi-phase clock generator 420 selector 430 multiplexer DL1 ~ DLn delay CK1 ~ CKn output clock 510 oscillator 520, 540 counter 530 finite state machine 532 Operation circuit CN1 Oscillator count value 15 1376890 CN2 Reference clock count value CN3 Spread spectrum clock count value 602~612, 910, 920 Step PH1 Phase maintenance signal

1616

Claims (1)

1376890 七 、申請專利範圍: 生展頻 ^脈(spread spectrum clock )之方法 ^ 提供具有-參考週期之一參考時脈;以及以,包含有: 根據該參考時脈來產生一展頻時脈,包含有: 依據該參考時脈產生複數個具有不同相位之輸出時耻· 依,參考時脈與該_•產生 應地開始一第一期間: , 於該第一期間内,依據該第一控制訊號輸出一第一選擇訊 、號,該第一選擇訊號代表一第一預定順序; 。 於該第一期間内,依據該第一選擇訊號之該第一預定順序依 序輪出該些相位不同之輸出時脈中之複數個,_ 頻時脈; 我展 依據該參考時脈與該展頻時脈產生-第二控制訊號,並相對 應地開始一第二期間; ^第-期間内’依據該第二控制訊號輸出一第二選擇吨 ;f’依魏第二選擇喊之該第二預定順序依 1出該些相位不同之輸出時脈中之複數個,以作為該 或貝日寻脈。 2. 如申請專利_第1項所述之方法, 其中該第一期間内所輸出 之 17 該些輸出時脈所對應之一累積延遲 内所輸出之該些輸出時脈所對應之-累積超前^位。間 3. 侧第1項所述街,㈣_—及/或第二押 制訊號之步騾包含: 〜步控 判斷該參考時脈之一第一邊緣是否對應至該展頻時脈之一第二 ,緣以產生-判斷結果,其中該第—邊緣與該第二邊緣分別 心二JE緣及一負緣或者為—負緣及一正緣;以及 田遠判斷結果顯示該第—邊緣對應至該第二邊緣,由該第一期間 /第二期間之狀態下,產生該第二/第一控制訊號,並相對庫地 開始該第二/第一期間。 《如申⑺專利範圍第3項所述之方法,其中該參考時脈之工作週 係等於50ο/ρ 5.如申請專利範圍第1項所述之方法,其另包含: 依據轉考時脈與該賴時脈產生_第三控舰號,並相對應地 開始一第三期間; 於該第三_内,依據該第三控制減輸n選擇訊# •以 及 ~ ’ 於5亥第二期間内’依據該第三選擇訊號輸出該參考時脈與該些相 位不同之輪出時脈中之至少一個,以作為該展步料脈。 18 1376890 6.如申請專利範圍第5項所述之方法,其進一步包含: 於遠第二期間内’依據一計時訊號以產生該第一或第二控制訊 號,並相對應地開始該第一或第二期間。 一種產生一展頻時脈(spreadspectrunid〇ck)之方法,包含有: 提供具有一參考週期之一參考時脈;以及 根據該參考時脈來產生一展頻時脈,包含有: 依據該參考時脈產生複數個具有不同相位之輪出時脈; 依據4數訊號產生一第一控制訊號,並相對應地開始—第 一期間; 於二第』間内’依據該弟—控制訊號輸出一第一選擇訊 號,該第-選擇訊號代表—第一預定順序; 於“第期間内’依據該第—選擇訊號之該第_歉順序依 序輸出4些相位不同之輸出時脈中之複數個,以作為該展 頻時脈;1376890 VII. Patent application scope: The method of spreading spread frequency clock (providing a reference clock with one reference period); and including: generating a spread spectrum clock according to the reference clock, The method includes: generating a plurality of outputs having different phases according to the reference clock, and referring to the clock and the generating a first period: in the first period, according to the first control The signal outputs a first selection signal, and the first selection signal represents a first predetermined sequence; During the first period, a plurality of the output clocks having different phases are sequentially rotated according to the first predetermined sequence of the first selection signal, and the _ frequency clock is used according to the reference clock. The spread spectrum clock generates a second control signal, and correspondingly starts a second period; ^ during the first period, 'outputs a second selected ton according to the second control signal; f' The second predetermined order is based on a plurality of output clocks having different phases to serve as the orbit. 2. The method of claim 1, wherein the output of the output period of the output clock is outputted by the output clock corresponding to one of the output clocks. ^ bit. 3. The street described in item 1 of the side, (4) _- and/or the second step of the signal consisting of: - step control determines whether the first edge of one of the reference clocks corresponds to one of the spread spectrum clocks Second, the edge produces a judgment result, wherein the first edge and the second edge respectively have a JE edge and a negative edge or a negative edge and a positive edge; and the Tianyuan judgment result indicates that the first edge corresponds to The second edge generates the second/first control signal from the state of the first period/second period, and starts the second/first period relative to the library. The method of claim 3, wherein the working period of the reference clock is equal to 50 ο/ρ. 5. The method of claim 1, wherein the method further comprises: And the Lai clock generates a third control ship number, and correspondingly starts a third period; in the third_, according to the third control, the n selection signal #•和~' During the period, at least one of the reference clocks and the rounded clocks different from the phases are outputted according to the third selection signal as the material of the step. The method of claim 5, further comprising: generating a first or second control signal according to a timing signal during a second period, and correspondingly starting the first Or the second period. A method for generating a spread spectrum clock (spreadspectrunid 〇ck) includes: providing a reference clock having a reference period; and generating a spread spectrum clock according to the reference clock, including: according to the reference The pulse generates a plurality of round-trip clocks having different phases; generating a first control signal according to the 4-number signal, and correspondingly starting - the first period; in the second period, according to the brother-control signal outputting a selection signal, the first selection signal represents a first predetermined sequence; in the "first period", according to the first apology sequence of the first selection signal, sequentially outputting a plurality of output clocks having different phases, As the spread spectrum clock; 依據該計數訊號產生一笛- 一 座生第一控制訊號,並相對應地開始一第 二期間; 於該第二期間内,依攄 艨該第二控制訊號輸出一第二選擇訊 l。第二選擇訊號代表一第―箱宕廟序,哕第— 序與該第—預定順序雜一預定川貝 於該第二_内㈣質上4目反;以及 序輪出該些相位不同之;選擇減之对一預疋順序依 頻時脈。 读出時脈中之複數個,以作為該展 19 1376890 8.如申請專利範圍第7項所述之方法,其中該 該些輸㈣脈所對應之—累積延遲相位實質上等於料2出之 内所輸出之該些輸出時脈所對應之一累積超前相位。ζ 一'· 9·如申請專利細第7項所述之方法,其另包含: 依據^计數訊號產生一第三控制訊號,並相對應地開始—第三期 於該第三_内’依據該第三控制訊號輸出—第三選擇訊號 及 u人 1〇. —種展頻時脈產生裝置,包含有:And generating a first control signal according to the counting signal, and correspondingly starting a second period; and during the second period, outputting a second selection signal according to the second control signal. The second selection signal represents a first box-order sequence, the first-order and the first-predetermined sequence are mixed, and the predetermined Chuanbei is in the second_inner (four) quality 4th order reverse; and the sequence is different from the phases ; choose to reduce the frequency of the clock to a pre-order. A plurality of the clocks are read as the method of the present invention, which is described in claim 7, wherein the method of claim 7 wherein the cumulative delay phase corresponds to the cumulative delay phase is substantially equal to the material 2 One of the output clocks outputted therein accumulates the leading phase. ζ一··9· The method of claim 7, wherein the method further comprises: generating a third control signal according to the ^counting signal, and correspondingly starting - the third period is in the third_inner According to the third control signal output-the third selection signal and the u-person 1〇. The spread-spectrum clock generation device includes: 之一參考時脈; 一參考時脈產生模組’时提供具有—參考週期 以及 展頻時脈產生模組,麵接於該參考時脈產生模組,用來根據該 參考時脈來產生-展頻時脈,該展頻時脈產生模組包含有广 一判斷與控制單元,包含有: 控制。fU虎產生器,用來依據該參考時脈與該展頻時脈產 生一第一控制訊號,並相對應地開始一第一期間,以 及依據該參考時脈與該展頻時脈產生一第二控制訊 號,並相對應地開始一第二期間;以及 20 一選擇訊號產生器,用來於該第—期間内,依據該第一控 制訊號輸出-第-選擇訊號,該第—選擇訊號代表一 第一預定順序,以及於該第二期間内,依據該第二控 制訊號輸出-第二選擇訊號,該第二選擇訊號代表一 第二預定順序,該第二預定順序與該第一預定順序實 質上相反;以及 週期設定單元,包含有: 一多相位時脈產生H,縣依魏參考魏產生複數個具 有不同相位之輸出時脈; 選擇為’用來於該第一期間内,依據該第一選擇訊號之 該第-預定順序依序輸出該些她不同之輸出時脈 中之複數個,以作為該展頻時脈,並於該第二期間 内’依據該第二選擇訊號之該第二預定順序依序輸出 該些相位不同之輸出時脈中之複數個,以作為該展頻 時脈。 h如申凊專利範ϋ第10項所述之裝置,其中該選湘於該第一期 門内所輸出.之該些輸出時脈所對應之一累積延遲相位實質上等 於及第一期間内所輸出之該些輸出時脈所對應之一累積超前相 位0 置,其中該判斷與控制單元另 12.如申請專利範圍第1〇項所述之骏 包含: 21 判斷電路’用來酬該參考時脈之―第一邊緣是否對應至該展 _%·脈之帛二邊緣以產生一判斷結果,其中該第一邊緣與 盆該第—邊緣分別為一正緣及一負緣或者為一負緣及一正緣; 其中’當該判斷電路之該判斷結果顯示該第 一邊緣對應至該第二 邊緣,該控制訊號產生器由該第一期間/第二期間之狀態下, 人秦一/第—控制訊號’並相對應地開始該第二/第一期 間。 13.如申睛專利範圍第12項所述之裝置,其中該參考時脈之工作週 期係等於50%。 K如申5月專利㈣帛1〇項所述之裝置,其中該控制訊號產生器另 用來依據鮮树脈與祕麟脈產生-第三控制峨,並相對 應地開始$二期間;該選擇訊號產生單元另用來於該第三期間 鲁内’依據該第三控制訊號輸出-第三選擇訊號;以及該選擇器另 用來於該第三期間内’依據該第三選擇訊號輸出該參考時脈與該 些相位不同之輸㈣脈中之至少—個,以作為該展頻時脈。’ 15. 如申請專概圍第14項所述之震置,其中該控制訊號產生器另 用來於該第三期間内,依據—計時訊號以產生該第—或第二控制 訊號,並相對應地開始該第一或第二期間。 16. —種展頻時脈產生裝置,包含有: 22 j37689〇 參考時脈產生模組,用來提供具有一參考週期之一參考時脈; 以及 ’ 展頻時脈產賴組’雛於該參考時脈產生麵,用來根據該 參考時脈來產生-展解脈,該展頻時脈產生模組包含有「 一判斷與控制單元,包含有: ’One reference clock; a reference clock generation module' provides a reference period and a spread spectrum clock generation module, and is connected to the reference clock generation module for generating according to the reference clock - The spread spectrum clock generation module includes a wide-ranging judgment and control unit, and includes: control. The fU tiger generator is configured to generate a first control signal according to the reference clock and the spread spectrum clock, and correspondingly start a first period, and generate a first according to the reference clock and the spread frequency clock a second control signal, and correspondingly starting a second period; and 20 a selection signal generator for outputting a -selection signal according to the first control signal during the first period, the first selection signal representative a first predetermined sequence, and in the second period, according to the second control signal output-second selection signal, the second selection signal represents a second predetermined sequence, the second predetermined sequence and the first predetermined sequence Substantially opposite; and a period setting unit, comprising: a multi-phase clock generating H, the county according to the Wei reference Wei generating a plurality of output clocks having different phases; selecting 'for the first period, according to the The first-predetermined sequence of the first selection signal sequentially outputs a plurality of the different output clocks of the plurality of selection signals as the spread-time clock, and in the second period The optional second predetermined sequence of signals sequentially output the plurality of outputs of different phases of a plurality of veins, as to the spread spectrum clock. The apparatus of claim 10, wherein the selected one of the output clocks outputted in the first period gate has a cumulative delay phase substantially equal to that in the first period One of the output clocks corresponding to the output accumulates the leading phase 0, wherein the judging and controlling unit further includes: as described in claim 1 of the patent scope: 21 judging circuit 'for repaying the reference Whether the first edge of the pulse corresponds to the edge of the _%· pulse to generate a judgment result, wherein the first edge and the first edge of the basin are a positive edge and a negative edge or a negative edge respectively And a positive edge; wherein 'when the judgment result of the judgment circuit indicates that the first edge corresponds to the second edge, the control signal generator is in the state of the first period/second period, - Control signal 'and correspondingly start the second/first period. 13. The device of claim 12, wherein the reference clock has a working period equal to 50%. K is the device described in the Japanese Patent Application (4), wherein the control signal generator is additionally used to generate a third control according to the fresh tree vein and the secret vein, and correspondingly start the $2 period; The selection signal generating unit is further configured to output the third control signal according to the third control signal during the third period; and the selector is further configured to output the signal according to the third selection signal during the third period The reference clock is at least one of the different (four) pulses different from the phases, as the spread spectrum clock. ' 15. If the application is as described in item 14, the control signal generator is additionally used to generate the first or second control signal according to the timing signal during the third period. The first or second period is started correspondingly. 16. A spread spectrum clock generating apparatus comprising: 22 j37689 〇 reference clock generation module for providing a reference clock having a reference period; and a 'spreading frequency clock generation group' The reference clock generation surface is configured to generate and display a pulse according to the reference clock. The spread spectrum clock generation module includes “a judgment and control unit, including: 一控制訊號產生器,用來依據一計數訊號產生一第-控制 訊號’並相對應地開始一第一期間,並依據該計數訊 號產生一第二控制訊號,並相對應地開始一第二 間; 一, -選擇訊號產生器,用來於該第—_内,依據該第—控 制訊號輸出-第-選擇訊號,該第一選擇訊號代表二 第-預定順序,並於該第二期_,依據該第二控制 訊號輸出-第二選擇訊號,該第二選擇訊號代表一第a control signal generator for generating a first control signal according to a counting signal and correspondingly starting a first period, and generating a second control signal according to the counting signal, and correspondingly starting a second room And a selection signal generator for outputting the first-selection signal according to the first-control signal output-first selection signal in the first__, and in the second period _ According to the second control signal output-second selection signal, the second selection signal represents a first 二預定順序’該第二預定順序與該第-耿順序實曾 上相反;以及 負 一坶期設定單元,包含有: —多相位雜產生n,料娜鱗考時脈纽複數個呈 有不同相位之輪出時脈;以及 選擇裔’用來於該第—期間内,依據該第一選擇訊號 該第y預定順序依序輸出該些相位不同之輪出時脈之 中之複婁文個,以作為該展頻時脈,並於該第二期 内’依據該第二選擇訊號之該第二歡餐依序輪 4相位不同之輸出時脈中之複數個,以作為該展頻 23 時脈。 如申5青專利範圍第16項所述之裝置,The second predetermined sequence 'the second predetermined order is opposite to the first-order sequence; and the negative one-time setting unit includes: - multi-phase miscellaneous generation n, and the number of the nano-scales is different. The round of the phase of the phase; and the selection of the 'for the first period', according to the first selection signal, the first predetermined order of the first selection signal sequentially outputs the recurring texts of the different rounds of the phase And as the spread frequency clock, and in the second period, the plurality of output clocks of the second snack according to the second selection signal are different according to the phase 4, as the spread frequency 23 Clock. Such as the device described in claim 16 of the 5th patent scope, 位期間内所輸出之該些輸出時脈所對應之一累積超前相 φ *申明專利範圍第16項所述之裝置,其中該控制訊號產生器另 其中該選擇器於該第一期 累積延遲相位實質上等 用來依據該計數訊號產生一第三控制訊號, 並相對應地開始一第 二期間;該選擇訊號產生單元另用來於該第三期間内,依據該第 二控制訊號輸出一第三選擇訊號;以及該選擇器另用來於該第三 期間内’依據該第二選擇訊號輸出該參考時脈與該些相位不同之 輪出時脈中之至少一個,以作為該展頻時脈。 八、圓式: 24The device according to claim 16, wherein the control signal generator further includes the selector in the first phase of the cumulative delay phase. Substantially generating a third control signal according to the counting signal, and correspondingly starting a second period; the selecting signal generating unit is further configured to output a second according to the second control signal during the third period a third selection signal; and the selector is further configured to: during the third period, output at least one of the reference clocks different from the phases according to the second selection signal as the spread spectrum pulse. Eight, round: 24
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Publication number Priority date Publication date Assignee Title
CN105871358A (en) * 2015-01-23 2016-08-17 瑞昱半导体股份有限公司 Spread-spectrum clock generating method and device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105871358A (en) * 2015-01-23 2016-08-17 瑞昱半导体股份有限公司 Spread-spectrum clock generating method and device
CN105871358B (en) * 2015-01-23 2018-10-26 瑞昱半导体股份有限公司 Spread spectrum clock pulse generation methods and device

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