1376890 六、發明說明: 【發明所屬之技術領域】 本發明有關-種產生-展_脈之方法及其相關展置,尤指一種 可決定所產生之展頻時脈切換頻率的時間點之方法與裝置。 【先前技術】 時脈電路是衫電子裝置中最重要的元件m統整體效能 的影響相當深遠。然而,時脈訊號在其所在的頻率上會產生很強的 電磁干擾(Electromagnetic Interference,EMI)。通常會定義一個門 檻值’且希望時脈訊號的電磁干擾均落在這個門檻之下。 因此’動態地改變時脈訊號的頻率,以使時脈訊號的能量分散至 不同的頻率上,此獄即稱為缝時脈產级術(啊 clock generation ) ° 【發明内容】 本發明的目的之-在於提供—種產生—展頻時脈之方法及其農 置’以解決先前技術中之問題。 、 步mrr露了一種產生一展頻時脈之方法。該方法包含 驟.祕具有一參考週期之一參考時脈;依據該 Γ=Γ之輪出時脈;依據該參考時脈與該展頻時脈產= ‘二開始一第一期間;於第一期間内,依據該第- 選擇訊號,其代表—第—财順序;於第一期 _脈==,_號之第—預定順序輸出該些相位不同之輸 時耽以目’以作為該展頻時脈;依據該參考時脈與該展頻 攄^控制訊號’並開始一第二期間;於第二期間内,依 據5亥第二控制訊號輸出—第二選擇訊號,其代表一第二預定順序, 5亥第二預定順雜該第1定順序實質上相反;以及於第二期間 内,依據該第二選擇職與該第二預定順序輸出該些她不同之輸 ㈣脈中之複數個’以作為該展頻時脈。 本發明之實施例另揭露了一種展頻時脈產生裝置,用來根據一參 考時脈來產生-展頻時脈。展頻時脈產生模組包含:—控制訊號產 生裔’用來依獅參考時脈與該展猶脈分職生控制訊號 與一第二控制訊號,並相對應地開始一第—期間與一第二期間;一 選擇訊生器’时於第—期_,依據該第-控觀號輸出代 表第-預定順序υ擇訊號,且於第二_内,依據該第二控 制訊號輸出代表第二預定順序之第二選擇訊號,其中該第二預定順 序與該第—預定順序實質上相反;-多相位時脈產生器,用來依據 該參考時脈產生複數個相位不同之輸出時脈;以及一選擇器,用來 於第-期間内’依據該第-選擇訊號之第—預定順序輪出該些相位 1376890 同之輸出時脈巾之複數個,以作為該展頻時脈,並於第二期間内, 遞該第二選擇訊號之第二預定順序輸出該些相位不同之輸出時脈 中之複數個’以作為該展頻時脈。 【實施方式】 第1圖為本發明展頻時脈產生裝置腦之實施例示意圖。如第ι 圖所示,展頻時脈產生裝置i⑻包含一參考時脈產生模組ιι〇及一 展頻時脈產生触UO。參考時脈產生餘11G提供具有—參考週 期TREF之一參考時脈CLKref,而展頻時脈產生模组12〇用來根據 參考時脈CLKr^來產生—展辦脈CLKss。展解脈產 包含一判斷與控鮮元⑽及-週期設定單元⑽,其中判斷與控 制早兀13(H系依據參考時脈CLKref與展頻時脈CLKss之差來產生 一第-選擇訊號SEL1或第二選擇訊號SEL2,藉以指示週期設定單 元140由-期間D1切換至一期間D2或相反,本實施例中判斷斑 控制單元130 參考雜CLKref與展_恤CLKss實質相差 W2時進行期間m、D2之切換’以達到一較佳之展頻效果。而 週期設定單元M0依據選擇訊號SEL1、狐2以於期間切、〇2中 分別提供具有-第-平均週期m第二平均週期τ2之展頻時脈 CLKSS。請注意’賴本實施·考時脈CL1Wu作购( cycle)等於50%,但本發明並不侷限於此。 ’ 第2圖(包含圖2A與圖2B)為第!圖所示之展頻時脈⑽ 6 1376890 的不意圖’其中圖2八係從週期 2 一延遲時間。因此,展頻時脈CLKss於期間, 考週期Tref之平均週㈣(如虛線左側=有^於參 =參考週期TREF之平均週期T2(如雜右側 在依據本說明書之揭露實施本發明時,只要期間 稽:’ 相位),本技術領域人士即可設計出各馳=積之總超則時間(或 期Τ2及其相對應之電路來實施本發明。期Τ1與各種平均週 =圖犯所示,設展頻時脈叫之頻率^,因1376890 VI. Description of the Invention: [Technical Field] The present invention relates to a method for generating and displaying a pulse, and a related display thereof, and more particularly to a method for determining a time point of a spread frequency clock switching frequency generated With the device. [Prior Art] The clock circuit is a far-reaching influence on the overall performance of the most important components of the electronic device. However, the clock signal produces a strong electromagnetic interference (EMI) at its frequency. Usually a threshold value is defined and the electromagnetic interference of the desired clock signal falls below this threshold. Therefore, 'the frequency of the clock signal is dynamically changed so that the energy of the clock signal is dispersed to different frequencies, and the prison is called a slit clock generation. [Invention] The object of the present invention It is to provide a method of generating a spread-spectrum clock and its farming to solve the problems in the prior art. Step mrr reveals a method of generating a spread spectrum clock. The method includes a reference clock having a reference period; a clock according to the Γ=Γ; according to the reference clock and the spread frequency clock production = 'two starts a first period; In the first period, according to the first-selection signal, it represents the first-first-order order; in the first period_pulse==, the _th of the first-predetermined order, the output of the different phases is outputted as the target Spreading the clock; according to the reference clock and the spread frequency control signal 'and start a second period; in the second period, according to the 5th second control signal output - the second selection signal, which represents a a second predetermined sequence, the fifth predetermined second order is substantially opposite to the first predetermined order; and in the second period, the second selected position and the second predetermined order are outputted according to the second (four) pulse A plurality of 'as the spread spectrum clock. Embodiments of the present invention further disclose a spread spectrum clock generating apparatus for generating a spread spectrum clock based on a reference clock. The spread spectrum clock generation module includes: - the control signal generation "is used to control the signal and the second control signal according to the lion reference clock and the exhibition, and correspondingly start a period - a period a second period; a selection of the signal generator 'in the first period _, according to the first control number output representative of the first-predetermined order selection signal, and in the second _, according to the second control signal output representative a second predetermined sequence of second selection signals, wherein the second predetermined sequence is substantially opposite to the first predetermined sequence; a multi-phase clock generator for generating a plurality of output clocks having different phases according to the reference clock; And a selector for rotating the plurality of phases 1376890 and the output timing pulse in the predetermined period according to the first predetermined period of the first selection signal as the spread frequency clock, and In the second period, the second predetermined sequence of the second selection signals is outputted as the plurality of output clocks having different phases as the spread-up clock. [Embodiment] FIG. 1 is a schematic view showing an embodiment of a brain of a spread spectrum clock generating apparatus of the present invention. As shown in Fig. ι, the spread spectrum clock generating device i(8) includes a reference clock generating module ιι〇 and a spread frequency clock generating touch UO. The reference clock generation remainder 11G provides a reference clock CLKref having a reference period TREF, and the spread spectrum clock generation module 12 is used to generate the pulse CLKss according to the reference clock CLKr^. The development of the pulse product includes a judgment and control unit (10) and a period setting unit (10), wherein the judgment and control is earlier than 13 (H is based on the difference between the reference clock CLKref and the spread frequency clock CLKss to generate a first selection signal SEL1 Or the second selection signal SEL2, thereby indicating that the period setting unit 140 is switched from the period D1 to the period D2 or vice versa. In the embodiment, the determination point control unit 130 performs the period m when the reference CLKref is substantially different from the sheet CLKss by W2. The switching of D2 is performed to achieve a better spread spectrum effect. The period setting unit M0 provides the spread spectrum with the second average period τ2 of the -first-average period m according to the selection signal SEL1 and the fox 2 for the period cut and the 〇2, respectively. Clock CLKSS. Please note that 'the implementation of the test time CL1Wu is equal to 50%, but the invention is not limited to this. ' Figure 2 (including Figure 2A and Figure 2B) is the first! Shows the spread-frequency clock (10) 6 1376890's not intended 'where Figure 2 is from the cycle 2 a delay time. Therefore, the spread-spectrum clock CLKss during the period, the average period of the test period Tref (four) (such as the left side of the dotted line = there is ^ Ref = the average period T2 of the reference period TREF (such as the right side In carrying out the invention in light of the disclosure of the present specification, one skilled in the art can design a total super-time (or period 2) and corresponding circuitry to implement the present invention, as long as the period: 'phase'. Period Τ1 and various average weeks = map shows, set the frequency of the spread frequency clock ^, because
;CLKss "I 錄),而於__,展㈣脈啦 在平均週期T2之相對應頻㈣(即⑽。如此-來,由於 ZCLKSS的頻率不集中在單一頻率上,故可達到分散能量與降低電 磁干擾之目的。此外,為防止展頻時脈CLKss之頻率相較於泉考 咖之頻率長時間偏快或偏慢,而導致展頻前後的資料產出 率(data th_ghput)不一致,本實施例將期_設定成等 出’以防止這種現象,然此並非本發明之限制,只要使期間^ 相:)時間(或相位)等於期間D2所累積之總超前時間(或 相位),即可防止該現象。 夂 第3圖為第1圖之判斷與控制單元13〇之-範例的示意圖。如第 7; CLKss "I recorded), and in __, exhibit (four) pulse in the average period T2 of the corresponding frequency (four) (ie (10). So - come, because the frequency of ZCLKSS is not concentrated on a single frequency, so the dispersion energy can be achieved In addition, in order to prevent the frequency of the spread spectrum clock CLKss from being too fast or slow compared to the frequency of the spring test, the data output rate (data th_ghput) before and after the spread spectrum is inconsistent, This embodiment sets the period_equal to 'to prevent this phenomenon', but this is not a limitation of the present invention, as long as the period (or phase) is equal to the total lead time (or phase) accumulated in the period D2. , to prevent this phenomenon.夂 Fig. 3 is a schematic diagram of an example of the judgment and control unit 13 of Fig. 1. As number 7
Ttotal +驟6n.,該總延遲時間可用總延遲相位來表示。 乂 ·=第二期間中’設定該展頻_具有—第二週期,i 驟606 該第二週期係小於該參考週期,且累積之總超前時間 即母個箄一週期與每個參考週期之差異累積總合)同樣 為T_ ’該總延遲時間可用總延遲相位來表示。回到步 一第:圖所示之各步驟可利用第卜3或5及4圖所示之各元件來 订/、中步驟608係由判斷與控制單元13〇執行,而步驟⑽〜 612係由週期設定單元⑽執行。各元件之詳細運作請參 此不再瞀沭。Ttotal + step 6n., the total delay time can be expressed by the total delay phase.乂·= in the second period, 'set the spread spectrum_has—the second period, i step 606, the second period is less than the reference period, and the cumulative total lead time is the parent period and each reference period The cumulative total of differences) is also T_ 'this total delay time can be expressed by the total delay phase. Returning to Step 1: The steps shown in the figure can be performed by using the components shown in Figures 3 or 5 and 4, and the step 608 is performed by the judgment and control unit 13〇, and the steps (10) to 612 are performed. It is executed by the cycle setting unit (10). Please refer to the detailed operation of each component.
第7圖為本發明展頻時脈產生裝置7GG之實施例示意圖,裝置 700之架構與第!圖的裝置1〇〇類似,兩者不同之處描述如下。在 第7圖中’判斷與控制單元,(例如—有限狀態機,咖_ machine)係、依據參和夺脈CLKref、展頻時脈CLKss以及一相位維 持訊號PH1來來產生選擇訊號SEU、弧2或SEU以決定切換至 期間D卜D2 4 D3 ’其中相位維持訊號PH1為一計時訊號,用來 指示是否達到一預定時間。本實施例中,於期間D1時,若CLFigure 7 is a schematic diagram of an embodiment of the spread spectrum clock generating device 7GG of the present invention, the architecture of the device 700 and the first! The device of the figure is similar, and the differences between the two are described below. In Fig. 7, the 'judgment and control unit, (for example, finite state machine, coffee machine), according to the reference pulse CLKref, the spread spectrum clock CLKss, and a phase sustain signal PH1 to generate the selection signal SEU, arc 2 Or SEU decides to switch to period D Bu D2 4 D3 'where phase maintaining signal PH1 is a timing signal for indicating whether a predetermined time has been reached. In this embodiment, during the period D1, if CL
SS 落後CLKREF達TREF/2時’即從D1切換至D3;當相位維持訊號PH1 指出由D1切換至D3達該預定時間時,即從D3切換至d2 ;當切 換至D2後,若CLKSS領先CLKREF達TREF/2時,即從D2切換至 D3 ;當相位維持訊號PH1指出由D2切換至D3達該預定時間時, 驗私740於期間 音圖H (包含圖8A與圖8B)為第7圖之展_脈叫s的示 ^®8A係從週期的角度來看,而圖8b則從 ”圖_示’於期間D1、D3及〇2中,展頻時脈CLK= =:T^T〜Τ2,“。摩所示, 日ί脈CLl/似%之頻率為f ’因此於期間m、仍及D2内,展頻 SS之頻率分別為fl (即f — d )、β (亦即f)及β (即f + d )。 此來’她於第2圖之實闕,本實施例可進-步分散展頻時 的頻率’以達到分散能量與降低電磁干擾之目的。此外, 貫施例中,期間D1所累積之總延遲時間(或相位)等於期間m ^累積之總超前時間(或相位),以防止展頻前後之資料產出率不 等〇 月〜雖然月’J述實施例係分別說明二個及三個期間之情形,然 .個以上之期間以實施 技術領域人士可依據本發明之揭露來利用三 本發明。 心考第9圖’第9 ®為本發明產生-展頻時脈之方法之另-操 4 I&例Uiil ’其與第6圖所示之流程圖之差別在於以下步驟: 12 1376890 :步驟91〇:==脈、該展頻時脈以及一相位維持訊號來決 . ==期間、該第二期間以及該第三期間,其中該相位 i92〇 :於=三期間中,設定該展頻時脈具有一第三週期,其 第三週期係等於該參考週期。回到步驟礙。 以及上驟^與7820之實施可利用第7圖之判斷與控制單元-•此不重覆=早實現’該些單元之詳細運作請參前述,於 例9騎示之枝料本㈣所料行的實施 下,明的限制條件’且在不違背本發明之精神的情況 步驟:適=他的中間步姆可將幾個步驟合併成單- 所傲糊1為柄明之她實糊,凡依本㈣帽專利範圍 所做之均㈣倾修飾,皆顧本發明之喊朗。 【圖式簡單說明】 第1圖為本發明展頻時脈產生裝置之第-實施例的示意圖。 第2圖(包含有圖2Α與圖2Β)為第1圖所示之展頻時脈的示意圖。 丄:)/Οδβυ •第3圖為第1圖之判斷與控制私的實施例示意圖。 .帛圖為第1圖之週期設定單元的-$!例的示意圖。 第5圖為第1圖之判斷與控制單元的另一實施例示意圖。 鲁第6圖為本發明產生一展頻時脈之方法之一操作範例的流程圖。 第7圖為本發明展頻時脈產生裝置之第二實施例的示意圖。 第8圖(包含有圖8Α與圖8Β)為第7圖所示之展頻時脈的示意圖。 第9圖為本發明產生一展頻時脈之方法之另一操作範例的流程圖。 ▲ 【主要元件符號說明】 100、700 展頻時脈產生裝置 110 參考時脈產生模組 120、720 展頻時脈產生模組 130 、 730 判斷與控制單元 140 、 740 週期設定單元 CLKREf 參考時脈 CLKSS 展頻時脈 1376890When SS lags CLKREF to TREF/2, it switches from D1 to D3. When phase hold signal PH1 indicates that D1 switches to D3 for the predetermined time, it switches from D3 to d2. When switching to D2, if CLKSS leads CLKREF. When TREF/2 is reached, it is switched from D2 to D3; when the phase maintenance signal PH1 indicates that D2 is switched to D3 for the predetermined time, the inspection 740 is in the period of the sound map H (including FIG. 8A and FIG. 8B) as the seventh diagram. The exhibition _ _ _ _ _ 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 ~Τ2,". As shown in the figure, the frequency of CLl/like % is f'. Therefore, during the period m, still and D2, the frequencies of the spread spectrum SS are fl (ie f - d ), β (ie f) and β ( That is, f + d ). Here, she is shown in Fig. 2, this embodiment can further spread the frequency at the time of spreading to achieve the purpose of dispersing energy and reducing electromagnetic interference. In addition, in the example, the total delay time (or phase) accumulated during the period D1 is equal to the total lead time (or phase) of the period m ^ accumulation, so as to prevent the data output rate before and after the spread spectrum from being different from the month to the month. The 'described embodiment' describes the situation of two and three periods, respectively. However, those skilled in the art can use the three inventions in accordance with the disclosure of the present invention. Heart Test Figure 9 '9th ® is the method of generating a spread-spectrum clock for the present invention. 4 I&Uiil' is different from the flow chart shown in Figure 6 in the following steps: 12 1376890: Step 91〇:== pulse, the spread spectrum clock, and a phase sustain signal to determine. == period, the second period, and the third period, wherein the phase i92〇: in the = three period, the spread spectrum is set The clock has a third period, and the third period is equal to the reference period. Go back to the steps. And the implementation of the above steps ^ and 7820 can use the judgment and control unit of Figure 7 - this does not repeat = early realization 'The detailed operation of these units, please refer to the above, in the case of the example of riding the branch (4) Under the implementation of the line, the explicit conditions 'and the steps that do not violate the spirit of the present invention: appropriate = his intermediate step can be combined into several steps - the proud of the 1 is the handle of her real paste, where According to the (4) cap patent range, the average (4) tilting modification is based on the invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing a first embodiment of a spread spectrum clock generating apparatus of the present invention. Fig. 2 (including Fig. 2A and Fig. 2B) is a schematic diagram of the spread spectrum clock shown in Fig. 1.丄:)/Οδβυ • Fig. 3 is a schematic diagram of an embodiment of the judgment and control of the first figure. The diagram is a schematic diagram of the -$! example of the cycle setting unit of Fig. 1. Fig. 5 is a view showing another embodiment of the judgment and control unit of Fig. 1. Lu 6 shows a flow chart of an operation example of a method for generating a spread spectrum clock according to the present invention. Figure 7 is a schematic view showing a second embodiment of the spread spectrum clock generating apparatus of the present invention. Fig. 8 (including Fig. 8A and Fig. 8A) is a schematic diagram of the spread spectrum clock shown in Fig. 7. Figure 9 is a flow chart showing another example of the operation of the method for generating a spread spectrum clock according to the present invention. ▲ [Main component symbol description] 100, 700 spread spectrum clock generation device 110 reference clock generation module 120, 720 spread spectrum clock generation module 130, 730 judgment and control unit 140, 740 cycle setting unit CLKREf reference clock CLKSS spread spectrum clock 1376890
Tref 參考週期 Ή、T2、T3 平均週期 m、D2、D3 期間 f 、 Ω 、 f2 、 β 頻率 d 差值 Td 延遲時間 310 判斷電路 320 控制訊號產生器 340 選擇訊號產生器 DR 判斷結果 SCI、SC2、SC 控制訊號 SEU、SEL2、SEL3 選擇訊號 CNT 計數訊號 410 多相位時脈產生器 420 選擇器 430 多工器 DL1 〜DLn 延遲器 CK1 〜CKn 輸出時脈 510 振盪器 520、540 計數器 530 有限狀態機 532 運算電路 CN1 振盪器計數值 15 1376890 CN2 參考時脈計數值 CN3 展頻時脈計數值 602〜612、910、920 步驟 PH1 相位維持訊號Tref reference period Ή, T2, T3 averaging period m, D2, D3 period f, Ω, f2, β frequency d difference Td delay time 310 judgment circuit 320 control signal generator 340 selects signal generator DR judgment result SCI, SC2 SC control signal SEU, SEL2, SEL3 select signal CNT count signal 410 multi-phase clock generator 420 selector 430 multiplexer DL1 ~ DLn delay CK1 ~ CKn output clock 510 oscillator 520, 540 counter 530 finite state machine 532 Operation circuit CN1 Oscillator count value 15 1376890 CN2 Reference clock count value CN3 Spread spectrum clock count value 602~612, 910, 920 Step PH1 Phase maintenance signal
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