CN1983446A

CN1983446A - Memory controller and its controlling method

Info

Publication number: CN1983446A
Application number: CN 200510137024
Authority: CN
Inventors: 陈玉国; 陈信全
Original assignee: Prolific Technology Inc
Current assignee: Prolific Technology Inc
Priority date: 2005-12-13
Filing date: 2005-12-13
Publication date: 2007-06-20

Abstract

An internal memory controller is prepared as generating multiple phase clock signal by phase-locked loop according to system clock signal, setting frequency of these phase clock signals to be as the same as that of system clock signal but arranging different phase-difference on one after another of these phase clock signals, receiving these phase clock signals by multitask executor, selecting one of these phase clock signals and outputting selected one for generating a selected phase clock signal under control of control logic circuit.

Description

Memory Controller Hub and control method thereof

Technical field

The present invention is relevant for a kind of Memory Controller Hub and method thereof, and is particularly to a kind of DDR sdram memory controller and method thereof.

Background technology

Please refer to Fig. 1, it has illustrated the calcspar of known Memory Controller Hub.Memory Controller Hub 100 comprises control logic circuit 110, trigger 120,130 and impact damper 141 to 143.When data transmission, need the content of acquisition transmission data, must cooperate to produce corresponding acquiring signal.And acquiring signal need cooperate demand and delay period.

Control logic circuit 110 output controlling signal C011.Trigger 120 receives controlling signal C011 and system clock signal Clk11, to produce controlling signal C012 to trigger 130.Trigger 120 receives controlling signal C012 and postpones back system clock signal Clk12, to produce controlling signal C012 output.

Postponing the generation of back system clock signal Clk12, is to produce through impact damper 141 to 143 with system clock signal Clk11.If with the system clock signal of 100Mhz, postpone the delay that back system clock signal Clk12 had 1/4 cycle, i.e. 2.5ns if make.Need adjustment, and consider the delay that circuit itself causes through impact damper.And each fine setting all needs the layout through accurate simulation and circuit.Frequency is if change 80Mhz into, and former 2.5ns is promptly inapplicable.Therefore, this known Memory Controller Hub also can't be changed frequency arbitrarily.

Please refer to Fig. 2, it has illustrated the calcspar of another known Memory Controller Hub.Memory Controller Hub 200 is with Memory Controller Hub 100 differences of Fig. 1, the generation of system clock signal Clk13 after the delay of input trigger 130, be to make system clock signal Clk11 behind impact damper 241 to 244, select the clock signal that produces through how many buffer delay through multiplexer 245 again, with system clock signal Clk13 after the output delay to trigger 130.Though can see through the degree that multiplexer selective system clock signal postpones, the precision of phase retardation still must be by the time and the quantity decision thereof of impact damper buffering itself, and effect is also not as expection.And above-mentioned known technology is subject to variable influences such as processing procedure, temperature, voltage, is difficult to pulling speed.

Summary of the invention

In view of this, purpose of the present invention is providing a kind of Memory Controller Hub and control method thereof exactly.But the coupled system demand is adjusted the signal delay phase place.And can change predominant frequency according to system requirements, and need not reset phase retardation.

According to purpose of the present invention, a kind of Memory Controller Hub is proposed, comprise control logic circuit, PLL and multiplexer.PLL produces a plurality of phase clock signals according to the system clock signal, and these a little phase clock signals and system clock signal have same frequency, and these phase clock signals have different phase differential mutually.Multiplexer receives these phase clock signals, under the control of control logic circuit, selects an output of these phase clock signals, selects back phase clock signal to produce one.

According to another object of the present invention, a kind of internal memory control method is proposed, be used for a Memory Controller Hub.At first, produce a plurality of phase clock signals with PLL according to the system clock signal.These phase clock signals and system clock signal have same frequency, and these phase clock signals have different phase differential mutually.Afterwards, select an output of these a little phase clock signals, select back phase clock signal to produce one.

For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below:

Description of drawings

Fig. 1 has illustrated the calcspar of known Memory Controller Hub.。

Fig. 2 has illustrated the calcspar of another known Memory Controller Hub.

Fig. 3 has illustrated the calcspar according to the Memory Controller Hub of a preferred embodiment of the present invention.

Fig. 4 has illustrated the calcspar according to the Memory Controller Hub of the present invention one second embodiment.

Embodiment

Please refer to Fig. 3, it has illustrated the calcspar according to the Memory Controller Hub of a preferred embodiment of the present invention.Memory Controller Hub 300 comprise control logic circuit 310, PLL 320 (Phase Locked Loop, PLL) and multiplexer 330.PLL 320 produces a plurality of phase clock signal Cmp according to system clock signal Clk31, and these phase clock signal Cmp and system clock signal Clk31 have same frequency, and the phase clock signal has different phase differential each other.Multiplexer 330 receives above-mentioned phase clock signal Cmp, in the signal Clkse of control logic circuit 310 control down, selects one of phase clock signal Cmp output, selects back phase clock signal Clk32 to produce one.

Select back phase clock signal Clk32 in order to as clock signal, or in order to as dodging control signal (strobe signal).The delay degree of visual required clock signal, or the degree of dodging the required delay period of control signal is adjusted the output of multiplexer 330.

Memory Controller Hub 300 for example is used in the double SDRAM (Synchronous dynamic random access memory) (Double Data RateSDRAM, DDR SDRAM).If select back phase clock signal Clk32 with being when dodging the control signal, in the demand of DDRSDRAM, the stage casing of palpus data signals is with acquisition data, and than 1/4 cycle of system clock signal delay.Cause is utilized two along clock conversion (Double Transitlon Clocking) technology in DDR SDRAM, trigger transmission at rising edge (Raising edge) and lower edge (the Falling edge) of system clock signal, and promptly per approximately 1/2 cycle promptly need trigger.Promptly need in the stage casing of data and dodge the control signal, promptly 1/4 cycle is with the acquisition data.

DDR SDRAM is SDRAM (Synchronous dynamic random access memory) (Synchronized Dynamic RandomAccess Memory, SDRAM) next memory architecture from generation to generation.The comparison of DDR SDRAM and SDRAM, the transmission speed of DDRSDRAM are the double of SDRAM.If the clock frequency of SDRAM is 66Mhz, and that the transmission time is 15ns at interval.That is for DDR SDRAM speech, and the interval of its transmission data time then is 7.5ns, and transmitted frequency can reach 133Mhz.

And the principle of DDR SDRAM is promptly as described above, and transmitting data is to adopt in the same clock period, and wave band is all being done the work that passes data up and down, and compared to SDRAM in the same clock period, only pass a secondary data, the efficient of DDR SDRAM is the twice of SDRAM.

PLL 320 is that the multiple phase that it is inner is pulled out, and produces multiple phase but still the clock signal of same frequency, each promptly above-mentioned phase clock signal Cmp.In the present embodiment, have eight phase clock signal Cmp, postpone 1/8 cycle respectively, 2/8 cycle in cycle to 7/8.No matter and all permanent sets of any frequency of all phase relations in the PLL 320, so the phase clock signal after selecting, can be by frequency influence yet.And the frequency of phase clock signal Cmp equates with system clock signal Clk31.

If the frequency of internal memory, must be corresponding during system conversion, or during the frequency lifting of environmental impact, can not have influence on the relative phase place of signal yet.And system can aim at the needed phase place of controlling signal automatically, and does not need software to adjust again.

Please refer to Fig. 4, it has illustrated the calcspar of the Memory Controller Hub of second embodiment that proposes according to the present invention.Be that with preceding embodiment difference present embodiment also comprises trigger 410 and 420.The first signal Co31 of trigger 410 receiving system clock signal Clk31 and control logic circuit 310 is to export the second signal Co32.Trigger 420 receives the second signal Co32 and selects back phase clock signal Clk32 to produce the 3rd signal S3.The 3rd signal S3 is reading signal for example, writes signal or address signal for example with thinking controlling signal.

Memory Controller Hub that the above embodiment of the present invention disclosed and control method thereof, but the coupled system demand is adjusted the signal delay phase place.And can change predominant frequency according to system requirements, and need not reset phase retardation, not need the practice as is known to cooperate different frequencies, to change signal required time delay.

In sum; though the present invention discloses as above with a preferred embodiment; right its is not in order to limit the present invention; anyly be familiar with present technique field person; without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, so protection scope of the present invention is as the criterion when looking accompanying the claim person of defining.

Claims

1. Memory Controller Hub comprises:

One control logic circuit;

One PLL produces a plurality of phase clock signals according to a system clock signal, and these phase clock signals and this system clock signal have same frequency, and these phase clock signals have different phase differential mutually; And

One multiplexer receives those phase clock signals, under the control of this control logic circuit, selects the output of one of these phase clock signals, selects back phase clock signal to produce one.

2. controller as claimed in claim 1 is characterized in that, this selection back phase clock signal is with being clock signal.

3. controller as claimed in claim 1 is characterized in that, this selection back phase clock signal is with being sudden strain of a muscle control signal.

4. controller as claimed in claim 1 is characterized in that, also comprises:

First trigger receives one first signal of this system clock signal and this control logic circuit, to export one second signal; And

One second trigger receives this second signal and this selection back phase clock signal to produce one the 3rd signal.

5. controller as claimed in claim 1 is characterized in that the 3rd signal is used as controlling signal.

6. controller as claimed in claim 1 is characterized in that, is used for double SDRAM (Synchronous dynamic random access memory).

7. an internal memory control method is used for a Memory Controller Hub, comprising:

Produce a plurality of phase clock signals with a PLL according to a system clock signal, these phase clock signals and this system clock signal have same frequency, and these phase clock signals have different phase differential mutually; And

Select the output of one of these phase clock signals, select back phase clock signal to produce one.

8. control method as claimed in claim 7 is characterized in that, this selection back phase clock signal is used as clock signal.

9. control method as claimed in claim 7 is characterized in that, this selection back phase clock signal is used as and dodges the control signal.

10. control method as claimed in claim 7 is characterized in that this Memory Controller Hub is used for DDRSDRAM.