CN113311314A - IC time sequence verification method and device - Google Patents
IC time sequence verification method and device Download PDFInfo
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- CN113311314A CN113311314A CN202110583310.0A CN202110583310A CN113311314A CN 113311314 A CN113311314 A CN 113311314A CN 202110583310 A CN202110583310 A CN 202110583310A CN 113311314 A CN113311314 A CN 113311314A
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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Abstract
The invention discloses an IC timing sequence verification method and device, wherein a user can send different waveform generation instructions to a processing device according to different types of ICs to be tested and user requirements, so that the processing device generates a test timing sequence waveform corresponding to the waveform generation instructions, and then whether the timing sequence waveform to be tested generated by the ICs to be tested based on the test timing sequence waveform is the same as an expected timing sequence waveform is judged so as to judge whether the ICs to be tested meet the design requirements of the user. Because the processing device is not limited by a circuit structure when generating the test time sequence waveform, the processing device can generate any type of test time sequence waveform to meet different inspection requirements, when a research and development designer researches a new IC to be tested, the processing device can directly generate the test time sequence waveform corresponding to the IC to be tested to test the IC to be tested, a matched detection device corresponding to the IC to be tested does not need to be developed, and the efficiency of verifying the IC to be tested is improved.
Description
Technical Field
The invention relates to the field of IC verification and test, in particular to an IC timing sequence verification method and device.
Background
At present, in an IC (Integrated Circuit) verification process, a detection IC is generally connected to an IC to be tested through an IC interface, the detection IC sends one or more test timing waveforms to the IC to be tested, after the IC to be tested receives the test timing waveforms, the corresponding test timing waveforms are output according to the test timing waveforms and fed back to the detection IC, when the IC to be tested has no fault, the output timing waveforms to be tested based on the test timing waveforms are the same as expected timing waveforms, and when the IC to be tested has a fault, the output timing waveforms to be tested based on the test timing waveforms are different from the expected timing waveforms. Therefore, after the detection IC receives the timing sequence waveform to be detected, it is required to detect whether the timing sequence waveform to be detected is the same as an expected timing sequence waveform corresponding to the test timing sequence waveform, so as to determine whether the IC to be detected meets the design requirement of the user, if so, it is determined that the IC to be detected meets the design requirement of the user, and if not, it is determined that the IC to be detected does not meet the design requirement of the user. In the prior art, the detection IC can only output several test timing waveforms corresponding to its own circuit structure due to the limitation of its own circuit structure, and cannot self-define the test timing waveforms output by itself, so that when a research and development designer develops a new IC to be tested, and the test timing waveforms required by the new IC to be tested do not match the test timing waveforms that can be output by the detection IC, a matched detection device corresponding to the IC to be tested needs to be developed to verify the IC to be tested, which seriously affects the verification efficiency.
In addition, in the prior art, UVM (Universal Verification Methodology) is also used for simulation Verification of the timing sequence of the IC to be tested, but the UVM has the following disadvantages: a) a time sequence waveform cannot be generated in a waveform acquisition mode; b) a large number of system level tests cannot be run due to hardware performance limitations of the simulation environment; c) and the method can not be used for testing the finished IC to be tested.
In summary, it is necessary to provide an IC timing verification method to adapt to the verification of various ICs to be tested.
Disclosure of Invention
The invention aims to provide an IC (integrated circuit) timing sequence verification method and device, which can generate any test timing sequence waveform to meet the inspection requirements of different ICs to be tested, can directly generate the test timing sequence waveform corresponding to the ICs to be tested to test the ICs to be tested when a research designer develops a new IC to be tested, does not need to develop a matched detection device corresponding to the ICs to be tested, and improves the efficiency of verifying the ICs to be tested.
In order to solve the above technical problem, the present invention provides an IC timing verification method, applied to a processing apparatus, including:
receiving a waveform generation instruction sent by a user based on the type of an IC to be tested and the user requirement;
generating a test time sequence waveform corresponding to the type of the IC to be tested and the user requirement based on the waveform generation instruction, and sending the test time sequence waveform to the IC to be tested;
sampling a time sequence waveform to be tested generated by the IC to be tested based on the test time sequence waveform;
judging whether the time sequence waveform to be detected is the same as the expected time sequence waveform;
if so, judging that the IC to be tested meets the design requirement of the user;
if not, judging that the IC to be tested does not meet the design requirements of the user.
Preferably, the determining whether the time-series waveform to be measured is the same as the expected time-series waveform includes:
and judging whether the time sequence waveform to be detected is the same as the expected time sequence waveform or not according to the type and/or frequency and/or high-low level logic of the time sequence waveform to be detected.
Preferably, generating a test timing waveform corresponding to the IC to be tested based on the waveform generation instruction, and sending the test timing waveform to the IC to be tested, includes:
reading test time sequence data which is stored in a memory and corresponds to the type of the IC to be tested and user requirements based on the waveform generation instruction, and generating a corresponding test time sequence waveform based on the test time sequence data;
and sending the test time sequence waveform generated based on the test time sequence data to the IC to be tested.
Preferably, the waveform generation instruction includes data information corresponding to the desired timing waveform;
generating a test timing waveform corresponding to the IC to be tested based on the waveform generation instruction, including:
and generating a test time sequence waveform corresponding to the type of the IC to be tested and the user requirement based on the data information.
Preferably, after generating a test timing waveform corresponding to the type of the IC to be tested and a user requirement and sending the test timing waveform to the IC to be tested, the method further includes:
and marking the test time sequence data corresponding to the test time sequence waveform and storing the test time sequence data in a memory.
Preferably, sampling a timing waveform to be tested generated by the IC to be tested based on the test timing waveform includes:
after receiving the trigger signal, starting to sample the time sequence waveform to be detected at a preset sampling frequency;
judging whether the sampling number reaches a preset sampling number or not;
if so, stopping sampling, and judging whether the time sequence waveform to be detected is the same as the expected time sequence waveform.
Preferably, after sampling the timing waveform to be tested generated by the IC to be tested based on the test timing waveform, the method further includes:
and sending the time sequence waveform to be detected to a display device to display the time sequence waveform to be detected.
Preferably, after sampling the timing waveform to be tested generated by the IC to be tested based on the test timing waveform, the method further includes:
and sending the time sequence waveform to be tested to an editing device so that a user edits the time sequence waveform to be tested through the editing device according to the time sequence waveform to be tested displayed on the display device to generate a test time sequence waveform meeting the preset requirement of the user.
To solve the above technical problem, the present invention provides an IC timing verification apparatus, comprising:
a memory for storing a computer program;
processing means for implementing the steps of the IC timing verification method described above when executing the computer program.
Preferably, the processing device comprises a time sequence processing module and a time sequence hardware module connected with the time sequence processing module;
the timing sequence processing module is used for receiving a waveform generation instruction sent by a user based on the type of an IC to be tested and user requirements; judging whether the time sequence waveform to be detected is the same as the expected time sequence waveform or not according to the time sequence waveform to be detected, if so, judging that the IC to be detected meets the design requirement of a user, and if not, judging that the IC to be detected does not meet the design requirement of the user;
the time sequence hardware module is used for generating a test time sequence waveform corresponding to the type of the IC to be tested and the user requirement based on the waveform generation instruction, sending the test time sequence waveform to the IC to be tested, sampling the time sequence waveform to be tested generated by the IC to be tested based on the test time sequence waveform, and sending the time sequence waveform to be tested to the time sequence processing module.
The application provides an IC timing sequence verification method and device, a user can send different waveform generation instructions to a processing device according to different types of ICs to be tested and user requirements, the processing device generates test timing sequence waveforms corresponding to the waveform generation instructions, namely, the corresponding test timing sequence waveforms can be generated according to the different types of the ICs to be tested and the different requirements of the user, and then whether the timing sequence waveforms to be tested generated by the ICs to be tested based on the test timing sequence waveforms are the same as expected timing sequence waveforms is judged so as to judge whether the ICs to be tested meet the design requirements of the user. Because the processing device is not limited by a circuit structure when generating the test time sequence waveform, the processing device can generate any type of test time sequence waveform to meet different inspection requirements, when a research and development designer researches a new IC to be tested, the processing device can directly generate the test time sequence waveform corresponding to the IC to be tested to test the IC to be tested, a matched detection device corresponding to the IC to be tested does not need to be developed, and the efficiency of verifying the IC to be tested is improved.
The application also provides an IC time sequence verification device, which has the same beneficial effects as the IC time sequence verification method described above.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed in the prior art and the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
FIG. 1 is a schematic flow chart of a method for verifying IC timing sequence according to the present invention;
FIG. 2 is a block diagram of an IC timing verification apparatus according to the present invention;
FIG. 3 is a block diagram of another IC timing verification apparatus according to the present invention.
Detailed Description
The core of the invention is to provide an IC timing sequence verification method and device, which can generate any test timing sequence waveform to meet the inspection requirements of different ICs to be tested, and can directly generate the test timing sequence waveform corresponding to the ICs to be tested to test the ICs to be tested when a research and development designer develops a new IC to be tested, without developing a matched detection device corresponding to the ICs to be tested, thereby improving the efficiency of verifying the ICs to be tested.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a schematic flow chart of an IC timing verification method according to the present invention, the method applied to a processing apparatus, including:
s11: receiving a waveform generation instruction sent by a user based on the type of an IC to be tested and the user requirement;
considering that the types of ICs to be tested are many, and the test timing waveforms required by the same type of ICs to be tested are different, if the IC to be tested is detected by using the IC detection method in the prior art, multiple types of detection devices need to be adaptively developed, and especially when research and development personnel research and develop a new IC to be tested, the corresponding detection device needs to be developed to verify the IC to be tested, but the detection device needs a certain research and development time to affect the verification of the IC to be tested, thereby affecting the verification efficiency of the IC to be tested.
In order to solve the technical problem, a processing device is developed in the application, which can generate different test timing waveforms according to a user instruction so as to adapt to various user requirements and different types of ICs to be tested, wherein the waveform generation instruction is a waveform generation instruction generated according to the type of the IC to be tested and the user requirement by the user, and then the processing device can generate any test timing waveforms corresponding to the type of the IC to be tested and the user requirements, so that various detection devices do not need to be designed and developed, and the speed of verifying the IC to be tested is improved.
It should be noted that, in the present application, the waveform generation instruction may be data information corresponding to the test timing waveform, or may also be mark information corresponding to the stored test timing waveform, and when the waveform generation instruction received by the processing device is data information, the corresponding test timing waveform may be directly generated according to the data information to detect the IC to be tested; when the detection information received by the processing device is the mark information, the processing device directly calls the stored test time sequence data corresponding to the test time sequence waveform according to the mark information, further generates the corresponding test time sequence waveform according to the test time sequence data, and sends the test time sequence waveform to the IC to be tested.
Of course, the specific implementation of the waveform generation instruction is not limited to the above example, and other implementations are possible, and the present application is not limited thereto.
S12: generating a test time sequence waveform corresponding to the type of the IC to be tested and the user requirement based on the waveform generation instruction, and sending the test time sequence waveform to the IC to be tested;
specifically, after receiving the waveform generation instruction, the processing device in the application generates a test timing waveform corresponding to the waveform generation instruction, and since the waveform generation instruction corresponds to the type and the user requirement of the IC to be tested, the test timing waveform corresponds to the type and the user requirement of the IC to be tested, so as to verify the corresponding IC to be tested.
It should be noted that the test time-series waveform generated based on the waveform generation instruction in the present application may be a new time-series waveform, or may also be a time-series waveform generated by calling time-series data corresponding to the time-series waveform that has been stored originally.
S13: sampling a time sequence waveform to be tested generated by the IC to be tested based on the test time sequence waveform;
s14: judging whether the time sequence waveform to be detected is the same as the expected time sequence waveform;
s15: if so, judging that the IC to be tested meets the design requirement of the user;
s16: if not, judging that the IC to be tested does not meet the design requirements of the user.
Specifically, after the test timing waveform is sent to the IC to be tested, the IC to be tested generates a test timing waveform based on the test timing waveform according to its own circuit structure, software program, etc., when the IC under test meets the design requirements of the user, the timing waveform under test and the expected timing waveform should be the same, when the IC to be tested does not meet the design requirement of the user, the IC to be tested is different from the expected time sequence waveform, therefore, after the IC to be tested generates the time sequence waveform to be tested, sampling the time sequence waveform to be tested, comparing the time sequence waveform to be tested with the expected time sequence waveform, judging whether the time sequence waveform is the same as the expected time sequence waveform, if so, judging that the IC to be tested meets the design requirement of the user, if not, judging that the IC to be tested does not meet the design requirement of the user, so that the user can design and modify the IC to be tested which does not meet the design requirement of the user in time.
As a preferred embodiment, the method for determining whether the time-series waveform to be measured is the same as the expected time-series waveform is not limited to determining whether the time-series waveform to be measured is the same as the expected time-series waveform according to the type, frequency and/or high-low level logic of the time-series waveform to be measured and the expected time-series waveform, and of course, other determination methods may be used.
In addition, the processing device can also generate an analysis report according to the judgment result, then store the analysis report in the memory, and mark the analysis report, wherein the mark corresponds to the IC to be tested, so that the user can inquire the analysis report later. Of course, the analysis report may not be limited to be directly sent to the user, and the application is not particularly limited herein.
In summary, since the processing device is not limited by the circuit structure when generating the test timing waveforms, any test timing waveforms can be generated to meet the inspection requirements of different ICs to be tested, and when a research and development designer develops a new IC to be tested, the test timing waveforms corresponding to the IC to be tested can be directly generated to test the IC to be tested, so that a matched detection device corresponding to the IC to be tested does not need to be developed, and the efficiency of verifying the IC to be tested is improved.
On the basis of the above-described embodiment:
as a preferred embodiment, generating a test timing waveform corresponding to an IC to be tested based on a waveform generation instruction, and transmitting the test timing waveform to the IC to be tested, includes:
reading test time sequence data which is stored in a memory and corresponds to the type of the IC to be tested and user requirements based on a waveform generation instruction, and generating a corresponding test time sequence waveform based on the test time sequence data;
and sending the test time sequence waveform generated based on the test time sequence data to the IC to be tested.
Considering that the IC to be tested is a certain IC to be tested which has been detected once and the user requirement is a certain requirement which has been tested once, if the type of IC to be tested or the user requirement is detected originally, the test timing data corresponding to the corresponding test timing waveform may be stored in the memory, and when the type of IC to be tested or the user requirement is detected again, the test timing data corresponding to the type of IC to be tested and the user requirement which have been stored in the memory may be directly used to generate the corresponding test timing waveform.
It should be noted that, when a new IC to be tested and a user's requirement are detected, the test timing data corresponding to the test timing waveform may be marked, where the mark corresponds to the type of the IC to be tested, and then the test timing data with the mark is stored in the memory. That is, the test timing data of the test timing waveform generated by the processing device may be stored in the memory using the storage function, and the test timing data stored in the memory may be reloaded into the processing device to generate the corresponding test timing waveform for the processing device to use.
In summary, the specific implementation manner in this embodiment is an implementation manner of generating a test timing waveform, which can implement the function of generating the test timing waveform, and the implementation manner is simple and reliable, and by storing data corresponding to the waveform, the waveform does not need to be repeatedly generated, thereby improving the verification efficiency.
As a preferred embodiment, the waveform generation instruction includes data information corresponding to a desired timing waveform;
generating a test timing waveform corresponding to the type of the IC to be tested and the user requirement based on the waveform generation instruction, comprising:
and generating a test time sequence waveform corresponding to the type of the IC to be tested and the user requirement based on the data information.
Consider that the IC under test is a new type of IC under test that has not been tested or the user requirement is a user requirement that has not been tested. At this time, the waveform generation instruction includes data information corresponding to the expected timing waveform, the data information is corresponding data information generated by a user according to the expected timing waveform and the circuit structure of the IC to be tested, and the processing device may generate a corresponding test timing waveform based on the data information, so as to implement the detection of the IC to be tested.
As a preferred embodiment, after generating a test timing waveform corresponding to the type of the IC to be tested and the user requirement and sending the test timing waveform to the IC to be tested, the method further includes:
and marking the test time sequence data corresponding to the test time sequence waveform and storing the test time sequence data in the memory.
After generating a test timing waveform corresponding to a new type of an IC to be tested and a user requirement, the test timing data corresponding to the test timing waveform may be stored in the memory, so that when the user requirement or the type of the IC to be tested is detected next time, the test timing data corresponding to the type of the IC to be tested and the user requirement, which is stored in the memory, is directly used to generate the corresponding test timing waveform without generating the test timing waveform again, thereby improving the verification efficiency. In addition, when storing the test time sequence data, the test time sequence data needs to be marked, the mark corresponds to the type of the IC to be tested and the user requirement, and then the test time sequence data with the mark is stored to the processing device. That is, the test timing data corresponding to the test timing waveform generated by the processing device may be stored in the memory using the storage function, and the test timing data stored in the memory may also be reloaded into the processing device, so as to generate the corresponding test timing waveform for the processing device to use.
In summary, the specific implementation manner in this embodiment is another implementation manner for generating the test timing waveform, which can implement the function of generating the test timing waveform, and the implementation manner is simple and reliable, and by storing the waveform, the waveform does not need to be repeatedly generated, thereby improving the verification efficiency.
As a preferred embodiment, sampling a timing waveform to be tested generated by an IC to be tested based on a test timing waveform includes:
after receiving the trigger signal, starting to sample the time sequence waveform to be detected at a preset sampling frequency;
judging whether the sampling number reaches a preset sampling number or not;
if yes, stopping sampling, and judging whether the time sequence waveform to be detected is the same as the expected time sequence waveform.
The specific implementation of sampling the waveform is as follows: the method comprises the steps of setting a processing device to be in a sampling mode, then selecting an IO port where an IC to be tested is connected with the processing device, setting a preset sampling frequency and a preset sampling number, starting to sample the time sequence waveform to be tested by the processing device with the preset sampling frequency, and controlling the processing device to stop sampling when the sampling number reaches the preset sampling number, so that sampling of the time sequence waveform to be tested is completed.
Of course, the condition for controlling the processing device to stop sampling is not limited to determining whether the number of samples reaches the number of samples, and may be determining whether the sampling time reaches the preset sampling time, and if so, controlling the processing device to stop sampling.
Therefore, the sampling of the time sequence waveform to be detected can be realized through the sampling mode, the realization mode is simple, and the control mode of the sampling is simpler.
As a preferred embodiment, after sampling the timing waveform to be tested generated by the IC to be tested based on the test timing waveform, the method further includes:
and sending the time sequence waveform to be detected to a display device to display the time sequence waveform to be detected.
For the convenience of the user to observe, in the present application, after the time-series waveform to be detected is detected, the time-series waveform to be detected is sent to the display device to be displayed, where the display device may be, but is not limited to, a display screen of a computer, and may also be other display devices, and the present application is not particularly limited herein.
As a preferred embodiment, after sampling the timing waveform to be tested generated by the IC to be tested based on the test timing waveform, the method further includes:
and sending the time sequence waveform to be tested to an editing device so that a user edits the time sequence waveform to be tested through the editing device according to the time sequence waveform to be tested displayed on the display device to generate a test time sequence waveform meeting the preset requirement of the user.
Considering that the types of some to-be-tested ICs and the logic and frequency differences between the test time sequence waveforms corresponding to the user requirements are not much, only the user needs to finely adjust the to-be-tested time sequence waveforms, so that the processing device in the application also sends the to-be-tested time sequence waveforms to the editing device, and the user can edit the to-be-tested time sequence waveforms conveniently.
The waveform editing is not limited to modifying the duty ratio, frequency, logic positive and negative, etc. of the time sequence waveform to be measured, or splicing or cutting the time sequence waveform to generate a new time sequence waveform, or adding noise data to the previous time sequence waveform, and the application is not limited in particular.
Referring to fig. 2, fig. 2 is a block diagram of an IC timing verification apparatus according to the present invention, the apparatus includes:
a memory 21 for storing a computer program;
the processing device 22 is configured to implement the steps of the IC timing verification method when executing the computer program.
Referring to fig. 3, fig. 3 is a block diagram of another IC timing verification apparatus according to the present invention.
As a preferred embodiment, the processing device includes a timing processing module 31 and a timing hardware module 32 connected to the timing processing module 31;
the timing sequence processing module 31 is configured to receive a waveform generation instruction sent by a user based on the type of the IC to be tested and a user requirement; judging whether the time sequence waveform to be detected is the same as the expected time sequence waveform or not according to the time sequence waveform to be detected, if so, judging that the IC to be detected meets the design requirement of a user, and if not, judging that the IC to be detected does not meet the design requirement of the user;
the timing hardware module 32 is configured to generate a test timing waveform corresponding to the type of the IC to be tested and the user requirement based on the waveform generation instruction, send the test timing waveform to the IC to be tested, sample the test timing waveform generated by the IC to be tested based on the test timing waveform, and send the test timing waveform to the timing processing module 31.
The processing device 22 in the present application may include, but is not limited to, a timing processing module 31 and a timing hardware module 32, where the timing processing module 31 may have, but is not limited to, functions of waveform acquisition, waveform display, waveform editing, waveform storage, waveform analysis, and the like, and the timing processing module may be, but is not limited to, a computer. The timing processing module 31 and the timing processing device can communicate with each other through, but not limited to, a communication module. The waveform editing function in the time sequence processing module 31 may generate time sequence waveform data, may modify duty ratio, frequency, logic positive and negative, and the like of the time sequence waveform in the data, and also support adding noise data to the time sequence waveform data, or performing data splicing or clipping on the time sequence waveform. The time-series waveform data in the time-series processing module 31 may be stored using a waveform storage function, and the stored time-series waveform data may be reloaded into the time-series processing module 31. The time sequence processing device generates a corresponding time sequence waveform according to the data after receiving the time sequence processing data. The timing waveform of the IC to be tested collected by the timing processing device is transmitted to the timing processing module 31, and the timing processing module 31 analyzes the timing waveform data to generate a report. Specifically, the timing processing module 31 supports timing type analysis, frequency calculation, logic assertion (high-low level determination), and the like on the timing waveform of the IC to be tested. The timing processing module 31 may edit the acquired timing waveform and is used to generate the timing waveform. The time-series waveform data can be presented in a waveform mode in a graphical interface so that a user can edit and analyze the time-series waveform data, and the user can configure the IO position of each waveform data in the time-series processing device through the graphical interface.
The timing hardware module 32 includes a timing waveform generating module, a timing waveform collecting module, a memory, an IO MUX (Multiplexer) module, and the like. Specifically, the timing hardware module 32 loads waveform data in the timing processing module 31 to a Memory through a communication module, or sends the timing waveform data in the Memory to the timing processing module 31, the timing hardware module 32 may, but is not limited to, accelerate transmission of data inside the timing processing device through an internal bus of an HPS-FPGA (Hard Processor System-Field-Programmable Gate Array, high performance server-Programmable Gate Array), wherein the timing waveform generating module is configured to generate a timing waveform, the waveform acquiring module is configured to acquire a timing waveform of an IC to be tested, and may also support returning of the timing waveform generated by the waveform generating module, the acquired timing waveform data may, but is not limited to, be stored in the Memory, the Memory may, but is not limited to, a RAM (Random-Access Memory) storage medium, and the Memory is configured to, in addition to storing a computer program, but also for storing all the time series data mentioned above. And the IO MUX module is responsible for configuring an IO port connected to the IC time sequence interface to be tested.
For other descriptions of the IC timing verification apparatus provided in the present application, refer to the above embodiments, which are not repeated herein.
It is to be noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. An IC timing verification method applied to a processing device includes:
receiving a waveform generation instruction sent by a user based on the type of an IC to be tested and the user requirement;
generating a test time sequence waveform corresponding to the type of the IC to be tested and the user requirement based on the waveform generation instruction, and sending the test time sequence waveform to the IC to be tested;
sampling a time sequence waveform to be tested generated by the IC to be tested based on the test time sequence waveform;
judging whether the time sequence waveform to be detected is the same as the expected time sequence waveform;
if so, judging that the IC to be tested meets the design requirement of the user;
if not, judging that the IC to be tested does not meet the design requirements of the user.
2. The IC timing verification method of claim 1, wherein determining whether the timing waveform under test is the same as the expected timing waveform comprises:
and judging whether the time sequence waveform to be detected is the same as the expected time sequence waveform or not according to the type and/or frequency and/or high-low level logic of the time sequence waveform to be detected.
3. The IC timing verification method of claim 1, wherein generating a corresponding test timing waveform based on the waveform generation instruction and sending the test timing waveform to the IC under test comprises:
reading test time sequence data which is stored in a memory and corresponds to the type of the IC to be tested and user requirements based on the waveform generation instruction, and generating a corresponding test time sequence waveform based on the test time sequence data;
and sending the test time sequence waveform generated based on the test time sequence data to the IC to be tested.
4. The IC timing verification method of claim 1, wherein the waveform generation instruction includes data information corresponding to the desired timing waveform;
generating a test timing waveform corresponding to the IC to be tested based on the waveform generation instruction, including:
and generating a test time sequence waveform corresponding to the type of the IC to be tested and the user requirement based on the data information.
5. The IC timing verification method of claim 1, wherein after generating a test timing waveform corresponding to the type of the IC under test and a user requirement and sending the test timing waveform to the IC under test, further comprising:
and marking the test time sequence data corresponding to the test time sequence waveform and storing the test time sequence data in a memory.
6. The IC timing verification method of claim 1, wherein sampling a timing waveform under test generated by the IC under test based on the timing waveform under test comprises:
after receiving the trigger signal, starting to sample the time sequence waveform to be detected at a preset sampling frequency;
judging whether the sampling number reaches a preset sampling number or not;
if so, stopping sampling, and judging whether the time sequence waveform to be detected is the same as the expected time sequence waveform.
7. The IC timing verification method of claim 1, wherein after sampling a timing waveform to be tested generated by the IC to be tested based on the timing waveform to be tested, further comprising:
and sending the time sequence waveform to be detected to a display device to display the time sequence waveform to be detected.
8. The IC timing verification method of claim 7, wherein after sampling a timing waveform to be tested generated by the IC to be tested based on the test timing waveform, further comprising:
and sending the time sequence waveform to be tested to an editing device so that a user edits the time sequence waveform to be tested through the editing device according to the time sequence waveform to be tested displayed on the display device to generate a test time sequence waveform meeting the preset requirement of the user.
9. An IC timing verification apparatus, comprising:
a memory for storing a computer program;
processing means for implementing the steps of the IC timing verification method according to any one of claims 1 to 8 when executing said computer program.
10. The IC timing verification apparatus of claim 9, wherein the processing apparatus comprises a timing processing module and a timing hardware module connected to the timing processing module;
the time sequence processing module is used for receiving a waveform generation instruction sent by a user based on the type of the IC to be tested and the user requirement; judging whether the time sequence waveform to be detected is the same as the expected time sequence waveform or not according to the time sequence waveform to be detected, if so, judging that the IC to be detected meets the design requirement of a user, and if not, judging that the IC to be detected does not meet the design requirement of the user;
the time sequence hardware module is used for generating a test time sequence waveform corresponding to the type of the IC to be tested and the user requirement based on the waveform generation instruction, sending the test time sequence waveform to the IC to be tested, sampling the time sequence waveform to be tested generated by the IC to be tested based on the test time sequence waveform, and sending the time sequence waveform to be tested to the time sequence processing module.
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