CN202025308U - Computer and automatic boot circuit thereof - Google Patents
Computer and automatic boot circuit thereof Download PDFInfo
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- CN202025308U CN202025308U CN2011200526273U CN201120052627U CN202025308U CN 202025308 U CN202025308 U CN 202025308U CN 2011200526273 U CN2011200526273 U CN 2011200526273U CN 201120052627 U CN201120052627 U CN 201120052627U CN 202025308 U CN202025308 U CN 202025308U
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Abstract
The utility model is applicable to the field of computers and provides a computer and an automatic boot circuit thereof. The automatic boot circuit of the computer comprises a detecting unit and an automatic boot triggering unit. In the embodiment of the utility model, the detecting unit detects whether the voltage of a battery is lower than a set triggering voltage value, if so, outputs a detecting signal to the automatic boot triggering unit; and the automatic boot triggering unit outputs a boot triggering signal to a super input/output chip, so that the super input/output chip outputs an electrifying boot signal, further the computer is electrified and booted, and when the electric quantity of the battery of a main board of the computer is too low, the computer also can be automatically and normally electrified and booted.
Description
Technical field
The utility model belongs to computer realm, relates in particular to a kind of computing machine and automatic boot circuit thereof.
Background technology
Be operated under the unmanned situation of intervening if be fit into the mainboard of computing machine complete machine, run into AC Power Failure and cause the mainboard accident power-off, when power up normally needs mainboard to finish automatically normally to power on the start operation often.
But, cause mainboard button cell electric weight to cross low and the value of setting that can not normally preserve the register of South Bridge chip and super I/O chip when the mainboard working time that is fit into complete machine than long or other situation, when running into AC Power Failure once more, mainboard can not be finished the start operation that normally powers on automatically.Now, common solution is to change the button cell of mainboard, is a loaded down with trivial details operation but disassemble cabinet replacing mainboard button cell, especially under the situation through reinforcing installation or dismounting inconvenience.
The utility model content
Fundamental purpose of the present utility model is to provide a kind of computing machine automatic boot circuit, and it is low excessively to be intended to solve the present mainboard button cell electric weight of working as, and there is problem that can not finish the start operation that normally powers on automatically in mainboard.
The utility model is to realize like this, a kind of computing machine automatic boot circuit, described computing machine automatic boot circuit comprises South Bridge chip, super I/O chip, power supply unit that links to each other successively and the battery that is connected with described South Bridge chip, and described computing machine automatic boot circuit also comprises:
Be connected with battery with described super I/O chip respectively, whether the voltage that detects battery is lower than the setting trigger voltage value, if be lower than, and the detecting unit of output detection signal; And
Be connected with detecting unit with described super I/O chip respectively, according to detection signal, output start trigger pip is given described super I/O chip, makes the described super I/O chip output starting-up signal that powers on, and makes the power on Auto Power On trigger element of start of computing machine.
In the said structure, described detecting unit comprises:
Power management chip U1, divider resistance R1, divider resistance R2, pull-up resistor R3 and PMOS pipe Q1;
The test side SENSE of described power management chip U1 connects battery by divider resistance R1, the test side SENSE of described power management chip U1 is by divider resistance R2 ground connection, the output terminal RESET# of described power management chip U1 connects the grid of PMOS pipe Q1, the drain electrode of described PMOS pipe Q1 meets the reset signal end RSMRST of super I/O chip, the source electrode of described PMOS pipe Q1 connects the Auto Power On trigger element, and the grid of described PMOS pipe Q1 also connects power supply by pull-up resistor R3.
In the said structure, described Auto Power On trigger element comprises:
NMOS pipe Q2, capacitor C 1, resistance R 4 and resistance R 5;
The grid of described NMOS pipe Q2 connects the source electrode of PMOS pipe Q1 by capacitor C 1, the grid of described NMOS pipe Q2 is also by resistance R 4 ground connection, the source ground of described NMOS pipe Q2, the drain electrode of described NMOS pipe Q2 meets the start trigger pip end FP_PWRBTN# of super I/O chip, the start trigger pip end FP_PWRBTN# of the super I/O chip of first termination of described resistance R 5, second termination power of described resistance R 5.
Another purpose of the present utility model is to provide a kind of computing machine, described computing machine comprises the computing machine automatic boot circuit, described computing machine automatic boot circuit comprises South Bridge chip, super I/O chip, power supply unit that links to each other successively and the battery that is connected with described South Bridge chip, and described computing machine automatic boot circuit also comprises:
Be connected with battery with described super I/O chip respectively, whether the voltage that detects battery is lower than the setting trigger voltage value, if be lower than, and the detecting unit of output detection signal; And
Be connected with detecting unit with described super I/O chip respectively, according to detection signal, output start trigger pip is given described super I/O chip, makes the described super I/O chip output starting-up signal that powers on, and makes the power on Auto Power On trigger element of start of computing machine.
In the said structure, described detecting unit comprises:
Power management chip U1, divider resistance R1, divider resistance R2, pull-up resistor R3 and PMOS pipe Q1;
The test side SENSE of described power management chip U1 connects battery by divider resistance R1, the test side SENSE of described power management chip U1 is by divider resistance R2 ground connection, the output terminal RESET# of described power management chip U1 connects the grid of PMOS pipe Q1, the drain electrode of described PMOS pipe Q1 meets the reset signal end RSMRST of super I/O chip, the source electrode of described PMOS pipe Q1 connects the Auto Power On trigger element, and the grid of described PMOS pipe Q1 also connects power supply by pull-up resistor R3.
In the said structure, described Auto Power On trigger element comprises:
NMOS pipe Q2, capacitor C 1, resistance R 4 and resistance R 5;
The grid of described NMOS pipe Q2 connects the source electrode of PMOS pipe Q1 by capacitor C 1, the grid of described NMOS pipe Q2 is also by resistance R 4 ground connection, the source ground of described NMOS pipe Q2, the drain electrode of described NMOS pipe Q2 meets the start trigger pip end FP_PWRBTN# of super I/O chip, the start trigger pip end FP_PWRBTN# of the super I/O chip of first termination of described resistance R 5, second termination power of described resistance R 5.
In the utility model, the computing machine automatic boot circuit comprises detecting unit and Auto Power On trigger element, the voltage that detecting unit detects battery is lower than the setting trigger voltage value, output detection signal is given the Auto Power On trigger element, Auto Power On trigger element output start trigger pip is given super I/O chip, makes the super I/O chip output starting-up signal that powers on, and makes the computing machine start that powers on, make computing machine cross when low at the mainboard battery electric quantity, start automatically also can normally power on.
Description of drawings
Fig. 1 is the module map of the computing machine automatic boot circuit that provides of the utility model embodiment;
Fig. 2 is the exemplary circuit figure of the computing machine automatic boot circuit that provides of the utility model embodiment;
Fig. 3 is reset signal end RSMRST#, the NMOS pipe that provides of the utility model embodiment and the voltage sequential chart of start trigger pip end FP_PWRBTN#.
Embodiment
In order to make the purpose of this utility model, principle and advantage clearer,, the utility model is further elaborated below in conjunction with drawings and Examples.Should be appreciated that specific embodiment described herein only in order to explanation the utility model, and be not used in qualification the utility model.
Fig. 1 shows the modular structure of the computing machine automatic boot circuit that the utility model embodiment provides, and for convenience of explanation, only shows the part relevant with the utility model embodiment, and details are as follows.
The computing machine automatic boot circuit comprises South Bridge chip 100, super I/O chip 200, power supply unit 300 that links to each other successively and the battery BAT that is connected with South Bridge chip 100, power supply unit 300 also is connected with super I/O chip 200 with South Bridge chip 100 respectively, be South Bridge chip 100 and 200 power supplies of super I/O chip, the computing machine automatic boot circuit also comprises detecting unit 400 and Auto Power On trigger element 500.
Detecting unit 400 is connected with battery BAT with super I/O chip 200 respectively, and whether the voltage that detects battery BAT is lower than the setting trigger voltage value, if be lower than, and output detection signal;
Auto Power On trigger element 500 is connected with detecting unit 400 with super I/O chip 200 respectively, according to detection signal, output start trigger pip is given super I/O chip 200, makes the super I/O chip 200 outputs starting-up signal that powers on, and makes the computing machine start that powers on.
Fig. 2 shows the exemplary circuit structure of the computing machine automatic boot circuit that the utility model embodiment provides, and for convenience of explanation, only shows the part relevant with the utility model embodiment, and details are as follows.
The power managing signal end SLP_SX of South Bridge chip 100, trigger pip end ICH_PWRBTN#, reset signal end RSMRST# are connected with power managing signal end SLP_SX, trigger pip end ICH_PWRBTN#, the reset signal end RSMRST# of super I/O chip 200 respectively, the starting-up signal end PS_ON# that powers on of super I/O chip 200 connects power supply unit 300, and the start trigger pip end FP_PWRBTN# of super I/O chip 200 connects Auto Power On trigger element 500.
As the utility model one embodiment, detecting unit 400 comprises:
Power management chip U1, divider resistance R1, divider resistance R2, pull-up resistor R3 and PMOS pipe Q1;
The power end VDD of power management chip U1 connects power supply, the ground end GND ground connection of power management chip U1, the test side SENSE of power management chip U1 meets battery BAT by divider resistance R1, the test side SENSE of power management chip U1 is by divider resistance R2 ground connection, the output terminal RESET# of power management chip U1 connects the grid of PMOS pipe Q1, the source electrode of PMOS pipe Q1 meets the reset signal end RSMRST# of super I/O chip 200, the drain electrode of PMOS pipe Q1 connects Auto Power On trigger element 500, and the grid of PMOS pipe Q1 also connects power supply by pull-up resistor R3.
As the utility model one embodiment, Auto Power On trigger element 500 comprises:
NMOS pipe Q2, capacitor C 1, resistance R 4 and resistance R 5;
The grid of NMOS pipe Q2 connects the drain electrode of PMOS pipe Q1 by capacitor C 1, the grid of NMOS pipe Q2 is also by resistance R 4 ground connection, the source ground of NMOS pipe Q2, the drain electrode of NMOS pipe Q2 meets the start trigger pip end FP_PWRBTN# of super I/O chip 200, the start trigger pip end FP_PWRBTN# of the super I/O chip 200 of first termination of resistance R 5, second termination power of resistance R 5.
The principle of work of computing machine automatic boot circuit is:
When computing machine powers on, the reset signal end RSMRST# output of super I/O chip 200 is uprised the RSMRST# reset signal of level by low level, when the voltage of mainboard battery BAT just often, the loop of detecting unit 400 automatic cutout Auto Power On trigger elements 500, Auto Power On trigger element 500 quits work, and computing machine powers on to start shooting and moves by preset value;
When the voltage of mainboard battery BAT is lower than the setting trigger voltage value, the power management chip U1 output control signal control PMOS pipe Q1 conducting of detecting unit 400, make the input end of Auto Power On trigger element 500 and the reset signal end RSMRST# of super I/O chip 200 connect, when the RSMRST# reset signal becomes high level by low level, the conducting of NMOS pipe Q2 source-drain electrode, this moment, the start trigger pip end FP_PWRBTN# of super I/O chip 200 was a low level, super I/O chip 200 output ICH_PWRBTN# trigger pips, trigger South Bridge chip 100 and carry out boot action, trigger South Bridge chip 100 output SLP_SX power managing signal and give super I/O chip 200, super I/O chip 200 output PS_ON# power on signal make the computing machine start that powers on.The RSMRST# reset signal is uprised in the level process by low level, because the influence of resistance R 4, the curved as shown in Figure 3 slow decline of waveform during capacitor C 1 charging, when the voltage of capacitor C 1 one ends arrives the T point, just the threshold voltage Vth with NMOS pipe Q2 equates, this end of capacitor C 1 links to each other with the grid of NMOS pipe Q2, therefore during from P during to K the magnitude of voltage of this section in the time all to be higher than the threshold voltage Vth of NMOS pipe Q2, NMOS pipe Q2 during this period of time is conducting, and the start trigger pip end FP_PWRBTN# of super I/O chip 200 is a ground connection.
The utility model embodiment also provides a kind of computing machine that comprises above-mentioned automatic boot circuit.
In the utility model embodiment, the computing machine automatic boot circuit comprises detecting unit and Auto Power On trigger element, the voltage that detecting unit detects battery is lower than the setting trigger voltage value, output detection signal is given the Auto Power On trigger element, Auto Power On trigger element output start trigger pip is given super I/O chip, make super I/O chip export the starting-up signal that powers on, make the computing machine start that powers on, make computing machine cross when low at the mainboard battery electric quantity, start automatically also can normally power on.
The above only is preferred embodiment of the present utility model; not in order to restriction the utility model; all any modifications of within spirit of the present utility model and principle, being done, be equal to and replace and improvement etc., all should be included within the protection domain of the present utility model.
Claims (6)
1. computing machine automatic boot circuit, described computing machine automatic boot circuit comprises South Bridge chip, super I/O chip, power supply unit that links to each other successively and the battery that is connected with described South Bridge chip, it is characterized in that described computing machine automatic boot circuit also comprises:
Be connected with battery with described super I/O chip respectively, whether the voltage that detects battery is lower than the setting trigger voltage value, if be lower than, and the detecting unit of output detection signal; And
Be connected with detecting unit with described super I/O chip respectively, according to detection signal, output start trigger pip is given described super I/O chip, makes the described super I/O chip output starting-up signal that powers on, and makes the power on Auto Power On trigger element of start of computing machine.
2. computing machine automatic boot circuit as claimed in claim 1 is characterized in that, described detecting unit comprises:
Power management chip U1, divider resistance R1, divider resistance R2, pull-up resistor R3 and PMOS pipe Q1;
The test side SENSE of described power management chip U1 connects battery by divider resistance R1, the test side SENSE of described power management chip U1 is by divider resistance R2 ground connection, the output terminal RESET# of described power management chip U1 connects the grid of PMOS pipe Q1, the source electrode of described PMOS pipe Q1 meets the reset signal end RSMRST# of super I/O chip, the drain electrode of described PMOS pipe Q1 connects the Auto Power On trigger element, and the grid of described PMOS pipe Q1 also connects power supply by pull-up resistor R3.
3. computing machine automatic boot circuit as claimed in claim 2 is characterized in that, described Auto Power On trigger element comprises:
NMOS pipe Q2, capacitor C 1, resistance R 4 and resistance R 5;
The grid of described NMOS pipe Q2 connects the drain electrode of PMOS pipe Q1 by capacitor C 1, the grid of described NMOS pipe Q2 is also by resistance R 4 ground connection, the source ground of described NMOS pipe Q2, the drain electrode of described NMOS pipe Q2 meets the start trigger pip end FP_PWRBTN# of super I/O chip, the start trigger pip end FP_PWRBTN# of the super I/O chip of first termination of described resistance R 5, second termination power of described resistance R 5.
4. computing machine, it is characterized in that, described computing machine comprises the computing machine automatic boot circuit, described computing machine automatic boot circuit comprises South Bridge chip, super I/O chip, power supply unit that links to each other successively and the battery that is connected with described South Bridge chip, and described computing machine automatic boot circuit also comprises:
Be connected with battery with described super I/O chip respectively, whether the voltage that detects battery is lower than the setting trigger voltage value, if be lower than, and the detecting unit of output detection signal; And
Be connected with detecting unit with described super I/O chip respectively, according to detection signal, output start trigger pip is given described super I/O chip, makes the described super I/O chip output starting-up signal that powers on, and makes the power on Auto Power On trigger element of start of computing machine.
5. computing machine as claimed in claim 4 is characterized in that, described detecting unit comprises:
Power management chip U1, divider resistance R1, divider resistance R2, pull-up resistor R3 and PMOS pipe Q1;
The test side SENSE of described power management chip U1 connects battery by divider resistance R1, the test side SENSE of described power management chip U1 is by divider resistance R2 ground connection, the output terminal RESET# of described power management chip U1 connects the grid of PMOS pipe Q1, the source electrode of described PMOS pipe Q1 meets the reset signal end RSMRST# of super I/O chip, the drain electrode of described PMOS pipe Q1 connects the Auto Power On trigger element, and the grid of described PMOS pipe Q1 also connects power supply by pull-up resistor R3.
6. computing machine as claimed in claim 5 is characterized in that, described Auto Power On trigger element comprises: NMOS pipe Q2, capacitor C 1, resistance R 4 and resistance R 5;
The grid of described NMOS pipe Q2 connects the drain electrode of PMOS pipe Q1 by capacitor C 1, the grid of described NMOS pipe Q2 is also by resistance R 4 ground connection, the source ground of described NMOS pipe Q2, the drain electrode of described NMOS pipe Q2 meets the start trigger pip end FP_PWRBTN# of super I/O chip, the start trigger pip end FP_PWRBTN# of the super I/O chip of first termination of described resistance R 5, second termination power of described resistance R 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011200526273U CN202025308U (en) | 2011-03-02 | 2011-03-02 | Computer and automatic boot circuit thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011200526273U CN202025308U (en) | 2011-03-02 | 2011-03-02 | Computer and automatic boot circuit thereof |
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| Publication Number | Publication Date |
|---|---|
| CN202025308U true CN202025308U (en) | 2011-11-02 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2011200526273U Expired - Lifetime CN202025308U (en) | 2011-03-02 | 2011-03-02 | Computer and automatic boot circuit thereof |
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| CN (1) | CN202025308U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103713912A (en) * | 2012-09-29 | 2014-04-09 | 深圳市祈飞科技有限公司 | Automatic power on circuit of computer |
| CN104407668A (en) * | 2014-10-29 | 2015-03-11 | 大唐移动通信设备有限公司 | Board card for controlling automatic electrification of board card based on X86 system architecture |
-
2011
- 2011-03-02 CN CN2011200526273U patent/CN202025308U/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103713912A (en) * | 2012-09-29 | 2014-04-09 | 深圳市祈飞科技有限公司 | Automatic power on circuit of computer |
| CN103713912B (en) * | 2012-09-29 | 2017-11-24 | 深圳市祈飞科技有限公司 | A kind of computer automatic boot circuit |
| CN104407668A (en) * | 2014-10-29 | 2015-03-11 | 大唐移动通信设备有限公司 | Board card for controlling automatic electrification of board card based on X86 system architecture |
| CN104407668B (en) * | 2014-10-29 | 2017-07-28 | 大唐移动通信设备有限公司 | It is a kind of to control the upper electric board automatically of the board based on X86 system architectures |
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Legal Events
| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
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| CX01 | Expiry of patent term |
Granted publication date: 20111102 |