CN108964648A - A kind of time sequence control device and method - Google Patents
A kind of time sequence control device and method Download PDFInfo
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- CN108964648A CN108964648A CN201810837174.1A CN201810837174A CN108964648A CN 108964648 A CN108964648 A CN 108964648A CN 201810837174 A CN201810837174 A CN 201810837174A CN 108964648 A CN108964648 A CN 108964648A
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- 238000000034 method Methods 0.000 title claims description 14
- 238000002955 isolation Methods 0.000 claims abstract description 49
- 230000005669 field effect Effects 0.000 claims abstract description 26
- 230000005540 biological transmission Effects 0.000 claims description 6
- 230000005611 electricity Effects 0.000 claims description 6
- 108010076504 Protein Sorting Signals Proteins 0.000 description 6
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/266—Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
Abstract
The embodiment of the present application discloses a kind of time sequence control device, and time sequence control device includes the first chip, the second chip and enabled isolation module；Enabled isolation module includes the first pull-up resistor, the second pull-up resistor, the first field-effect tube MOS and the second field-effect tube MOS；The power supply status PG signal output end of first chip is extremely connected with the grid G of the first MOS；One end of first pull-up resistor, the 2nd MOS the pole G be extremely connected with the drain D of the first MOS respectively；The pole D of 2nd MOS is connected with the level signal input terminal of one end of the second pull-up resistor, the second chip respectively；If the first MOS is in the conductive state, the 2nd MOS is in an off state, then inputs the PG signal that level signal is high level to the signal input part of the second chip as enable signal；If the first MOS is in an off state, the 2nd MOS is in the conductive state, then not to the signal input part input signal of the second chip.
Description
Technical field
This application involves big data storage server hardware technology fields, more particularly to a kind of time sequence control device and side
Method.
Background technique
In cloud computing era, mass data storage transmits the memory carrier platform for needing large capacity.This large capacity is deposited
Carrier is stored up, in the storage service system operation course of work, it usually needs guarantee that power module timing meets professional standard, that is, need
Monitor power supply output state.
In the prior art, usually by power IC (Power integrated circuit, Power IC) root
According to the feedback signal of power supply chip, control system powers on or the timing of lower electricity.Wherein, Power IC may include muti-piece power supply core
Piece, and power supply status (Power Good, PG) signal output end of upper level power supply chip can be with next stage power supply chip
Signal input part is connected, so that the PG signal that the PG signal output end of upper level power supply chip is exported can be input to next stage
The signal input part of power supply chip.
However, in the prior art, storage service system is run in the course of work, when power supply switches, and switch
It there are when voltage difference between power supply, will lead in power up, the PG signal of upper level power supply chip has fluctuation interference, phase
Ying Di, PG signal sequence voltage also will receive interference (such as high level fluctuation)；Since the signal of next stage power supply chip inputs
The PG signal for holding inputted signal to be exported by upper level power supply chip, therefore the PG signal that next stage power supply chip is exported
It will receive influence, in this way, will lead to the timing disorder of power supply chips at different levels, and then power supply chip intermittences at different levels caused to be restarted,
There are the risks of loss of data.
Summary of the invention
In order to solve the above-mentioned technical problem, this application provides one kind
The embodiment of the present application discloses following technical solution:
The embodiment of the present application provides a kind of time sequence control device, the time sequence control device include the first chip,
Second chip and enabled isolation module；The enabled isolation module includes the first pull-up resistor, the second pull-up resistor, first effect
It should pipe MOS and the second field-effect tube MOS；
The power supply status PG signal output end of first chip is extremely connected with the grid G of the first MOS；Described first
One end of pull-up resistor, the 2nd MOS the pole G be extremely connected with the drain D of the first MOS respectively；The D of 2nd MOS
Pole is connected with the level signal input terminal of one end of second pull-up resistor, second chip respectively；First pull-up
The other end of resistance is connected with pull-up power supply respectively with the other end of second pull-up resistor；The source S pole of first MOS
It is grounded respectively with the pole S of the 2nd MOS；
Wherein, after the PG signal output end output PG signal of first chip, if the first MOS is on shape
State, and the 2nd MOS is in an off state, then the PG signal is pulled to high level by the pull-up power supply, and by level signal
It is inputted as enable signal to the signal input part of second chip for the PG signal of high level；If the first MOS
It is in an off state, and the 2nd MOS is in the conductive state, then not to the signal input part input signal of second chip.
Optionally, the enabled isolation module further includes isolation resistance；One end of the isolation resistance and first core
The power supply status PG signal output end of piece is connected, and the other end of the isolation resistance is extremely connected with the grid G of the first MOS；
The isolation resistance is used to adjust the unlatching response time of the first MOS and the 2nd MOS.
Optionally, the first MOS and the 2nd MOS is N-channel field-effect tube.
Optionally, first chip and second chip are power IC.
Optionally, the model IR38263 of the power IC.
Present invention also provides a kind of sequential control method, the method is applied to timing control described in any of the above embodiments
Device, which comprises
Enabled isolation module receives the PG signal that the first chip is sent；
The enabled isolation module determines the first field-effect tube MOS in the enabled isolation module according to the PG signal
With the working condition of the second field-effect tube MOS；
If the first MOS is in the conductive state, and the 2nd MOS is in an off state, then pull-up power supply believes the PG
Number be pulled to high level, the enabled isolation module using the PG signal that level signal is high level as enable signal, and
The enable signal is inputted to the signal input part of second chip；If the first MOS is in an off state, and second
MOS is in the conductive state, then not to the signal input part input signal of second chip.
Optionally, the first MOS and the 2nd MOS is N-channel field-effect tube.
Optionally, first chip and second chip are power IC.
Optionally, the model IR38263 of the power IC.
Present invention also provides a kind of time sequence control device, described device includes:
Receiving unit, for receiving the PG signal of the first chip transmission；
Determination unit, for determining the work of the first field-effect tube MOS and the second field-effect tube MOS according to the PG signal
Make state；
Transmission unit, if it is in the conductive state for the first MOS, and the 2nd MOS is in an off state, then pulls up electricity
The PG signal is pulled to high level by source, the enabled isolation module using the PG signal that level signal is high level as
Enable signal, and the enable signal is inputted to the signal input part of second chip；If the first MOS is off
State, and the 2nd MOS is in the conductive state, then not to the signal input part input signal of second chip.
It can be seen from above-mentioned technical proposal in the technical solution of the application, time sequence control device include the first chip,
Second chip and enabled isolation module.The enabled isolation module includes the first pull-up resistor, the second pull-up resistor, first effect
It should pipe MOS and the second field-effect tube MOS.The grid of the power supply status PG signal output end of first chip and the first MOS
Pole G is extremely connected；One end of first pull-up resistor, the 2nd MOS the pole the G drain D pole phase with the first MOS respectively
Even；The pole D of 2nd MOS level signal input terminal with one end of second pull-up resistor, second chip respectively
It is connected；The other end of first pull-up resistor is connected with pull-up power supply respectively with the other end of second pull-up resistor；Institute
The pole S of the source S pole and the 2nd MOS of stating the first MOS is grounded respectively.Therefore it is exported in the PG signal of the first chip
After end output PG signal, if the first MOS is in the conductive state, and the 2nd MOS is in an off state, then illustrates the PG letter
It number is high level, the PG signal can be pulled to high level, and be the institute of high level by level signal by the pull-up power supply
PG signal is stated as enable signal to input to the signal input part of second chip；If the first MOS is in an off state,
And the 2nd MOS it is in the conductive state, then illustrate the PG signal be low level, and not to the signal of second chip input
Hold input signal.As it can be seen that when the PG signal that the PG signal output end of the first chip exports is high level, it can be to the second chip
Signal input part input enable signal, and when the PG signal output end of the first chip output PG signal be low level when, no
Enable signal is inputted to the signal input part of the second chip；In this way, when the PG signal sequence of the first chip is interfered, due to
The PG signal that first chip is exported is after enabled isolation module, only when PG signal is high level just to the letter of the second chip
Number input terminal inputs enable signal, therefore the PG signal of the second chip can be made not fluctuate, i.e. the PG letter of the second chip
Number be unaffected, avoid the timing disorder of the second chip, thus greatly reduce the second chip occur intermittence restart,
The risk of loss of data, and then ensure that the operation work of storage service system.
Detailed description of the invention
In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of application without any creative labor, may be used also for those of ordinary skill in the art
To obtain other drawings based on these drawings.
Fig. 1 is a kind of structural schematic diagram of time sequence control device provided by the embodiments of the present application；
Fig. 2 is a kind of structural schematic diagram of enabled isolation module provided by the embodiments of the present application；
Fig. 3 is a kind of method flow diagram of sequential control method provided by the embodiments of the present application；
Fig. 4 is a kind of structural schematic diagram of time sequence control device provided by the embodiments of the present application.
Specific embodiment
In order to make those skilled in the art more fully understand application scheme, below in conjunction in the embodiment of the present application
Attached drawing, the technical scheme in the embodiment of the application is clearly and completely described, it is clear that described embodiment is only this
Apply for a part of the embodiment, instead of all the embodiments.Based on the embodiment in the application, those of ordinary skill in the art exist
Every other embodiment obtained under the premise of creative work is not made, shall fall in the protection scope of this application.
With reference to the accompanying drawing, the various non-limiting embodiments of the application are described in detail.
It is a kind of structural schematic diagram of time sequence control device provided by the embodiments of the present application referring to Fig. 1.As shown in Figure 1, this
Embodiment provides a kind of test circuit board signal device, and time sequence control device includes the first chip 101,102 and of the second chip
Enabled isolation module 103.Wherein, as shown in Fig. 2, enabled isolation module 103 may include on the first pull-up resistor 104, second
Pull-up resistor 105, the first field-effect tube MOS 106 and the second field-effect tube MOS 107.
It should be noted that in one implementation, the first MOS 106 and the 2nd MOS 107 can be N-channel field
Effect pipe.In one implementation, first chip and second chip can be power IC, for example, electric
The model of source integrated circuit can be IR38263.
In the present embodiment, the grid G pole of the power supply status PG signal output end of the first chip 101 and the first MOS 106
It is connected；One end of first pull-up resistor 104, the pole G of the 2nd MOS 107 are extremely connected with the drain D of the first MOS 106 respectively；The
The pole D of two MOS 107 is connected with the level signal input terminal of one end of the second pull-up resistor 105, the second chip 102 respectively；The
The other end of one pull-up resistor 104 is connected with pull-up power supply 108 respectively with the other end of the second pull-up resistor 105, wherein pull-up
The voltage of power supply 108 can be 3V, also, the effect of the first pull-up resistor 104 and the second pull-up resistor 105 is to prevent from enabling
103 shorted to earth of isolation module；The source S pole of first MOS 106 and the pole S of the 2nd MOS 107 are grounded respectively.
In the present embodiment, after the PG signal output end output PG signal of first chip 101, if the first MOS
106 is in the conductive state, and the 2nd MOS 107 is in an off state, then illustrates that the PG signal can be high level, therefore pull up electricity
The PG signal can be pulled to high level by source 108, and can be using the PG signal that level signal is high level as enabled letter
Number, it is inputted to the signal input part of the second chip 102；If the first MOS 106 is in an off state, and the 2nd MOS 107 is in
On state, then not to the signal input part input signal of the second chip 102.In this way, the PG when the first chip 101 can be made
When signal sequence is interfered, the PG signal exported by the first chip 101 only works as PG after enabled isolation module 102
Enable signal just is inputted to the signal input part of the second chip 102 when signal is high level, therefore the second chip 102 can be made
PG signal will not fluctuate, i.e. the PG signal of the second chip 102 is unaffected, and avoid the timing of the second chip 102
Disorder, thus greatly reduce the second chip 102 occur it is intermittent restart, the risk of loss of data.
In one possible implementation, enabling isolation module 103 can also include isolation resistance 109.Wherein, it is isolated
One end of resistance 109 is connected with the power supply status PG signal output end of the first chip 101, the other end of isolation resistance 109 and
The grid G of one MOS 106 is extremely connected.Specifically, isolation resistance 109 can be used for adjusting the first MOS 106 and the 2nd MOS 107
The unlatching response time, so that the unlatching response time of the first MOS 106 and the 2nd MOS 107 reaches preset value, wherein this is pre-
If value can be understood as ideal value；It should be noted that if the resistance value of isolation resistance 109 is bigger, then the first MOS 106 and second
The unlatching response time of MOS 107 is longer, conversely, then the unlatching response time of the first MOS 106 and the 2nd MOS 107 is shorter.
It can be seen from above-mentioned technical proposal in the technical solution of the application, time sequence control device include the first chip,
Second chip and enabled isolation module.The enabled isolation module includes the first pull-up resistor, the second pull-up resistor, first effect
It should pipe MOS and the second field-effect tube MOS.The grid of the power supply status PG signal output end of first chip and the first MOS
Pole G is extremely connected；One end of first pull-up resistor, the 2nd MOS the pole the G drain D pole phase with the first MOS respectively
Even；The pole D of 2nd MOS level signal input terminal with one end of second pull-up resistor, second chip respectively
It is connected；The other end of first pull-up resistor is connected with pull-up power supply respectively with the other end of second pull-up resistor；Institute
The pole S of the source S pole and the 2nd MOS of stating the first MOS is grounded respectively.Therefore it is exported in the PG signal of the first chip
After end output PG signal, if the first MOS is in the conductive state, and the 2nd MOS is in an off state, then illustrates the PG letter
It number is high level, the PG signal can be pulled to high level, and be the institute of high level by level signal by the pull-up power supply
PG signal is stated as enable signal to input to the signal input part of second chip；If the first MOS is in an off state,
And the 2nd MOS it is in the conductive state, then illustrate the PG signal be low level, and not to the signal of second chip input
Hold input signal.As it can be seen that when the PG signal that the PG signal output end of the first chip exports is high level, it can be to the second chip
Signal input part input enable signal, and when the PG signal output end of the first chip output PG signal be low level when, no
Enable signal is inputted to the signal input part of the second chip；In this way, when the PG signal sequence of the first chip is interfered, due to
The PG signal that first chip is exported is after enabled isolation module, only when PG signal is high level just to the letter of the second chip
Number input terminal inputs enable signal, therefore the PG signal of the second chip can be made not fluctuate, i.e. the PG letter of the second chip
Number be unaffected, avoid the timing disorder of the second chip, thus greatly reduce the second chip occur intermittence restart,
The risk of loss of data, and then ensure that the operation work of storage service system.
Referring to Fig. 3, a kind of sequential control method in the embodiment of the present application is shown, it is corresponding that the method is applied to Fig. 1
Time sequence control device, which comprises
S301: enabled isolation module receives the PG signal that the first chip is sent.
S302: the enabled isolation module determines the first field-effect in the enabled isolation module according to the PG signal
The working condition of pipe MOS and the second field-effect tube MOS.
S303: if the first MOS is in the conductive state, and the 2nd MOS is in an off state, then pull-up power supply will be described
PG signal is pulled to high level, and the enabled isolation module is using the PG signal that level signal is high level as enabled letter
Number, and the enable signal is inputted to the signal input part of second chip；If the first MOS is in an off state,
And the 2nd MOS it is in the conductive state, then not to the signal input part input signal of second chip.
In the present embodiment, after the PG signal output end output PG signal of the first chip, if the first MOS is on shape
State, and the 2nd MOS is in an off state, then illustrates that the PG signal can be high level；Therefore pull-up power supply can be first passed through, by this
PG signal is pulled to high level by low level, with guarantee the PG signal after pull-up power supply is drawn high for high level, then, can be with
Using the PG signal that level signal is high level as enable signal, and inputted to the signal input part of the second chip, so that
Second chip can be according to the enable signal, and control powers on or the timing of lower electricity, and records data.If the first MOS is off
State, and the 2nd MOS is in the conductive state then illustrates that the PG signal is low level, for avoid the second chip PG signal electricity
Ordinary mail number toggles constantly between high level and low level, and the PG signal of the second chip is caused to fluctuate, therefore can not
To the signal input part input signal of the second chip.
It can be seen from above-mentioned technical proposal in the technical solution of the application, when the first chip PG signal sequence by
To PG signal when interference, exported by the first chip after enabled isolation module, only just when PG signal is high level
Enable signal is inputted to the signal input part of the second chip, therefore the PG signal of the second chip can be made not fluctuate, i.e.,
The PG signal of second chip is unaffected, and is avoided the timing disorder of the second chip, is thus greatly reduced the second chip
Occur intermittence restart, the risk of loss of data, and then ensure that the operation work of storage service system.
Referring to fig. 4, showing a kind of time sequence control device, described device in the embodiment of the present application includes:
Receiving unit 401, for receiving the PG signal of the first chip transmission.
Determination unit 402, for determining the first field-effect tube MOS's and the second field-effect tube MOS according to the PG signal
Working condition.
Transmission unit 403, if in the conductive state for the first MOS, and the 2nd MOS is in an off state, then on
Draw power supply that the PG signal is pulled to high level, level signal is the PG signal of high level by the enabled isolation module
It is inputted as enable signal, and by the enable signal to the signal input part of second chip；If the first MOS is in
Off state, and the 2nd MOS is in the conductive state, then not to the signal input part input signal of second chip.
It can be seen from above-mentioned technical proposal in the technical solution of the application, when the first chip PG signal sequence by
To PG signal when interference, exported by the first chip after enabled isolation module, only just when PG signal is high level
Enable signal is inputted to the signal input part of the second chip, therefore the PG signal of the second chip can be made not fluctuate, i.e.,
The PG signal of second chip is unaffected, and is avoided the timing disorder of the second chip, is thus greatly reduced the second chip
Occur intermittence restart, the risk of loss of data, and then ensure that the operation work of storage service system.
It should be noted that all the embodiments in this specification are described in a progressive manner, each embodiment it
Between same and similar part may refer to each other, each embodiment focuses on the differences from other embodiments.
Equipment and system embodiment described above is only schematical, wherein as illustrated by the separation member unit can be or
Person, which may not be, to be physically separated.It can select some or all of the modules therein according to the actual needs to realize this
The purpose of example scheme.Those of ordinary skill in the art are without creative efforts, it can understand and real
It applies.
The above, only this preferable specific embodiment, but the protection scope of the application is not limited thereto, it is any
Within the technical scope of the present application, any changes or substitutions that can be easily thought of by those familiar with the art, all answers
Cover within the scope of protection of this application.Therefore, the protection scope of the application should be subject to the protection scope in claims.
Claims (10)
1. a kind of time sequence control device, which is characterized in that the time sequence control device includes the first chip, the second chip and enables
Isolation module；The enabled isolation module includes the first pull-up resistor, the second pull-up resistor, the first field-effect tube MOS and second
Field-effect tube MOS；
The power supply status PG signal output end of first chip is extremely connected with the grid G of the first MOS；First pull-up
One end of resistance, the 2nd MOS the pole G be extremely connected with the drain D of the first MOS respectively；The pole D of 2nd MOS point
It is not connected with the level signal input terminal of one end of second pull-up resistor, second chip；First pull-up resistor
The other end be connected respectively with pull-up power supply with the other end of second pull-up resistor；The source S pole of first MOS and institute
The pole S for stating the 2nd MOS is grounded respectively；
Wherein, after the PG signal output end output PG signal of first chip, if the first MOS is in the conductive state, and
2nd MOS is in an off state, then the PG signal is pulled to high level by the pull-up power supply, and is high electricity by level signal
The flat PG signal is inputted as enable signal to the signal input part of second chip；It is closed if the first MOS is in
Disconnected state, and the 2nd MOS is in the conductive state, then not to the signal input part input signal of second chip.
2. the apparatus according to claim 1, which is characterized in that the enabled isolation module further includes isolation resistance；It is described
One end of isolation resistance is connected with the power supply status PG signal output end of first chip, the other end of the isolation resistance with
The grid G of first MOS is extremely connected；
The isolation resistance is used to adjust the unlatching response time of the first MOS and the 2nd MOS.
3. device according to claim 1 or 2, which is characterized in that the first MOS and the 2nd MOS is N-channel
Field-effect tube.
4. device according to claim 1 or 2, which is characterized in that first chip and second chip are power supply
Integrated circuit.
5. device according to claim 4, which is characterized in that the model IR38263 of the power IC.
6. a kind of sequential control method, which is characterized in that the method is applied to the described in any item timing controls of claim 1-5
Device processed, which comprises
Enabled isolation module receives the PG signal that the first chip is sent；
The enabled isolation module determines the first field-effect tube MOS and in the enabled isolation module according to the PG signal
The working condition of two field-effect tube MOS；
If the first MOS is in the conductive state, and the 2nd MOS is in an off state, then pull-up power supply will be on the PG signal
It is pulled to high level, the enabled isolation module is using the PG signal that level signal is high level as enable signal, and by institute
Enable signal is stated to input to the signal input part of second chip；If the first MOS is in an off state, and the 2nd MOS
It is in the conductive state, then not to the signal input part input signal of second chip.
7. according to the method described in claim 6, it is characterized in that, the first MOS and the 2nd MOS are N-channel field
Effect pipe.
8. according to the method described in claim 6, it is characterized in that, first chip and second chip are integrated for power supply
Circuit.
9. device according to claim 8, which is characterized in that the model IR38263 of the power IC.
10. a kind of time sequence control device, which is characterized in that described device includes:
Receiving unit, for receiving the PG signal of the first chip transmission；
Determination unit, for determining the work shape of the first field-effect tube MOS and the second field-effect tube MOS according to the PG signal
State；
Transmission unit, if it is in the conductive state for the first MOS, and the 2nd MOS is in an off state, then pull-up power supply will
The PG signal is pulled to high level, and the enabled isolation module is using the PG signal that level signal is high level as enabled
Signal, and the enable signal is inputted to the signal input part of second chip；If the first MOS is off shape
State, and the 2nd MOS is in the conductive state, then not to the signal input part input signal of second chip.
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| CN201810837174.1A CN108964648A (en) | 2018-07-26 | 2018-07-26 | A kind of time sequence control device and method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810837174.1A CN108964648A (en) | 2018-07-26 | 2018-07-26 | A kind of time sequence control device and method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110011654A (en) * | 2019-05-17 | 2019-07-12 | 江苏芯盛智能科技有限公司 | A kind of power domain ON-OFF control circuit, method and chip |
| WO2021056908A1 (en) * | 2019-09-29 | 2021-04-01 | 苏州浪潮智能科技有限公司 | Method for detecting rationality of pg pin power-on time sequence, system and related components |
| CN113708602A (en) * | 2021-10-27 | 2021-11-26 | 苏州浪潮智能科技有限公司 | PG signal processing circuit and power supply device |
| CN114489303A (en) * | 2021-12-30 | 2022-05-13 | 深圳市广和通无线股份有限公司 | Power-on sequence control circuit and system |
| US11671209B2 (en) | 2013-03-28 | 2023-06-06 | Nec Corporation | Method and apparatus for determining HARQ timing in communication systems |
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2018
- 2018-07-26 CN CN201810837174.1A patent/CN108964648A/en not_active Withdrawn
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11671209B2 (en) | 2013-03-28 | 2023-06-06 | Nec Corporation | Method and apparatus for determining HARQ timing in communication systems |
| CN110011654A (en) * | 2019-05-17 | 2019-07-12 | 江苏芯盛智能科技有限公司 | A kind of power domain ON-OFF control circuit, method and chip |
| CN110011654B (en) * | 2019-05-17 | 2022-10-11 | 江苏芯盛智能科技有限公司 | Power domain switch control circuit, method and chip |
| WO2021056908A1 (en) * | 2019-09-29 | 2021-04-01 | 苏州浪潮智能科技有限公司 | Method for detecting rationality of pg pin power-on time sequence, system and related components |
| US11863178B2 (en) | 2019-09-29 | 2024-01-02 | Inspur Suzhou Intelligent Technology Co., Ltd. | Method for detecting rationality of PG pin power-on time sequence, system and related components |
| CN113708602A (en) * | 2021-10-27 | 2021-11-26 | 苏州浪潮智能科技有限公司 | PG signal processing circuit and power supply device |
| CN114489303A (en) * | 2021-12-30 | 2022-05-13 | 深圳市广和通无线股份有限公司 | Power-on sequence control circuit and system |
| CN114489303B (en) * | 2021-12-30 | 2024-01-05 | 深圳市广和通无线股份有限公司 | Power-on time sequence control circuit and system |
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Application publication date: 20181207 |