CN110011654B - Power domain switch control circuit, method and chip - Google Patents
Power domain switch control circuit, method and chip Download PDFInfo
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- CN110011654B CN110011654B CN201910414743.6A CN201910414743A CN110011654B CN 110011654 B CN110011654 B CN 110011654B CN 201910414743 A CN201910414743 A CN 201910414743A CN 110011654 B CN110011654 B CN 110011654B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/266—Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
- H03K2217/0081—Power supply means, e.g. to the switch driver
Abstract
The application discloses power domain switch control circuit, method and chip, including N PSW, wherein: a first input end and a second input end of a first PSW are respectively connected with a first enabling signal and a second enabling signal, a first input end and a second input end of an ith PSW are respectively connected with a first output end and a second output end of an i-1 th PSW, and a first output end and a second output end of an Nth PSW respectively output a first confirmation signal and a second confirmation signal; the first enabling signal and the second enabling signal are separated by a preset time delay, and each PSW comprises a first switch unit and a second switch unit which are respectively controlled to be switched on and switched off by a corresponding first input end and a corresponding second input end. Therefore, the on-off of the first switch unit controlled by the first enabling signal and the on-off of the second switch unit controlled by the second enabling signal are not interfered with each other, the action time difference exists, the phenomenon that overlarge current transient pulse is generated due to the on-off at the same time is avoided, and devices inside a chip are protected.
Description
Technical Field
The present application relates to the field of chip design technologies, and in particular, to a power domain switch control circuit, a method, and a chip.
Background
The low power consumption research of chips, which is usually based on transistor level, starts from analyzing the source of power consumption. The power consumption of a CMOS (Complementary Metal Oxide Semiconductor) generally includes three parts, one is dynamic power consumption caused by charging and discharging a load capacitor; secondly, in the short jump process of the CMOS, the P tube and the N tube are conducted simultaneously to form short-circuit current between a power supply and the ground to cause short-circuit power consumption, and thirdly, static power consumption is caused by leakage current. As shown in fig. 1, the leakage current here mainly includes: gate leakage current, sub-threshold current, and drain diffusion junction leakage current.
In the existing low power consumption solution, one chip is generally divided into a plurality of power domains, and a Power Switch (PSW) is adopted to control the on and off of different power domains, so as to meet the requirement of low power consumption.
In the same power supply domain, devices with large driving capability are divided into a group called a large chain, and devices with small driving capability are divided into a group called a small chain. As shown in fig. 2, the conventional solution uses a dual-input header PSW to form a control circuit, which sequentially controls the on and off of the large chain and the small chain. The first input end of the PSW1 is connected with an enable signal, the first output end of the PSW1 is connected with the first input end of the PSW2, the rest is done, the first output end of the PSWn is connected with the second input end of the PSWn, the second output end of the PSWn is connected with the second input end of the PSW (n-1), the rest is done, and finally the ack signal is output from the second output end of the PSW 1. The heat hvt PMOS of each PSW controls a driving device in the large chain, and the daughter hvt PMOS controls a device in the small chain, so that the small chain and the large chain are sequentially started from front to back, and the instantaneous power of the chip is effectively reduced.
Within the PSW, the maximum delay for a signal to pass from nsepien to nsepout is 0.7ns, and there is also a delay from nsepinout of the current PSW to nsepien of the next PSW, but this delay is negligible relative to the former. Suppose that 100 ten thousand devices in a power domain can estimate that the time difference between the sequential opening of the big chain and the small chain is about 350us. All driving devices in the power domain are sequentially started within the small time difference, and instantaneous current pulses with large amplitude can be generated due to leakage current at the moment that all driving devices are powered on and powered off simultaneously, so that partial devices are in the risk of being broken down.
Therefore, how to provide a solution to the above technical problems is a problem to be solved by those skilled in the art.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a power domain switch control circuit, method and chip with smaller transient current pulse. The specific scheme is as follows:
a power domain switch control circuit comprising N PSWs, wherein:
a first input end and a second input end of a first PSW are respectively connected with a first enable signal and a second enable signal, a first input end and a second input end of an ith PSW are respectively connected with a first output end and a second output end of an i-1 th PSW, and a first output end and a second output end of an Nth PSW respectively output a first confirmation signal and a second confirmation signal;
the PSW comprises a first input end and a second input end, wherein i and N are integers, i is more than 1 and less than or equal to N, the first enabling signal and the second enabling signal are two enabling signals separated by a preset time delay, and each PSW comprises a first switch unit and a second switch unit which are respectively controlled to be switched on and switched off by the corresponding first input end and the corresponding second input end.
Preferably, the power domain switch control circuit further comprises:
the first power domain comprises N first-class driving elements, and the driving state of each first-class driving element is controlled by a corresponding first switch unit;
and the second power domain comprises N second-type driving elements, and the driving state of each second-type driving element is controlled by a corresponding second switch unit.
Preferably, the control end of the first switch unit of each PSW is connected to the corresponding first input end and first output end, and the first end and the second end of the first switch unit are sequentially connected to the corresponding common power source and the corresponding first-type driving element;
and the control end of the second switch unit of each PSW is connected with the corresponding second input end and second output end, and the first end and the second end of the second switch unit of each PSW are sequentially connected with the common power supply and the corresponding second-class driving element.
Preferably, each of the PSWs further comprises a first diode, a second diode, a third diode, and a fourth diode; wherein:
the control end of the first switch unit of each PSW is connected with the corresponding first input end through a corresponding first diode, and the control end of the first switch unit of each PSW is connected with the corresponding first output end through a corresponding second diode;
the control end of the second switch unit of each PSW is connected with the corresponding second input end through the corresponding third diode, and the control end of the second switch unit of each PSW is connected with the corresponding second output end through the corresponding fourth diode.
Preferably, the first enable signal and the second enable signal are two enable signals generated based on a configuration register.
Preferably, the first switch unit and the second switch unit are both PMOS transistors.
Correspondingly, the invention also discloses a power domain switch control method, which comprises the following steps:
acquiring a control parameter, wherein the control parameter comprises a preset time delay between a first enabling signal and a second enabling signal;
and applying the first enabling signal and the second enabling signal to a power domain switch control circuit according to the control parameter so as to control N PSWs, wherein N is an integer greater than 1.
Preferably, the applying the first enable signal and the second enable signal to the power domain switch control circuit according to the control parameter to control the processes of the N PSWs specifically includes:
applying the first enable signal to the power domain switch control circuit;
and after waiting for the preset time delay, applying the second enabling signal to the power domain switch control circuit.
Preferably, the control parameter further includes a feedback delay obtained by subtracting the signal transmission delay from the preset delay;
correspondingly, the applying the first enable signal and the second enable signal to the power domain switch control circuit according to the control parameter to control the processes of the N PSWs specifically includes:
applying the first enable signal to the power domain switch control circuit;
and when a first confirmation signal of the power domain switch control circuit is received, waiting for feedback time delay, and applying the second enabling signal to the voltage source switch control circuit.
Correspondingly, the invention also discloses a power domain switch control chip which comprises the power domain switch control circuit.
The application discloses power domain on-off control circuit, including N PSW, wherein: a first input end and a second input end of a first PSW are respectively connected with a first enable signal and a second enable signal, a first input end and a second input end of an ith PSW are respectively connected with a first output end and a second output end of an i-1 th PSW, and a first output end and a second output end of an Nth PSW respectively output a first confirmation signal and a second confirmation signal; and i and N are integers, i is more than 1 and less than or equal to N, the first enable signal and the second enable signal are two enable signals separated by a preset time delay, and each PSW comprises a first switch unit and a second switch unit which are respectively controlled to be switched on and switched off by a corresponding first input end and a corresponding second input end.
From the above, in the present application, the on/off of the first switch unit controlled by the first enable signal and the on/off of the second switch unit controlled by the second enable signal are not interfered with each other, and because there is a time difference between the first enable signal and the second enable signal, there is an action time difference between the on/off of the first switch unit and the on/off of the second switch unit, thereby avoiding that the first switch unit and the second switch unit are simultaneously on/off in a very short time to generate an excessive current transient pulse, reducing the power consumption of the chip, protecting the internal devices of the chip, and improving the reliability of the chip.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a schematic diagram illustrating the composition of CMOS leakage current in the prior art;
FIG. 2 is a diagram illustrating a conventional power domain switch control circuit in the prior art;
FIG. 3 is a diagram illustrating a structure of a power domain switch control circuit according to an embodiment of the present disclosure;
FIG. 4 is a diagram illustrating an exemplary power domain switch control circuit according to an embodiment of the present disclosure;
FIG. 5 is a flowchart illustrating steps of a power domain switch control method according to an embodiment of the present disclosure;
FIG. 6 is a flowchart illustrating steps of a specific power domain switch control method according to an embodiment of the present invention;
fig. 7 is a flowchart illustrating steps of another specific power domain switch control method according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the prior art, the difference of the turn-on time of all driving devices in a power supply domain is extremely small, and a large current transient pulse is generated, so that partial devices can be broken down. The control of the driving device in the application is controlled by two enabling signals which are separated by preset time delay, so that overlarge current transient pulse is avoided, and devices in a chip are protected.
The embodiment of the application discloses a power domain switch control circuit, which comprises N PSWs (power supply state switches), and is shown in figure 3, wherein:
the first input end and the second input end of the first PSW are respectively connected with a first enable signal enable1 and a second enable signal enable2, the first input end and the second input end of the ith PSW are respectively connected with the first output end and the second output end of the (i-1) th PSW, and the first output end and the second output end of the Nth PSW respectively output a first acknowledgement signal ack1 and a second acknowledgement signal ack2;
wherein i and N are integers, i is more than 1 and less than or equal to N, the first enable signal enable1 and the second enable signal enable2 are two enable signals separated by a preset time delay, and each PSW comprises a first switch unit and a second switch unit which are respectively controlled to be switched on and switched off by a corresponding first input end and a corresponding second input end.
It is understood that the PSWs used in this embodiment are of a dual-input header type, each PSW is an integrated module of a fixed circuit, and the integrated module includes, in addition to the first input terminal, the second input terminal, the first switch unit, the second switch unit, the first output terminal, and the second output terminal, other related auxiliary components, such as a backflow preventing diode, an output signal terminal of the first switch unit and the second switch unit, and the like.
The specific types of the first switch unit and the second switch unit may be a certain circuit unit with controllable switching characteristics, or may be a controllable switch tube, such as a MOS tube, a triode, or the like, and a PMOS tube may be usually selected.
It should be noted that the on-off control of the first switch unit and the second switch unit are respectively controlled by the first input terminal and the second input terminal of the PSW where the first switch unit and the second switch unit are located, that is, the first switch unit and the second switch unit in each PSW are respectively controlled by the corresponding first input terminal and second input terminal to be on or off, and the on-off state of the first switch unit and the second switch unit can be used as a signal to control other elements in the power domain, and the on-off state is output by the output signal terminal of the first switch unit or the second switch unit.
Specifically, as is apparent from fig. 3, the first enable signal enable1 controls the first switching cells in all N PSWs, and the second enable signal enable2 controls the second switching cells in all N PSWs. In the prior art shown in fig. 2, only one enable signal enable is used to control the heat hvt PMOS and the daughter hvt PMOS, so that they are sequentially turned on in a very short time, an excessive current pulse is generated in the circuit, and the hidden trouble that an internal device is broken down exists; in the embodiment, the conduction states of the two types of PMOS, i.e., the first switch unit and the second switch unit, are independently controlled by two enable signals, i.e., the first enable signal enable1 and the second enable signal enable2, respectively, the conduction time difference of the two types of switch units is determined by the time difference of the two enable signals, i.e., the preset time delay, a proper preset time delay is selected, and after one enable signal is sent and the corresponding type of switch unit is to be completely conducted, the other enable signal is sent and the corresponding switch unit is conducted, so that the simultaneous conduction of all switch units in a very short time is avoided, the instantaneous pulse of the current is smaller, and the possibility that the instantaneous current breaks through internal devices is eliminated. Meanwhile, because the current transient pulse is small, the power consumption of devices related to the power domain switch control circuit is lower than that of the prior art, and the purpose of low power consumption is achieved.
It can be understood that, the precedence relationship between the first enable signal enable1 and the second enable signal enable2 is not limited herein, as long as the time interval between the two enable signals is a preset time delay, and the preset time delay is set to require that the first enable signal does not start transmission during the transmission process of the power domain switch control circuit, and the second enable signal does not start transmission.
Furthermore, the lengths of the preset time delays of the two enable signals do not have a unified standard, and because the voltage level and the number of devices in each specific item are different, the preset time delay needs to be determined according to a specific IR drop simulation result, and the magnitude of the preset time delay is generally in the millisecond level. Specifically, the preset time delay value is generally selected and set by referring to the voltage level, the model parameters of the PSWs, the number of the PSWs in the power domain switch control circuit, the model parameters of the driving objects of each of the first switch unit and the second switch unit, and other factors; specifically, the embodiment of the application can acquire circuit parameters related to the preset time delay, and obtain the preset time delay or other control quantities by using a calculation formula for determining the priority level of the circuit parameters; in addition, experimental verification can be performed to detect the signal transmission time delay of the individual first enable signal enable1 and the individual second enable signal enable2 in the N PSWs, detect the time required for waiting for the current to be stable in the driving process of the driving objects of the two switch units, set control parameters according to the time data and the priority thereof, and finally determine whether the control parameters or the preset time delay set by the experiment can meet the requirements in the embodiment. The specific test method can be performed on a specific physical circuit or can be completed through a simulation circuit model.
It can be understood that the preset time delay may be set in the control program in advance, or may be configured for regulation and control in the field, or may be adjusted according to the circuit condition in the field after being set in the control program in advance. Specifically, the first enable signal enable1 and the second enable signal enable2 are generally two enable signals generated based on the configuration register, and the setting of the preset time delay is also performed on parameter control of the configuration register.
From the above, in the present application, the on/off of the first switch unit controlled by the first enable signal and the on/off of the second switch unit controlled by the second enable signal do not interfere with each other, and because there is a time difference between the first enable signal and the second enable signal, there is an action time difference between the on/off of the first switch unit and the on/off of the second switch unit, so that it is avoided that the first switch unit and the second switch unit are simultaneously turned on and off within a very short time to generate an excessive current transient pulse, thereby reducing the power consumption of the chip, protecting the internal devices of the chip, and improving the reliability of the chip.
The embodiment of the application discloses a specific power domain switch control circuit, and compared with the previous embodiment, the embodiment further describes and optimizes the technical scheme. Specifically, the method comprises the following steps:
referring to fig. 4, the power domain switch control circuit further includes:
the first power domain comprises N first-type driving elements, and the driving state of each first-type driving element is controlled by a corresponding first switch unit;
and the second power domain comprises N second-type driving elements, and each second-type driving element is controlled by a corresponding second switch unit to be in a driving state.
Specifically, in the connection relationship of the circuit devices, the control end of the first switch unit of each PSW is connected to the corresponding first input end and first output end, and the first end and the second end of the first switch unit are sequentially connected to the corresponding common power supply TVDD and the corresponding first-type driving element; the control end of the second switch unit of each PSW is connected to the corresponding second input end and second output end, and the first end and the second end of the second switch unit are sequentially connected to the corresponding common power supply TVDD and the corresponding second-type driving element. Here, the second terminals of the first switching unit and the second switching unit are the output signal terminals of the control driving element in the above embodiment. It should be understood that an output port or a module unit corresponding to a module unit in this paragraph actually refers to an output port or a module unit in the PSW where the module unit is located. It can be seen that, in fig. 4, the first switch unit and the second switch unit are both PMOS transistors, and taking PMOS transistors as an example, the gate, the source, and the drain of the PMOS transistor sequentially correspond to the control terminal, the first terminal, and the second terminal of the first switch unit or the second switch unit.
Furthermore, each PSW further includes a first diode NSLEEPOUT1, a second diode NSLEEPOUT1, a third diode nsleep 2 and a fourth diode NSLEEPOUT2, so as to prevent the backflow phenomenon from damaging the circuit; wherein:
the control end of the first switch unit of each PSW is connected with the corresponding first input end through the corresponding first diode NSLEEPIN1, and the control end of the first switch unit of each PSW is connected with the corresponding first output end through the corresponding second diode NSLEEPOUT 1;
the control end of the second switch unit of each PSW is connected to the corresponding second input end through the corresponding third diode NSLEEPIN2, and the control end of the second switch unit of each PSW is connected to the corresponding second output end through the corresponding fourth diode NSLEEPOUT 2.
It is understood that besides the above mentioned circuit structure of PSW corresponding to fig. 4, other PSW structures can be applied in the present embodiment, and are not limited herein.
Further, the division of the first power domain and the second power domain may generally divide the first power domain and the second power domain into a small chain and a large chain according to the total driving power of the driving elements in the power domains. In addition to this, the respective drive powers of the drive elements in the power domain may also be compared and divided.
In a specific embodiment, the driving elements in the same power range belong to the same power domain, where the first type of driving element is specifically a driving element whose driving power is in a first power range, the second type of driving element is specifically a driving element whose driving power is in a second power range, and the first power range and the second power range do not overlap with each other, but the same power range may refer to a set of several power intervals, that is, a case where the first power range and the second power range may intersect on a power number axis is allowed by this embodiment.
In addition to the above method of dividing the power domains according to the driving power, it is also possible to divide all the driving elements into the first type driving elements and the second type driving elements by using other parameter conditions or design requirements, such as functions and physical positions of the driving elements, so as to obtain the first power domain and the second power domain.
It is to be understood that the first type of driving element and the second type of driving element in this embodiment may be designed with reference to the circuit structure of fig. 4, or may select another driving circuit, and the configuration is not limited in detail here.
Accordingly, the present application discloses a power domain switch control method, as shown in fig. 5, including:
s11: acquiring a control parameter;
the control parameter comprises a preset time delay between a first enable signal enable1 and a second enable signal enable 2;
specifically, the present embodiment may be applied to the power domain switch control circuit described in the above embodiments, and may also be applied to other power domain switch control circuits including N PSWs. The value of the preset time delay is generally selected and set according to factors such as model parameters of the PSW, the number of PSWs in the power domain switch control circuit, and model parameters of driving objects of each of the first switch unit and the second switch unit.
Therefore, in addition to the preset time delay directly set by the control parameter in this embodiment, other control quantities related to time may also be selected, so as to achieve the purpose that the two enable signals do not interfere with each other in this embodiment.
Specifically, the embodiment of the application can acquire circuit parameters related to the preset time delay, and obtain the preset time delay or other control quantities by using a calculation formula determining the priority level of the circuit parameters; and test verification can be carried out, the signal transmission time delay of the single first enable signal enable1 and the single second enable signal enable2 in the N PSWs is measured and calculated, the time required by waiting for the current to be stable in the driving process of the driving objects of the two switch units is detected, and then control parameters are set according to the time data and the priority level of the time data.
S12: and applying a first enable signal enable1 and a second enable signal enable2 to the power domain switch control circuit according to the control parameters to control the N PSWs, wherein N is an integer greater than 1.
Specifically, the two enable signals, i.e., the first enable signal enable1 and the second enable signal enable2, applied to the power domain switch control circuit pass through the N PSWs, and actually, the two enable signals independently control a part of each PSW. As can be understood from the above, the first enable signal enable1 controls the first switch units in all the N PSWs, and the second enable signal enable2 controls the second switch units in all the N PSWs, the connection structure of the power domain switch control circuit in this embodiment determines that the two enable signals do not interfere with each other, and a phenomenon in the prior art that one enable signal enable controls all the first switch units and the second switch units, so that all the switch units are turned on in a very short time and an excessive current pulse is generated in the circuit, cannot occur. Therefore, in this embodiment, as long as a proper preset time delay is set, after one enable signal is sent and the corresponding switch unit is turned on, another enable signal is sent and the corresponding switch unit is turned on, so that all the switch units can be prevented from acting in a very short time, and thus, the current transient pulse is small.
Specifically, the embodiment does not limit the precedence relationship between the first enable signal enable1 and the second enable signal enable2, as long as the time interval between the two enable signals is the preset time delay.
As an example of the power domain switch control circuit in the above embodiment, as can be seen from the specific circuit topology diagram in fig. 4, the first switch unit is used to drive the first type of driving element of the first power domain, the second switch unit is used to drive the second type of driving element of the second power domain, and the two types of driving elements are classified and wired according to the driving power, and may be classified according to the driving power range, and may also be classified according to the function and physical location of the driving element.
From the above, in the present application, the on/off of the first switch unit controlled by the first enable signal and the on/off of the second switch unit controlled by the second enable signal are not interfered with each other, and because there is a time difference between the first enable signal and the second enable signal, there is an action time difference between the on/off of the first switch unit and the on/off of the second switch unit, thereby avoiding that the first switch unit and the second switch unit are simultaneously on/off in a very short time to generate an excessive current transient pulse, reducing the power consumption of the chip, protecting the internal devices of the chip, and improving the reliability of the chip.
The embodiment of the present application discloses a specific power domain switch control method, and compared with the previous embodiment, the present embodiment further describes and optimizes the technical scheme. Specifically, see fig. 6 for a schematic representation of:
s21: acquiring a control parameter;
the control parameter comprises a preset time delay between a first enable signal enable1 and a second enable signal enable 2;
s22: applying a first enable signal enable1 to a power domain switch control circuit;
s23: and after waiting for the preset time delay, applying a second enable signal enable2 to the power domain switch control circuit.
In the embodiment, the sequence of the first enable signal enable1 and the second enable signal enable2 is clearly specified, the first enable signal enable1 is applied and then waits for a preset time delay, the second enable signal enable2 is directly applied, the embodiment is simple and easy to implement under the conditions that the whole power domain switch control circuit is correctly wired and has no line device fault, the action time of the second enable signal enable2 can be deduced only by positioning the action time of the first enable signal enable1, and the method is an efficient and rapid control method.
The embodiment of the present application discloses a specific power domain switch control method, and compared with the previous embodiment, the present embodiment further describes and optimizes the technical scheme. Specifically, see fig. 7 for a schematic representation of:
s31: acquiring a control parameter; the control parameters also comprise feedback time delay obtained by subtracting the signal transmission time delay according to the preset time delay;
s32: applying a first enable signal enable1 to a power domain switch control circuit;
s33: and when the first acknowledgement signal ack1 of the power domain switch control circuit is received and the feedback time delay is waited, applying a second enable signal enable2 to the voltage source switch control circuit.
Compared with the previous embodiment, the present embodiment also verifies whether the connection of the power domain switch control circuit is correct and reliable during the process of applying the enable signal: if the signal path of the first enable signal enable1 is complete and correct, the first acknowledgement signal ack1 can be received; if the signal path of the second enable signal enable2 is complete and correct, the second acknowledgement signal ack2 can be received; if a certain confirmation signal is not received, the corresponding signal path may have problems, and the circuit needs to be checked again to eliminate the hidden trouble of the circuit in the power domain switch control circuit. That is, after receiving the first acknowledge signal ack1, the second enable signal enable2 is applied, so that the system reliability of the entire power domain switch control circuit can be improved.
Specifically, the feedback time delay is different from the preset time delay. The preset time delay must be set in consideration of the signal transmission time delay, that is, the time from the sending of the first enable signal enable1 to the receiving of the first acknowledge signal ack1, and also the time from the sending of the second enable signal enable2 to the receiving of the second acknowledge signal ack2, while in the present embodiment, the timing is started from the receiving of the first acknowledge signal ack1, so that the signal transmission time delay is not included in the feedback time delay, and only the current stability reserved time for the driving object of the PMOS is considered.
Further, since the feedback delay involves three signals: the first enable signal enable1, the first acknowledge signal ack1 and the second enable signal enable2, so the present embodiment is slightly different from the previous embodiment in step execution, but at the same time, the present embodiment improves the reliability of the power domain switch control circuit, which is an advantage that the previous embodiment does not have.
Correspondingly, the application also discloses a power domain switch control chip, which comprises the power domain switch control circuit in the embodiment.
Specifically, the power domain switch control chip is a chip integrated with the power domain switch control circuit, and details of the specific power domain switch control circuit may refer to relevant contents in the above embodiments, which are not described herein again.
The power domain switch control chip in this embodiment has the same beneficial effects as the power domain switch control circuit described above, and is not described herein again.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or apparatus that comprises the element.
The power domain switch control circuit, the method and the chip provided by the present application are introduced in detail above, and a specific example is applied in the present application to explain the principle and the implementation of the present application, and the description of the above embodiment is only used to help understand the method and the core idea of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, the specific implementation manner and the application scope may be changed, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (7)
1. A power domain switch control circuit, comprising N PSWs, wherein:
a first input end and a second input end of a first PSW are respectively connected with a first enable signal and a second enable signal, a first input end and a second input end of an ith PSW are respectively connected with a first output end and a second output end of an i-1 th PSW, and a first output end and a second output end of an Nth PSW respectively output a first confirmation signal and a second confirmation signal;
wherein i and N are integers, i is more than 1 and less than or equal to N, the first enable signal and the second enable signal are two enable signals separated by a preset time delay, each PSW comprises a first diode, a second diode, a third diode, a fourth diode, a first switch unit with controllable on-off and a second switch unit with controllable on-off, and in each PSW:
the control end of the first switch unit is connected with the corresponding first input end through the corresponding first diode, the control end of the first switch unit is connected with the corresponding first output end through the corresponding second diode, the first end of the first switch unit is connected with a public power supply, and the second end of the switch unit is connected with the corresponding first-class driving device;
the control end of the second switch unit is connected with the corresponding second input end through the corresponding third diode, the control end of the second switch unit is connected with the corresponding second output end through the corresponding fourth diode, the first end of the second switch unit is connected with the public power supply, and the second end of the second switch unit is connected with the corresponding second-class driving element;
the power domain switch control circuit further comprises:
a first power domain including N first-type driving elements, each of the first-type driving elements having a driving state controlled by a corresponding first switching unit;
and the second power domain comprises N second-type driving elements, and each second-type driving element is controlled by the corresponding second switch unit to control the driving state.
2. The power domain switch control circuit of claim 1, wherein the first enable signal and the second enable signal are two enable signals generated based on a configuration register.
3. The power domain switch control circuit of claim 2, wherein the first switch unit and the second switch unit are both PMOS transistors.
4. A power domain switch control method, applied to the power domain switch control circuit of any one of claims 1 to 3, comprising:
acquiring a control parameter, wherein the control parameter comprises a preset time delay between a first enabling signal and a second enabling signal;
and applying the first enabling signal and the second enabling signal to the power domain switch control circuit according to the control parameter so as to control N PSWs, wherein N is an integer greater than 1.
5. The method according to claim 4, wherein the applying the first enable signal and the second enable signal to the power domain switch control circuit according to the control parameter to control the process of the N PSWs comprises:
applying the first enable signal to the power domain switch control circuit;
and after waiting for the preset time delay, applying the second enabling signal to the power domain switch control circuit.
6. The power domain switch control method of claim 4, wherein the control parameters further comprise a feedback delay obtained by subtracting a signal transmission delay from the preset delay;
correspondingly, the applying the first enable signal and the second enable signal to the power domain switch control circuit according to the control parameter to control the processes of the N PSWs specifically includes:
applying the first enable signal to the power domain switch control circuit;
and when a first confirmation signal of the power domain switch control circuit is received, waiting for feedback time delay, and applying the second enabling signal to the power domain switch control circuit.
7. A power domain switch control chip comprising the power domain switch control circuit of any one of claims 1 to 3.
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| US11862228B2 (en) | 2021-07-16 | 2024-01-02 | Changxin Memory Technologies Inc. | Power supply circuit and memory |
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