CN110011654A - A kind of power domain ON-OFF control circuit, method and chip - Google Patents
A kind of power domain ON-OFF control circuit, method and chip Download PDFInfo
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- CN110011654A CN110011654A CN201910414743.6A CN201910414743A CN110011654A CN 110011654 A CN110011654 A CN 110011654A CN 201910414743 A CN201910414743 A CN 201910414743A CN 110011654 A CN110011654 A CN 110011654A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/266—Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
- H03K2217/0081—Power supply means, e.g. to the switch driver
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Abstract
This application discloses a kind of power domain ON-OFF control circuit, method and chips, including N number of PSW, wherein: the first input end and the second input terminal of first PSW is respectively connected to the first enable signal and the second enable signal, the first input end and the second input terminal of i-th PSW connect the first output end and second output terminal of (i-1)-th PSW respectively, and the first output end and second output terminal of n-th PSW exports the first confirmation signal and the second confirmation signal respectively；First enable signal and the second enable signal are separated by default time delay, and each PSW includes first switch unit and second switch unit, control on-off by corresponding first input end and the second input terminal respectively.By upper; it is not interfere with each other in the application by the on-off of first switch unit and the on-off of the second switch unit controlled by the second enable signal of the control of the first enable signal; it is poor there are actuation time, it avoids while on-off generates excessive electric current transient pulse, protect chip interior device.
Description
Technical field
This application involves chip design art field, in particular to a kind of power domain ON-OFF control circuit, method and chip.
Background technique
The low-power consumption of chip is studied, and usually based on transistor level, is started with from the source of analysis power consumption.CMOS
The power consumption of (Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductor) generally includes
Three parts, first is that dynamic power consumption caused by load capacitance charge and discharge；Second is that CMOS, during of short duration jump, P is managed and N
Pipe simultaneously turns on the short circuit current to be formed between power supply and ground and causes short-circuit dissipation, third is that the quiescent dissipation as caused by leakage current.
As shown in Figure 1, leakage current here specifically includes that grid leakage current, subthreshold current and drain diffusion junction leakage.
In existing Low Power Loss Solution, a chip is usually divided into multiple power domains, using PSW (power
Switch, power switch) control opening and shutting off for different electrical power domain, and then meet the needs of low-power consumption.
In same power domain, the big device of driving capability is divided into one group by us, referred to as big chain, and driving capability is small
Device be divided into one group, referred to as chainlet.As shown in Fig. 2, existing solution is using dual-input header type
PSW constitutes a control circuit, successively controls opening and shutting off for big chain and chainlet.Wherein, the first input end of PSW1 connects
Enable enable signal, the first input end of the first output termination PSW2 of PSW1, and so on, by the first output end of PSWn
The second input terminal of PSWn is connect, the second output terminal of PSWn connects the second input terminal of PSW (n-1), and so on, last ack letter
Number from the second output terminal of PSW1 export.Wherein the mother hvt PMOS of each PSW controls the driving element in big chain,
Daughter hvt PMOS controls the device in chainlet, to successively open before and after realizing chainlet and big chain, chip is effectively reduced
Instantaneous power.
Inside PSW, it is 0.7ns that signal, which is transmitted to NSLEEPOUT maximum delay from NSLEEPIN, from current PSW's
Also there is delay during the NSLEEPIN of NSLEEPINOUT to next PSW, but relative to the former, this delay time can be neglected
Slightly.Assuming that there is 1,000,000 gate devices that can estimate big chain and chainlet in a power domain, first the post-opening time difference is about
350us.Power domain All Drives part, All Drives part while power-on and power-off wink are successively opened within the time difference small in this way
Between, since there are leakage currents, the biggish transient current pulse of amplitude can be generated, there are breakdown wind so as to cause part of devices
Danger.
Therefore, how to provide a kind of scheme of solution above-mentioned technical problem is that current those skilled in the art need to solve
Problem.
Summary of the invention
In view of this, the application's is designed to provide a kind of lesser power domain switch control electricity of transient current pulse
Road, method and chip.Its concrete scheme is as follows:
A kind of power domain ON-OFF control circuit, including N number of PSW, in which:
The first input end and the second input terminal of first PSW is respectively connected to the first enable signal and the second enabled letter
Number, the first input end and the second input terminal of i-th PSW connect the first output end and second of (i-1)-th PSW respectively
Output end, the first output end and second output terminal of PSW described in n-th export the first confirmation signal and the second confirmation letter respectively
Number；
Wherein i and N is integer, and 1 < i≤N, first enable signal are separated by pre- with second enable signal
If two enable signals of time delay, each PSW includes first switch unit and second switch unit, respectively by corresponding
First input end and the second input terminal control on-off.
Preferably, the power domain ON-OFF control circuit further include:
The first power domain including N number of first kind driving element, each first kind driving element is respectively by corresponding
First switch unit controls driving condition；
Second source domain including N number of second class driving element, each second class driving element is respectively by corresponding
Second switch unit controls driving condition.
Preferably, the control terminal of the first switch unit of each PSW connects corresponding first input end and first defeated
Outlet, the first end and second end of first switch unit are sequentially connected corresponding public power and corresponding first kind driving member
Part；
The control terminal of the second switch unit of each PSW connects corresponding second input terminal and second output terminal,
The first end and second end of second switch unit is sequentially connected the public power and corresponding second class driving element.
Preferably, each PSW further includes first diode, the second diode, third diode and the 4th diode；
Wherein:
Pass through corresponding first between the control terminal of the first switch unit of each PSW and corresponding first input end
Diode connection, is connected between control terminal and corresponding first output end by corresponding second diode；
Pass through corresponding third between the control terminal of the second switch unit of each PSW and corresponding second input terminal
Diode connection, is connected between control terminal and corresponding second output terminal by corresponding 4th diode.
Preferably, first enable signal and second enable signal are to be made based on two that configuration register generates
It can signal.
Preferably, the first switch unit and the second switch unit are PMOS tube.
Correspondingly, the invention also discloses a kind of power domain method of controlling switch, comprising:
Control parameter is obtained, the control parameter includes the default time delay between the first enable signal and the second enable signal；
According to the control parameter, applying first enable signal and described second to power domain ON-OFF control circuit makes
Energy signal, to control N number of PSW, wherein N is the integer greater than 1.
Preferably, described according to the control parameter, first enable signal is applied to power domain ON-OFF control circuit
It is specifically included with second enable signal with controlling the process of N number of PSW:
First enable signal is applied to the power domain ON-OFF control circuit；
It is delayed when waiting described default, second enable signal is applied to the power domain ON-OFF control circuit.
Preferably, when the control parameter further includes the feedback obtained according to the default time delay subtraction signal propagation delay time
Prolong；
Correspondingly, it is described according to the control parameter, it is enabled that described first is applied to the power domain ON-OFF control circuit
Signal and second enable signal are specifically included with controlling the process of N number of PSW:
First enable signal is applied to the power domain ON-OFF control circuit；
When the first confirmation signal for receiving the power domain ON-OFF control circuit, feedback delay is waited, then to the electricity
Potential source ON-OFF control circuit applies second enable signal.
Correspondingly, the invention also discloses a kind of power domain switch control chip, including power supply domain switch as described above
Control circuit.
This application discloses a kind of power domain ON-OFF control circuits, including N number of PSW, in which: the of first PSW
One input terminal and the second input terminal are respectively connected to the first enable signal and the second enable signal, the first input of i-th of PSW
End and the second input terminal connect the first output end and second output terminal of (i-1)-th PSW respectively, and first of PSW described in n-th
Output end and second output terminal export the first confirmation signal and the second confirmation signal respectively；Wherein i and N are integer, and 1 < i
≤ N, first enable signal and second enable signal are to be separated by two enable signals of default time delay, each described
PSW includes first switch unit and second switch unit, is controlled respectively by corresponding first input end and the second input terminal logical
It is disconnected.
By upper, by the on-off of the first switch unit of the first enable signal control and by the second enable signal control in the application
The on-off of the second switch unit of system is not interfere with each other, and because there are the times between the first enable signal and the second enable signal
Difference, therefore the on-off of first switch unit and the on-off of second switch unit are poor there are actuation time, avoid first switch unit
On-off generates excessive electric current transient pulse simultaneously in a very short period of time with second switch unit, reduces chip power-consumption, protects
Chip interior device has been protected, the reliability of chip is improved.
Detailed description of the invention
In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of application for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is the composition schematic diagram of CMOS leakage current in the prior art；
Fig. 2 is a kind of structure distribution figure of common power domain ON-OFF control circuit in the prior art；
Fig. 3 is a kind of structure distribution figure of power domain ON-OFF control circuit in the embodiment of the present application；
Fig. 4 is a kind of structure distribution figure of specific power domain ON-OFF control circuit in the embodiment of the present application；
Fig. 5 is a kind of step flow chart of power domain method of controlling switch in the embodiment of the present application；
Fig. 6 is a kind of step flow chart of specific power domain method of controlling switch in the embodiment of the present application；
Fig. 7 is the step flow chart of another specific power domain method of controlling switch in the embodiment of the present application.
Specific embodiment
Below in conjunction with the attached drawing in the embodiment of the present application, technical solutions in the embodiments of the present application carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of embodiments of the present application, instead of all the embodiments.It is based on
Embodiment in the application, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall in the protection scope of this application.
In the prior art, the opening time difference of All Drives part is minimum in power domain, generates the instantaneous arteries and veins of biggish electric current
Punching, it is breakdown to may cause part of devices.The control of driving element is separated by the enable signal of default time delay by two in the application
Control, to avoid generating excessive electric current transient pulse, protects chip interior device.
The embodiment of the present application discloses a kind of power domain ON-OFF control circuit, including N number of PSW, shown in Figure 3, in which:
The first input end and the second input terminal of first PSW is respectively connected to the first enable signal enable1 and second and makes
Can signal enable2, the first input end and the second input terminal of i-th PSW connect respectively (i-1)-th PSW the first output end and
Second output terminal, the first output end and second output terminal of n-th PSW export the confirmation of the first confirmation signal ack1 and second respectively
Signal ack2；
Wherein i and N is integer, and 1 < i≤N, the first enable signal enable1 is with the second enable signal enable2
It is separated by two enable signals of default time delay, each PSW includes first switch unit and second switch unit, respectively by corresponding to
First input end and the second input terminal control on-off.
It is understood that the PSW used in the present embodiment is dual-input header type, each PSW is to fix
The integration module of circuit, in addition to first input end, the second input terminal, first switch unit, second switch list in the integration module
Further include other relevant auxiliary elements other than member, the first output end, second output terminal, such as prevents the diode flow backwards, the
One switch unit and the output signal end of second switch unit etc..
Wherein, the concrete type of first switch unit and second switch unit, either certain is with controllable switch spy
The circuit unit of property, is also possible to controlled tr tube, such as metal-oxide-semiconductor, triode etc., usually can choose PMOS tube.
It should be noted that the control of the on-off of first switch unit and second switch unit itself is respectively by its place PSW
First input end, the control of the second input terminal, namely the above first switch unit in each PSW and second switch unit point
On-off is not controlled by corresponding first input end and the second input terminal, and the on-off shape of first switch unit and second switch unit
State can be used as the other elements that signal is gone in control power domain, and the on off operating mode is by first switch unit or second switch unit
Output signal end output.
Specifically, it is obvious that the first enable signal enable1 controls first in all N number of PSW in Fig. 3
Switch unit, the second enable signal enable2 control the second switch unit in all N number of PSW.The prior art shown in Fig. 2
Mother hvt PMOS and daughter hvt PMOS is controlled merely with an enable signal enable, so that they are extremely short
Time in sequentially turn on, excessive current impulse is generated in circuit, there are the breakdown hidden danger of internal components；And the present embodiment
The on state of middle first switch unit and second switch unit these two types PMOS, respectively by the first enable signal enable1 and
The time difference of the two enable signal independent controls of the second enable signal enable2, two class switching means conductives is enabled by two
The time difference of signal, that is, default time delay determine, select appropriate default time delay, in one enable signal of transmission, wait correspond to
This kind of switch units all turn on after, retransmit another enable signal, the corresponding switch unit of conducting, avoid all
Switch unit simultaneously turns in a very short period of time, so that electric current transient pulse is smaller, it is internal to eliminate transient current breakdown
The possibility of device.Simultaneously because electric current transient pulse is smaller, the relevant device power consumption of power domain ON-OFF control circuit is than existing skill
Art is lower, realizes the purpose of low-power consumption.
It is understood that not restricted first enable signal enable1 and the second enable signal enable2 here
Precedence relationship presets the setting of time delay, it is desirable that first makes as long as the time interval of two enable signals is default time delay
In the transmission process of power domain ON-OFF control circuit, second enable signal does not start to transmit energy signal.
Further, none unified standard of the length of the default time delay of two enable signals, because each specific
Voltage class and device count are all different in project, so needing to be gone to determine according to specific IR drop simulation result default
Time delay, magnitude is generally all in Millisecond.Specifically, the numerical value of default time delay, it generally can reference voltage grade, the model of PSW
The driving pair of the number, each first switch unit and second switch unit of PSW quantity in parameter, power domain ON-OFF control circuit
The factors such as the model parameter of elephant carry out selection setting；Specifically, the embodiment of the present application can obtain circuit relevant to default time delay
Parameter, using being determined that the calculation formula of circuit parameter priority level obtains default time delay or other control amounts；In addition, may be used also
Verification experimental verification is carried out, detects individual first enable signal enable1, individual second enable signal enable2 in N number of PSW
In signal propagation delay time, detect two kinds of switch units driven object waited during driving electric current stablize need when
Between, further according to these time data and its priority, control parameter, the control parameter or default time delay of final test setting are set
The requirement whether being able to achieve in the present embodiment.Specific test method can also be with either carry out on specific circuit in kind
It is completed by simulation circuit model.
It is understood that the default time delay can be set in advance in a control program, can also scene carry out regulation and match
Set, or in advance set in a control program after, be adjusted again according to field circuit situation.Specifically, the first enable signal
Enable1 and the second enable signal enable2 is generally two enable signals generated based on configuration register, presets time delay
It is arranged and also stops on the state modulator to configuration register.
By upper, by the on-off of the first switch unit of the first enable signal control and by the second enable signal control in the application
The on-off of the second switch unit of system is not interfere with each other, and because there are the times between the first enable signal and the second enable signal
Difference, therefore the on-off of first switch unit and the on-off of second switch unit are poor there are actuation time, avoid first switch unit
On-off generates excessive electric current transient pulse simultaneously in a very short period of time with second switch unit, reduces chip power-consumption, protects
Chip interior device has been protected, the reliability of chip is improved.
The embodiment of the present application discloses a kind of specific power domain ON-OFF control circuit, relative to a upper embodiment, this reality
It applies example and further instruction and optimization has been made to technical solution.It is specific:
It is shown in Figure 4, power domain ON-OFF control circuit further include:
The first power domain including N number of first kind driving element, each first kind driving element is respectively by corresponding first
Switch unit controls driving condition；
Second source domain including N number of second class driving element, each second class driving element is respectively by corresponding second
Switch unit controls driving condition.
Specifically, the control terminal connection of the first switch unit of each PSW is corresponding in the connection relationship of circuit devcie
First input end and the first output end, the first end and second end of first switch unit are sequentially connected corresponding public power
TVDD and corresponding first kind driving element；The control terminal of the second switch unit of each PSW connects corresponding second input terminal
And second output terminal, the first end and second end of second switch unit are sequentially connected corresponding public power TVDD and corresponding
Second class driving element.Here it is controlled in the second end of first switch unit and second switch unit, that is, a upper embodiment
The output signal end of driving element.It is understood that the corresponding output port of a certain modular unit or module list in this section
Member actually refers to and the output port or modular unit in the PSW where the modular unit.As can be seen that first switch in Fig. 4
Unit and second switch unit are PMOS tube, and by taking PMOS tube as an example, then the grid of PMOS tube, source electrode and drain electrode are corresponding in turn to
The control terminal of first switch unit or second switch unit, first end and second end.
Further, each PSW further includes first diode NSLEEPIN1, the second diode NSLEEPOUT1,
Three diode NSLEEPIN2 and the 4th diode NSLEEPOUT2 prevent refluence phenomenon from damaging to circuit；Wherein:
Pass through corresponding first between the control terminal of the first switch unit of each PSW and corresponding first input end
Diode NSLEEPIN1 connection passes through corresponding second diode between control terminal and corresponding first output end
NSLEEPOUT1 connection；
Pass through corresponding third between the control terminal of the second switch unit of each PSW and corresponding second input terminal
Diode NSLEEPIN2 connection passes through corresponding 4th diode between control terminal and corresponding second output terminal
NSLEEPOUT2 connection.
It can be with it is understood that other than the circuit structure for being previously mentioned PSW corresponding with Fig. 4, in the present embodiment
Using the PSW of other structures, herein with no restriction.
Further, the division of the first power domain and second source domain, general total drive according to driving element in power domain
Dynamic power, can divide into chainlet and big chain for the first power domain and second source domain.In addition to this, driving element in power domain
Respective driving power can also be compared and divide.
In a kind of specific embodiment, the driving element of same power bracket is belonged into same power domain, at this time
A kind of driving element is specially driving element of the driving power in the first power bracket, and the second class driving element is specially to drive function
Rate is in the driving element of the second power bracket, and the first power bracket and the second power bracket are not overlapped mutually, but same power model
Enclose the set that can refer to several power intervals, that is to say, that the first power bracket and the second power bracket are on power number axis
The case where being likely to occur intersection is all that the present embodiment allows.
Other than the above-mentioned this method divided according to driving power to power domain, other parameters item can also be utilized
Part or design requirement, such as function, the physical location of driving element, by all driving elements be divided into first kind driving element and
Second class driving element, to obtain the first power domain and second source domain.
It is understood that first kind driving element, the second class driving element in the present embodiment, are referred to Fig. 4's
Circuit structure is designed, and also can choose other driving circuits, does not do detailed structure qualification here.
Correspondingly, this application discloses a kind of power domain method of controlling switch, it is shown in Figure 5, comprising:
S11: control parameter is obtained；
Wherein, when control parameter includes default between the first enable signal enable1 and the second enable signal enable2
Prolong；
Specifically, the present embodiment can be applied to power domain ON-OFF control circuit described in foregoing embodiments, can also answer
It include in the power domain ON-OFF control circuit of N number of PSW for other.The numerical value of default time delay, generally joins according to the model of PSW
Number, in power domain ON-OFF control circuit PSW quantity number, each first switch unit and second switch unit driven object
The factors such as model parameter carry out selection setting.
Therefore, the control parameter in the present embodiment is in addition to the default time delay that is directly arranged, it is also an option that other and time
Relevant control amount, to realize two non-interfering purposes of enable signal in the present embodiment.
Specifically, the embodiment of the present application can obtain circuit parameter relevant to default time delay, using circuit parameter has been determined
The calculation formula of priority level obtains default time delay or other control amounts；Verification experimental verification, measuring and calculating individual first can also be carried out
The signal propagation delay time of enable signal enable1, individual second enable signal enable2 in N number of PSW, two kinds of detection are opened
The driven object for closing unit waits electric current to stablize the time needed during driving, further according to these time data and its preferentially
Grade setting control parameter.
S12: according to control parameter, applying the first enable signal enable1 and second to power domain ON-OFF control circuit makes
Energy signal enable2, to control N number of PSW, wherein N is the integer greater than 1.
Specifically, to the first enable signal enable1 and the second enable signal of the application of power domain ON-OFF control circuit
The two enable signals of enable2 passed this N number of PSW, on the actually each PSW of the two enable signal independent controls
A part.By above it can be appreciated that the first enable signal enable1 controls the first switch unit in all N number of PSW,
Second enable signal enable2 controls the second switch unit in all N number of PSW, power domain switch control electricity in the present embodiment
The wiring construction on road is determined and is not interfere with each other between two enable signals, and an enable signal in the prior art will not occur
Enable controls all first switch units and second switch unit, so that all switch units are opened, is electric in very short time
The phenomenon that excessive current impulse is generated in road.Therefore, as long as the present embodiment is provided with appropriate default time delay, one is being sent
Enable signal after enabling corresponding switch unit all turn on, retransmits another enable signal and its corresponding switch list is connected
Member, so that it may avoid all switch units from acting in a very short period of time, so that electric current transient pulse is smaller.
Specifically, the present embodiment does not limit the successive pass of the first enable signal enable1 and the second enable signal enable2
System, as long as the time interval of two enable signals is default time delay.
By taking the power domain ON-OFF control circuit of foregoing embodiments as an example, it can see by the physical circuit topological diagram of Fig. 4, the
One switch unit is used to drive the first kind driving element of the first power domain, and second switch unit is for driving second source domain
Second class driving element, two kinds of driving elements are classified with driving power, wiring, can be classification with driving power range according to
According to, it can also be using the function of driving element, physical location as classification foundation, against existing technologies, including total driving power is larger
Power domain can be described as big chain, total lesser power domain of driving power can be described as chainlet.
By upper, by the on-off of the first switch unit of the first enable signal control and by the second enable signal control in the application
The on-off of the second switch unit of system is not interfere with each other, and because there are the times between the first enable signal and the second enable signal
Difference, therefore the on-off of first switch unit and the on-off of second switch unit are poor there are actuation time, avoid first switch unit
On-off generates excessive electric current transient pulse simultaneously in a very short period of time with second switch unit, reduces chip power-consumption, protects
Chip interior device has been protected, the reliability of chip is improved.
The embodiment of the present application discloses a kind of specific power domain method of controlling switch, relative to a upper embodiment, this reality
It applies example and further instruction and optimization has been made to technical solution.Specifically, shown in Figure 6:
S21: control parameter is obtained；
Wherein, when control parameter includes default between the first enable signal enable1 and the second enable signal enable2
Prolong；
S22: the first enable signal enable1 is applied to power domain ON-OFF control circuit；
S23: delaying when waiting default, applies the second enable signal enable2 to power domain ON-OFF control circuit.
In the present embodiment, clear stipulaties the first enable signal enable1's and the second enable signal enable2 is successive suitable
Sequence waits default time delay, directly the second enable signal enable2 of application after applying the first enable signal enable1, in entire electricity
The wiring of source domain ON-OFF control circuit is correct good, that in the case where line device failure, the present embodiment is not simple and easy, it is only necessary to right
The actuation time of first enable signal enable1 positions, and can derive the actuation time of the second enable signal enable2, be
A kind of control method of efficient quick.
The embodiment of the present application discloses a kind of specific power domain method of controlling switch, relative to a upper embodiment, this reality
It applies example and further instruction and optimization has been made to technical solution.Specifically, shown in Figure 7:
S31: control parameter is obtained；Control parameter further includes being obtained according to the default time delay subtraction signal propagation delay time
Feedback delay；
S32: the first enable signal enable1 is applied to power domain ON-OFF control circuit；
S33: as the first confirmation signal ack1 for receiving power domain ON-OFF control circuit, waiting feedback delay, then to electricity
Potential source ON-OFF control circuit applies the second enable signal enable2.
Compared to a upper embodiment, the present embodiment also demonstrates power domain switch control during applying enable signal
Whether the wiring of circuit is correct reliable: if the signal path of the first enable signal enable1 is completely correct, can receive the
One confirmation signal ack1；If the signal path of the second enable signal enable2 is completely correct, the second confirmation letter can be received
Number ack2；If not receiving a certain confirmation signal, mean that corresponding signal path is likely to occur problem, needs to examine again
It tests, excludes the route hidden danger in power domain ON-OFF control circuit.That is, after receiving the first confirmation signal ack1, then apply
Add the second enable signal enable2, the system reliability of entire power domain ON-OFF control circuit can be improved.
Specifically, feedback delay is different with default time delay.Signal propagation delay time must be taken into consideration in the setting of default time delay, also
Be from the first enable signal enable1 is sent to the time for receiving the first confirmation signal ack1, made from transmission second
Can signal enable2 to the time for receiving the second confirmation signal ack2, and from receiving the first confirmation signal in the present embodiment
Ack1 starts timing, therefore does not include signal propagation delay time in feedback delay, and the electric current for being only thought of as the driven object of PMOS is steady
It is qualitative to set aside some time.
Further, since feedback delay is related to three signals: the first enable signal enable1, the first confirmation signal
Ack1 and the second enable signal enable2, therefore the present embodiment is executed in step and is above slightly different with a upper embodiment, but same
When embodiment improves the reliabilities of power domain ON-OFF control circuit, this is the no advantage of a upper embodiment.
Correspondingly, disclosed herein as well is a kind of power domain switch control chip, including the electricity as described in foregoing embodiments
Source domain ON-OFF control circuit.
Specifically, power domain switch control chip is to be integrated with the chip of power domain ON-OFF control circuit, specific power domain
The detail section of ON-OFF control circuit is referred to the related content in foregoing embodiments, and details are not described herein again.
Wherein, the power domain switch control chip in the present embodiment has identical as above power domain ON-OFF control circuit
Beneficial effect, details are not described herein again.
Finally, it is to be noted that, herein, relational terms such as first and second and the like be used merely to by
One entity or operation are distinguished with another entity or operation, without necessarily requiring or implying these entities or operation
Between there are any actual relationship or orders.Moreover, the terms "include", "comprise" or its any other variant meaning
Covering non-exclusive inclusion, so that the process, method, article or equipment for including a series of elements not only includes that
A little elements, but also including other elements that are not explicitly listed, or further include for this process, method, article or
The intrinsic element of equipment.In the absence of more restrictions, the element limited by sentence "including a ...", is not arranged
Except there is also other identical elements in the process, method, article or apparatus that includes the element.
A kind of power domain ON-OFF control circuit, method and chip provided herein are described in detail above,
Specific examples are used herein to illustrate the principle and implementation manner of the present application, and the explanation of above embodiments is only used
The present processes and its core concept are understood in help；At the same time, for those skilled in the art, according to the application's
Thought, there will be changes in the specific implementation manner and application range, in conclusion the content of the present specification should not be construed as
Limitation to the application.
Claims (10)
1. a kind of power domain ON-OFF control circuit, which is characterized in that including N number of PSW, in which:
The first input end and the second input terminal of first PSW is respectively connected to the first enable signal and the second enable signal,
The first input end and the second input terminal of i-th PSW connects the first output end of (i-1)-th PSW and second defeated respectively
Outlet, the first output end and second output terminal of PSW described in n-th export the first confirmation signal and the second confirmation signal respectively；
Wherein i and N is integer, and 1 < i≤N, first enable signal and second enable signal is when being separated by default
Two enable signals prolonged, each PSW includes first switch unit and second switch unit, respectively by corresponding first
Input terminal and the second input terminal control on-off.
2. power domain ON-OFF control circuit according to claim 1, which is characterized in that further include:
The first power domain including N number of first kind driving element, each first kind driving element is respectively by corresponding first
Switch unit controls driving condition；
Second source domain including N number of second class driving element, each second class driving element is respectively by corresponding second
Switch unit controls driving condition.
3. power domain ON-OFF control circuit according to claim 2, which is characterized in that
The corresponding first input end of control terminal connection of the first switch unit of each PSW and the first output end, first
The first end and second end of switch unit is sequentially connected corresponding public power and corresponding first kind driving element；
Corresponding second input terminal of control terminal connection and second output terminal of the second switch unit of each PSW, second
The first end and second end of switch unit is sequentially connected the public power and corresponding second class driving element.
4. power domain ON-OFF control circuit according to claim 3, which is characterized in that each PSW further includes the one or two
Pole pipe, the second diode, third diode and the 4th diode；Wherein:
Pass through corresponding one or two pole between the control terminal of the first switch unit of each PSW and corresponding first input end
Pipe connection, is connected between control terminal and corresponding first output end by corresponding second diode；
Pass through corresponding three or two pole between the control terminal of the second switch unit of each PSW and corresponding second input terminal
Pipe connection, is connected between control terminal and corresponding second output terminal by corresponding 4th diode.
5. according to claim 1 to any one of 4 power domain ON-OFF control circuits, which is characterized in that the described first enabled letter
Number and second enable signal be two enable signals generated based on configuration register.
6. power domain ON-OFF control circuit according to claim 5, which is characterized in that the first switch unit and described
Two switch units are PMOS tube.
7. a kind of power domain method of controlling switch characterized by comprising
Control parameter is obtained, the control parameter includes the default time delay between the first enable signal and the second enable signal；
According to the control parameter, first enable signal and the second enabled letter are applied to power domain ON-OFF control circuit
Number, to control N number of PSW, wherein N is the integer greater than 1.
8. power domain method of controlling switch according to claim 7, which is characterized in that it is described according to the control parameter, it is right
Power domain ON-OFF control circuit applies first enable signal and second enable signal, to control the process of N number of PSW,
It specifically includes:
First enable signal is applied to the power domain ON-OFF control circuit；
It is delayed when waiting described default, second enable signal is applied to the power domain ON-OFF control circuit.
9. power domain method of controlling switch according to claim 7, which is characterized in that the control parameter further includes according to institute
State the feedback delay that default time delay subtraction signal propagation delay time obtains；
Correspondingly, it is described according to the control parameter, first enable signal is applied to the power domain ON-OFF control circuit
It is specifically included with second enable signal with controlling the process of N number of PSW:
First enable signal is applied to the power domain ON-OFF control circuit；
When the first confirmation signal for receiving the power domain ON-OFF control circuit, feedback delay is waited, then to the voltage source
ON-OFF control circuit applies second enable signal.
10. a kind of power domain switch control chip, which is characterized in that opened including the power domain as described in any one of claim 1 to 6
Close control circuit.
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| CN201910414743.6A CN110011654B (en) | 2019-05-17 | 2019-05-17 | Power domain switch control circuit, method and chip |
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|---|---|---|---|
| CN201910414743.6A CN110011654B (en) | 2019-05-17 | 2019-05-17 | Power domain switch control circuit, method and chip |
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| CN110011654B CN110011654B (en) | 2022-10-11 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023284122A1 (en) * | 2021-07-16 | 2023-01-19 | 长鑫存储技术有限公司 | Power source circuit and memory |
| US11862228B2 (en) | 2021-07-16 | 2024-01-02 | Changxin Memory Technologies Inc. | Power supply circuit and memory |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106849041A (en) * | 2017-03-27 | 2017-06-13 | 上海华力微电子有限公司 | A kind of surge current control module and its method |
| CN207968328U (en) * | 2018-03-09 | 2018-10-12 | 上海岭芯微电子有限公司 | A kind of booster type synchronization DC-DC circuit |
| CN108964648A (en) * | 2018-07-26 | 2018-12-07 | 郑州云海信息技术有限公司 | A kind of time sequence control device and method |
-
2019
- 2019-05-17 CN CN201910414743.6A patent/CN110011654B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106849041A (en) * | 2017-03-27 | 2017-06-13 | 上海华力微电子有限公司 | A kind of surge current control module and its method |
| CN207968328U (en) * | 2018-03-09 | 2018-10-12 | 上海岭芯微电子有限公司 | A kind of booster type synchronization DC-DC circuit |
| CN108964648A (en) * | 2018-07-26 | 2018-12-07 | 郑州云海信息技术有限公司 | A kind of time sequence control device and method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023284122A1 (en) * | 2021-07-16 | 2023-01-19 | 长鑫存储技术有限公司 | Power source circuit and memory |
| US11862228B2 (en) | 2021-07-16 | 2024-01-02 | Changxin Memory Technologies Inc. | Power supply circuit and memory |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110011654B (en) | 2022-10-11 |
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