CN102413001A - Intelligent BYPASS system - Google Patents
Intelligent BYPASS system Download PDFInfo
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- CN102413001A CN102413001A CN2011104537318A CN201110453731A CN102413001A CN 102413001 A CN102413001 A CN 102413001A CN 2011104537318 A CN2011104537318 A CN 2011104537318A CN 201110453731 A CN201110453731 A CN 201110453731A CN 102413001 A CN102413001 A CN 102413001A
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Abstract
The invention discloses an intelligent BYPASS system which mainly comprises a network interface circuit (1); and the intelligent BYPASS system is characterized by also comprising a relay switching circuit (2), a GPIO (general purpose input/output) logic control circuit (3) and a power supply circuit (4), wherein the relay switching circuit (2) is used for controlling the network switch state of the network interface circuit (1); the GPIO logic control circuit (3) is used for providing control signals for the relay switching circuit (2) so as to control the connection and disconnection of a relay in the relay switching circuit (2); and the power supply circuit (4) is used for providing a working power supply for the relay switching circuit (2) and the GPIO logic control circuit (3). By using the intelligent BYPASS system disclosed by the invention, an effect that the BYPASS system can be shut off or started under the condition that a device is not electrified can be achieved; and after the device is electrified, the BYPASS system also can be shut off or started, thereby providing a strong support for firewall servers.
Description
Technical field
The present invention relates to field of network communication, specifically be meant a kind of intelligent BYPASS system.
Background technology
In scientific and technological high speed development today, the operation of network and enterprise is closely related, and in order to ensure the safety of enterprise in network, SOCKS server obtains number of applications; If SOCKS server breaks down, like deadlock, sudden power or the like, will interrupt the network path of enterprise, influence enterprise and normally run, cause very big loss.
In order to overcome the above problems, a lot of SOCKS server suppliers have expected that the method for use BYPASS (bypass) guarantees the unimpeded continuously of enterprise network.At present, existing BYPASS realizes through the mode that power supply triggers, yet adopts this mode; Generally be not have under the situation of energising at equipment, the BYPASS function is opened, and equipment is in case after the energising; BYPASS is adjusted into closed condition immediately, and BYPASS just can not realize Based Intelligent Control.
Summary of the invention
The objective of the invention is to overcome present BYPASS system does not have under the situation of energising at equipment, and the BYPASS function can be opened, and in case will be adjusted into closed condition immediately after the energising, can not realize the defective of Based Intelligent Control, and a kind of intelligent BYPASS is provided system.
The present invention realizes through following technical scheme: a kind of intelligent BYPASS system; Mainly form by network interface circuit; Also comprise the relay switching circuit that is used for Control Network interface circuit network switching state simultaneously; For relay switching circuit provides control signal with repeat circuit conducting of control relay switching circuit and the GPIO logic control circuit that ends, for relay switching circuit and GPIO logic control circuit provide the power-supplying circuit of working power to form.
Described network interface circuit is made up of LANA port and LANB port; Described LANA port is made up of RJ45 connector, resistance R 50, resistance R 51 and capacitor C 56; Be connected with the TX-port with the TX+ of RJ45 connector respectively after resistance R 51 and resistance R 50 serial connections; One end of capacitor C 56 links to each other with the tie point of resistance R 50 with resistance R 51, and its other end is ground connection then.
Described relay switching circuit is then for reaching a switching circuit of being formed with door by resistance, metal-oxide-semiconductor, relay.
Described GPIO logic control circuit is made up of resistance R 6, metal-oxide-semiconductor Q4 and diode D1; Resistance R 6 is in parallel with diode D1, and its P utmost point then is connected with metal-oxide-semiconductor Q4.
Described power-supplying circuit comprises power supply chip Q1, and resistance R 1 is connected the other end ground connection of resistance R 2 with resistance R 2 its tie points of serial connection back with power supply chip Q1; The other end of resistance R 1 is connected with power supply chip Q1; One end of capacitor C 1 is connected with power supply chip Q1, and its other end is ground connection then.
Described logic control switch circuit is formed by resistance, metal-oxide-semiconductor, relay and with door, wherein the VBYPASS power supply through after resistance R 12 and the resistance R 13 respectively with door U1, be connected with a U2; GPIOB, GPIOC be connected respectively to door U1 and with 1 pin of door U2; With door U1, with the door U2 3 pin ground connection, with door U1, with the door U2 5 pin connect the VBYPASS power supply; Be connected respectively to the G utmost point of metal-oxide-semiconductor Q5, metal-oxide-semiconductor Q6 with door U1 with output pin 4 pin of door U2, the S utmost point ground connection of metal-oxide-semiconductor Q5 and metal-oxide-semiconductor Q6, the D utmost point of metal-oxide-semiconductor Q5 and metal-oxide-semiconductor Q6 is received the VBYPASS power supply through resistance R 9, resistance R 10;
The D utmost point of metal-oxide-semiconductor Q5 and metal-oxide-semiconductor Q6 is connected respectively to 1 pin and 8 pin of relay K 11 simultaneously; GPIOD is connected to the G utmost point of metal-oxide-semiconductor Q1; The VBYPASS power supply is connected to the D utmost point of metal-oxide-semiconductor Q1 through R11, and the D utmost point of metal-oxide-semiconductor Q1 is directly connected to 8 pin of relay K 1, and 1 pin of relay K 1 is directly connected to the VBYPASS power supply; 2 pin of relay K 11 are connected with 2 pin of 3 pin of relay K 1, relay K 4; 3 pin of relay K 11 are connected with 2 pin of 4 pin of relay K 1, relay K 2, and 7 pin of relay K 11 are connected with 7 pin of 6 pin of relay K 1, relay K 4, and 6 pin of relay K 11 are connected with 7 pin of 5 pin of relay K 1, relay K 2; 3,6 pin of relay K 2 are connected with 1,2 pin of LANA1 respectively, and 3,6 pin of relay K 4 are connected with 1,2 pin of LANB1 respectively.
The present invention compared with prior art has the following advantages and beneficial effect:
(1) the present invention is not only simple in structure, and realize with low cost, flexible operation.
(2) the present invention can be implemented in equipment does not have under the situation of energising, and this BYPASS system can close or open, and after the equipment energising, the function that this BYPASS system also can close or open is for SOCKS server provides strong support.
Description of drawings
Fig. 1 is an overall structure schematic block diagram of the present invention.
Fig. 2 is a network interface circuit structure chart of the present invention.
Fig. 3 is the structure chart of relay switching circuit.
Fig. 4 is a GPIO logic control circuit structure chart.
Fig. 5 is the power-supplying circuit structure chart.
Wherein, the Reference numeral title in the accompanying drawing is respectively:
The 1-network interface circuit, 2-relay switching circuit, 3-GPIO logic control circuit, 4-power-supplying circuit.
Embodiment
Below in conjunction with embodiment the present invention is done to specify further, but execution mode of the present invention is not limited thereto.
Embodiment
Shown in Fig. 1～5, the present invention includes network interface circuit 1, relay switching circuit 2, GPIO logic control circuit 3 and power-supplying circuit 4.Wherein, Network interface circuit 1 is made up of LANA and two network ports of LANB, and described LANA port is by the RJ45 connector, and resistance R 51, R50 and capacitor C 56 constitute; During connection, be connected with the TX-interface with the TX+ of RJ45 connector respectively after resistance R 51 and resistance R 50 serial connections; Between one end of capacitor C 56 and resistance R 51 and the resistance R 50, the other end is ground connection then.
Described network interface circuit is made up of LANA port and LANB port; Described LANA port is made up of RJ45 connector, resistance R 50, resistance R 51 and capacitor C 56; Be connected with the TX-port with the TX+ of RJ45 connector respectively after resistance R 51 and resistance R 50 serial connections; One end of capacitor C 56 links to each other with the tie point of resistance R 50 with resistance R 51, and its other end is ground connection then.
2 of described relay switching circuits are by resistance, metal-oxide-semiconductor, relay, forms with door, the VBYPASS power supply through resistance R 12, resistance R 13 after respectively with door U1, be connected with 2 pin of a U2; GPIOB, GPIOC be connected respectively to the door U1, with the door U2 1 pin; With door U1, with the door U2 3 pin ground connection; With door U1, connect the VBYPASS power supply, with door U1, be connected respectively to the 1 pin grid (the G utmost point) of metal-oxide-semiconductor Q5, metal-oxide-semiconductor Q6 with output pin 4 pin of door U2 with 5 pin of door U2; 2 pin source electrodes (the S utmost point) ground connection of metal-oxide-semiconductor Q5, metal-oxide-semiconductor Q6, the 3 pin drain electrodes (the D utmost point) of metal-oxide-semiconductor Q5, metal-oxide-semiconductor Q6 are received the VBYPASS power supply through resistance R 9, resistance R 10; 3 pin of metal-oxide-semiconductor Q5, metal-oxide-semiconductor Q6 drain electrodes (the D utmost point) simultaneously are connected respectively to 1 pin and 8 pin of relay K 11; GPIOD is connected to the 1 pin grid (the G utmost point) of metal-oxide-semiconductor Q1; The VBYPASS power supply is connected to the drain electrode (the D utmost point) of metal-oxide-semiconductor Q1 through resistance R 11; The 3 pin drain electrodes (the D utmost point) of metal-oxide-semiconductor Q1 are directly connected to 8 pin of relay K 1; 1 pin of relay K 1 is directly connected to the VBYPASS power supply, and 2 pin of relay K 11 are connected with 2 pin of 3 pin of relay K 1, relay K 4, and 3 pin of relay K 11 are connected with 2 pin of 4 pin of relay K 1, relay K 2; 7 pin of relay K 11 are connected with 7 pin of 6 pin of relay K 1, relay K 4; 6 pin of relay K 11 are connected with 7 pin of 5 pin of relay K 1, relay K 2, and 3,6 pin of relay K 2 are connected with 1,2 pin of LANA1 respectively, and 3,6 pin of relay K 4 are connected with 1,2 pin of LANB1 respectively.
Described GPIO logic control circuit is made up of resistance R 6, metal-oxide-semiconductor Q4 and diode D1; Resistance R 6 is in parallel with diode D1, and its P utmost point then is connected with metal-oxide-semiconductor Q4.
Described power-supplying circuit comprises power supply chip Q1, and resistance R 1 is connected the other end ground connection of resistance R 2 with resistance R 2 its tie points of serial connection back with power supply chip Q1; The other end of resistance R 1 is connected with power supply chip Q1; One end of capacitor C 1 is connected with power supply chip Q1, and its other end is ground connection then.
During operation; At first the power supply of VBYPASS power supply is provided by power supply chip Q1; And then the state of GPIOA, GPIOB, GPIOC, GPIOD is set, and control the conducting cut-off state of metal-oxide-semiconductor Q1, metal-oxide-semiconductor Q4, metal-oxide-semiconductor Q5 and metal-oxide-semiconductor Q6 through GPIOA, GPIOB, GPIOC, GPIOD; At last; The switch closed condition of coming control relay K1, K2, K4, K11 through the conducting cut-off state of metal-oxide-semiconductor Q1, metal-oxide-semiconductor Q4, metal-oxide-semiconductor Q5 and metal-oxide-semiconductor Q6, and then control the BYPASS state of LANA1 and LANB1 through the switch closed condition of relay K 1, relay K 2, relay K 4 and relay K 11.
For example:
Under operating system, close the BYPASS function: working procedure makes GPIOA=1, GPIOD=0.
The first step: power supply chip Q1 provides VBYPASS power supply;
Second step: GPIOA=1 → Q4 is in conducting state → RELAY_A=1, Cathode=0 → and, 3 pin of relay K 2, K4 and 4 pin, 5 pin and 6 pin conductings;
The 3rd step: 1 pin that GPIOD=0 → Q1 is in cut-off state → relay K 1 is 1, and 8 pin of relay K 1 are 2 pin and 3 pin, 6 pin and the 7 pin conductings of 1 → relay K 1;
The 4th step: the operation through 1,2 makes 1,2 pin of LANA1 and 1,2 pin of LANB1 break off; Promptly close the BYPASS function.
As stated, just can realize the present invention preferably.
Claims (6)
1. intelligent BYPASS system; It is characterized in that: mainly by network interface circuit (1), be used for relay switching circuit (2) that Control Network interface circuit (1) carries out the network switching state, for relay switching circuit (2) provides control signal with control relay switching circuit (2) repeat circuit conducting and the GPIO logic control circuit (3) that ends, and power-supplying circuit (4) composition of working power is provided for relay switching circuit (2) and GPIO logic control circuit (3).
2. a kind of intelligent BYPASS according to claim 1 system; It is characterized in that: described network interface circuit (1) is made up of LANA port and LANB port; Described LANA port is made up of RJ45 connector, resistance R 50, resistance R 51 and capacitor C 56; Be connected with the TX-port with the TX+ of RJ45 connector respectively after resistance R 51 and resistance R 50 serial connections, an end of capacitor C 56 links to each other with the tie point of resistance R 50 with resistance R 51, and its other end is ground connection then.
3. a kind of intelligent BYPASS according to claim 1 system is characterized in that: described relay switching circuit (2) is for by resistance, metal-oxide-semiconductor, relay and the logic control switch circuit formed with door.
4. a kind of intelligent BYPASS according to claim 1 system, it is characterized in that: described GPIO logic control circuit (3) is made up of resistance R 6, metal-oxide-semiconductor Q4 and diode D1; Resistance R 6 is in parallel with diode D1, and its P utmost point then is connected with metal-oxide-semiconductor Q4.
5. a kind of intelligent BYPASS according to claim 1 system, it is characterized in that: described power-supplying circuit (4) comprises power supply chip Q1, resistance R 1 is connected the other end ground connection of resistance R 2 with resistance R 2 its tie points of serial connection back with power supply chip Q1; The other end of resistance R 1 is connected with power supply chip Q1; One end of capacitor C 1 is connected with power supply chip Q1, and its other end is ground connection then.
6. a kind of intelligent BYPASS according to claim 3 system; It is characterized in that: described logic control switch circuit is formed by resistance, metal-oxide-semiconductor, relay and with door, wherein the VBYPASS power supply through after resistance R 12 and the resistance R 13 respectively with door U1, be connected with a U2; GPIOB, GPIOC be connected respectively to door U1 and with 1 pin of door U2; With door U1, with the door U2 3 pin ground connection, with door U1, with the door U2 5 pin connect the VBYPASS power supply; Be connected respectively to the G utmost point of metal-oxide-semiconductor Q5, metal-oxide-semiconductor Q6 with door U1 with output pin 4 pin of door U2, the S utmost point ground connection of metal-oxide-semiconductor Q5 and metal-oxide-semiconductor Q6, the D utmost point of metal-oxide-semiconductor Q5 and metal-oxide-semiconductor Q6 is received the VBYPASS power supply through resistance R 9, resistance R 10; The D utmost point of metal-oxide-semiconductor Q5 and metal-oxide-semiconductor Q6 is connected respectively to 1 pin and 8 pin of relay K 11 simultaneously; GPIOD is connected to the G utmost point of metal-oxide-semiconductor Q1; The VBYPASS power supply is connected to the D utmost point of metal-oxide-semiconductor Q1 through R11, and the D utmost point of metal-oxide-semiconductor Q1 is directly connected to 8 pin of relay K 1, and 1 pin of relay K 1 is directly connected to the VBYPASS power supply; 2 pin of relay K 11 are connected with 2 pin of 3 pin of relay K 1, relay K 4; 3 pin of relay K 11 are connected with 2 pin of 4 pin of relay K 1, relay K 2, and 7 pin of relay K 11 are connected with 7 pin of 6 pin of relay K 1, relay K 4, and 6 pin of relay K 11 are connected with 7 pin of 5 pin of relay K 1, relay K 2; 3,6 pin of relay K 2 are connected with 1,2 pin of LANA1 respectively, and 3,6 pin of relay K 4 are connected with 1,2 pin of LANB1 respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110453731.8A CN102413001B (en) | 2011-12-29 | 2011-12-29 | Intelligent BYPASS system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110453731.8A CN102413001B (en) | 2011-12-29 | 2011-12-29 | Intelligent BYPASS system |
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| Publication Number | Publication Date |
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| CN102413001A true CN102413001A (en) | 2012-04-11 |
| CN102413001B CN102413001B (en) | 2014-04-30 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201110453731.8A Active CN102413001B (en) | 2011-12-29 | 2011-12-29 | Intelligent BYPASS system |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103902928A (en) * | 2014-03-24 | 2014-07-02 | 同方计算机有限公司 | Network physical isolation device |
| CN116501397A (en) * | 2023-05-04 | 2023-07-28 | 深圳市联瑞电子有限公司 | Method for implementing BYPASS control by PCIe board card |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040228369A1 (en) * | 2003-05-14 | 2004-11-18 | George Simmons | Switching arrangement and method for communications platform |
| US20100005162A1 (en) * | 2008-07-04 | 2010-01-07 | Inventec Corporation | Bypass control module and network management apparatus thereof and control method of the network system |
| CN101626311A (en) * | 2008-07-10 | 2010-01-13 | 英业达股份有限公司 | Bypass control module and device and method for managing network |
| CN202042898U (en) * | 2011-05-17 | 2011-11-16 | 公安部第三研究所 | Program controlled bypass protection circuit of network equipment |
-
2011
- 2011-12-29 CN CN201110453731.8A patent/CN102413001B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040228369A1 (en) * | 2003-05-14 | 2004-11-18 | George Simmons | Switching arrangement and method for communications platform |
| US20100005162A1 (en) * | 2008-07-04 | 2010-01-07 | Inventec Corporation | Bypass control module and network management apparatus thereof and control method of the network system |
| CN101626311A (en) * | 2008-07-10 | 2010-01-13 | 英业达股份有限公司 | Bypass control module and device and method for managing network |
| CN202042898U (en) * | 2011-05-17 | 2011-11-16 | 公安部第三研究所 | Program controlled bypass protection circuit of network equipment |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103902928A (en) * | 2014-03-24 | 2014-07-02 | 同方计算机有限公司 | Network physical isolation device |
| CN116501397A (en) * | 2023-05-04 | 2023-07-28 | 深圳市联瑞电子有限公司 | Method for implementing BYPASS control by PCIe board card |
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| Publication number | Publication date |
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| CN102413001B (en) | 2014-04-30 |
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