CN203504601U - Transmission control circuit for high-level data link control (HDLC), and inter-board communication system - Google Patents
Transmission control circuit for high-level data link control (HDLC), and inter-board communication system Download PDFInfo
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- CN203504601U CN203504601U CN201320577102.0U CN201320577102U CN203504601U CN 203504601 U CN203504601 U CN 203504601U CN 201320577102 U CN201320577102 U CN 201320577102U CN 203504601 U CN203504601 U CN 203504601U
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Abstract
The utility model discloses a transmission control circuit for high-level data link control (HDLC). The transmission control circuit includes a drive circuit and a switching control circuit, wherein the drive circuit is in electrical signal connection with a CPU of an interface board where the drive circuit is located; an output end of the switching control circuit is in electrical signal connection with the drive circuit, and controls the operation of the drive circuit according to a reset logic switch. By using the HDLC transmission control circuit proposed in the embodiment of the utility model, the reliability and the stability of inter-board communication using an HDLC bus can be improved, and thus the management and the maintenance performance of network equipment are effectively improved. The utility model further discloses an inter-board communication system including the transmission control circuit.
Description
Technical field
The utility model relates to a kind of data sending controling circuit, relates to especially a kind of High-Level Data Link Control (High-Level Data Link Control, HDLC) sending controling circuit, belongs to communication technical field.
Background technology
Along with the development of network technology and the continuous expansion of communication equipment scale, the safety and reliability of the network equipment to be had higher requirement, communication between plates bus becomes one of key technology determining the reliable and stable work of the network equipment.Realize the comprehensive management to distinct device, need between master control borad and different interface board, set up a kind of communication mechanism, formation can be safeguarded manageable passage.
At present, in distributed real-time communication system, HDLC is because its busy line number is less, transmission data are reliably selected as the communication between plates bus of interactive maintenance information, be widely used between master control borad and interface board, it can meet point-to-point application can adapt to the application of point-to-multipoint again, in system running, multi-site shares a HDLC bus, master control borad sends order and configuration data by HDLC down going channel to each interface board, adopt the mode of poll to carry out acquisition interface plate information simultaneously, interface board feeds back current board state and other information by HDLC data feedback channel to master control borad, transmission rate maximum can reach 10Mbit/S.
When HDLC bus is used for communication between plates, because a bus connects master control borad and a plurality of interface board, but on synchronization up direction, it only allows an interface board to send data to bus, and whether each interface board allows to carry out data transmission and is controlled by the level of the I/O port output of the CPU of interface disc, , when allowing data transmission and not allowing data to send, the level of the I/O output of CPU is different, but such way can there are the following problems: when the network equipment powers on or when interface board powers on, CPU is in power up, as the I/O port of the CPU of the transmission Enable Pin of HDLC in output level nondeterministic statement, be the control that it is not subject to CPU, thus, not only may cause this interface board to send misdata bag to master control borad, serious words can affect other interface board and communicate by letter with master control borad.
Utility model content
The inter-board communication system that the technical problems to be solved in the utility model is to provide a kind of HDLC sending controling circuit and comprises this circuit, it can make to utilize the communication between plates of HDLC bus to have reliability and stability, thereby effectively improves the performance that administers and maintains of the network equipment.
For solving the problems of the technologies described above, the utility model provides a kind of High-Level Data Link Control HDLC sending controling circuit, comprise: drive circuit, ON-OFF control circuit, described drive circuit is connected with the CPU signal of telecommunication of this drive circuit place interface board, the output of described ON-OFF control circuit is connected with the described drive circuit signal of telecommunication, according to preset logic switch, controls described drive circuit works.
Further, the output of described ON-OFF control circuit is connected with the power input signal of telecommunication of described drive circuit.
Further, described ON-OFF control circuit comprises: logic controller and the P channel MOS tube after powering on, according to preset logic, exported, the grid of described metal-oxide-semiconductor is connected with the output signal of telecommunication of described logic controller, the source electrode of described metal-oxide-semiconductor is connected with external threshold voltage source, and the drain electrode of described metal-oxide-semiconductor is connected with the power input of described drive circuit.
Wherein, between the source electrode of described metal-oxide-semiconductor and described logic controller output, be provided with RC charge-discharge circuit.
Wherein, the charging interval of described RC charge-discharge circuit is not less than powering on setup time of described logic controller.
Further, between the drain electrode of described metal-oxide-semiconductor and power supply ground, be provided with electric capacity.
Further, described ON-OFF control circuit comprises: logic controller and the switch element after powering on, according to preset logic, exported, the control end of described switch element is connected with the output of described logic controller, in described logic controller, be provided with timer, after powering on, only have described timer timing then just according to the on off state of preset logic output control switch element.
Wherein, described logic controller is CPLD or FPGA.
The utility model also provides a kind of inter-board communication system, comprise: the master control borad communicating by HDLC bus and a plurality of interface board, described in each, interface board comprises: via it, realize the mutual drive circuit of signal between described interface board and described master control borad, and HDLC sending controling circuit, described HDLC sending controling circuit also comprises: ON-OFF control circuit; The output of described ON-OFF control circuit is connected with the described drive circuit signal of telecommunication, according to preset logic switch, controls described drive circuit works.
Compared with prior art, the utility model embodiment proposes utilizes the HDLC sending controling circuit proposing in the embodiment of the present invention and the inter-board communication system that comprises this circuit, in the time of can preventing that the network equipment from powering on or interface board powers on, CPU is in power up, as the I/O port of the CPU of the transmission Enable Pin of HDLC in output level nondeterministic statement (, it is not subject to the control of CPU) situation occur, guarantee accuracy and the fail safe of system.
Accompanying drawing explanation
Fig. 1 utilizes HDLC bus between master control borad and interface board, to carry out the system schematic of communication between plates in the utility model embodiment;
Fig. 2 is the schematic diagram of the ON-OFF control circuit of the utility model embodiment.
Embodiment
Below with reference to drawings and Examples, describe execution mode of the present utility model in detail, to the utility model, how application technology means solve technical problem whereby, and the implementation procedure of reaching technique effect can fully understand and implement according to this.
Shown in figure 1, for carrying out the system schematic of communication between plates between the master control borad that communicates by HDLC bus in the utility model embodiment and interface board.In this inter-board communication system, described master control borad connects a plurality of interface boards by HDLC bus, and described master control borad sends order and configuration data by HDLC down going channel to each interface board, adopts the mode of poll to gather each interface board information simultaneously; And interface board reports relevant information according to the poll instruction of master control borad to master control borad described in each.Wherein:
Described master control borad comprises: the master control borad CPU that is integrated with hdlc controller;
Described interface board comprises: the interface board CPU that is integrated with hdlc controller, and HDLC sending controling circuit, wherein, described HDLC sending controling circuit comprises: ON-OFF control circuit and drive circuit, described interface board CPU alternately (for example carries out signal via described drive circuit and described master control borad, the transmission enable signal of HDLC, upward signal TXD, and the downstream signal RXD of reception master control borad transmission, the sending and receiving clock of HDLC etc.), and, the output of described ON-OFF control circuit is connected with the described drive circuit signal of telecommunication, according to preset time delay logic switch, control described drive circuit works.
Specifically, according to preset time delay logic switch, controlling described drive circuit works comprises: after interface board powers on, ON-OFF control circuit just makes described drive circuit works through time delay Preset Time, more preferably, the output of described ON-OFF control circuit is directly connected with the power input signal of telecommunication of described drive circuit, controls drive circuit whether normally start work with this.
For above-mentioned ON-OFF control circuit, it can be realized by following hardware circuit, as shown in Figure 2, specific as follows:
Described ON-OFF control circuit comprises: logic controller and the field effect transistor (metal-oxide-semiconductor) after powering on, according to predetermined time delay logic, exported, described logic controller and described interface board common-battery source (not shown), its output is connected with grid (G) signal of telecommunication of described metal-oxide-semiconductor, the source electrode of described metal-oxide-semiconductor (S) is connected with external threshold voltage source, and the drain electrode of described metal-oxide-semiconductor (D) is connected with the power input of described drive circuit.
In typical realization, described logic controller typically can be by CPLD (Complex Programmable Logic Device, CPLD) or field programmable gate array (Field Programmable Gate Array, FPGA) realize; And metal-oxide-semiconductor typically adopts P-channel field-effect transistor (PEFT) pipe, certainly, if adopt N channel field-effect pipe, those of ordinary skills carry out part deformation design and can realize on basis embodiment illustrated in fig. 2, repeat no more, the following course of work also only be take P channel MOS tube as example explanation herein.
While utilizing foregoing circuit interface board send control procedure as follows:
After interface board powers on, logic controller and metal-oxide-semiconductor also power on, logic controller starts output causes the restriction that metal-oxide-semiconductor turn-offs to send predetermined level, in circuit, be shown in figure 2: logic controller output high level signal, now, the grid of metal-oxide-semiconductor (G) is high level, and metal-oxide-semiconductor turn-offs, and its drain electrode (D) does not have Voltage-output; Drive circuit does not have operating voltage thus, it will form isolation between interface board CPU and master control borad, now, the CPU of interface board will can be by not carrying out data interaction between drive circuit and master control borad, can not take HDLC bus, thus, main control unit can not receive wrong packet, that is to say, when interface board powers on, can effectively control the transmission of its HDLC and control.
The scheduled time after interface board powers on, logic controller starts output causes the permission that metal-oxide-semiconductor is opened to send predetermined level, in circuit, be shown in figure 2: logic controller output low level signal, metal-oxide-semiconductor conducting, additional power source voltage (V shown in Fig. 2) is delivered to drain electrode (D) by the source electrode (S) of metal-oxide-semiconductor, and as the operating voltage of drive circuit (exemplarily, can select to comprise the circuit of 74LVTH125), make thus drive circuit normally work; Make thus to form between this interface board and master control borad available data path.
But, in the present embodiment, at interface board powered on moment, grid (G) voltage for metal-oxide-semiconductor, because powering on of CPLD/FPGA also needs the process configuring, need its setup time of T1, the T1 of powered on moment in the time CPLD/FPGA output level be low, now metal-oxide-semiconductor may conducting, for fear of this kind of situation, occur, further, between the source electrode (S) of metal-oxide-semiconductor and described logic controller output, arrange and comprise the first capacitor C 1 in parallel and the RC charge-discharge circuit of R, at the setup time of T1 in the time, the source class of metal-oxide-semiconductor (S) is due to the existence of the first capacitor C 1, its turn-on threshold voltage can be first to the first capacitor C 1 charging, charging interval can suitably select the value of the first capacitor C 1 and resistance to determine according to T1 setup time, because T1 time setup time is conventionally shorter, so the voltage of accumulation is conventionally enough little in the first capacitor C 1, and can not make metal-oxide-semiconductor conducting, thereby make drive circuit without power supply, do not start work.Setup time, T1 can determine according to the self character of CPLD/FPGA, and exemplarily, if adopt CPLD to control, the first capacitor C 1 can be chosen 10uf; If adopt FPGA to control, FPGA due to external SDRAM need to be longer with respect to CPLD setup time, the capacitance of the first capacitor C 1 is larger, to guarantee that the drain voltage of metal-oxide-semiconductor when powering on can not reach the voltage that drives chip.Export the high level of predetermined delay time T2 to turn-off metal-oxide-semiconductor, CPLD/FPGA continues output low level subsequently, make metal-oxide-semiconductor grid (G) keep low level always, metal-oxide-semiconductor is in normally on thus, its output guarantees that drive circuit, always in normal operating conditions, forms available data path between interface board and master control borad.
But, in some special scene, for avoid the above-mentioned actual charging interval of RC charge-discharge circuit be less than CPLD/FPGA setup time T1 situation, can between the drain electrode (D) of metal-oxide-semiconductor and power supply ground, be provided with the second capacitor C 2, when setup time, T1 had voltage to be delivered to drain electrode (D) from source electrode (S) in the time, can be first to these the second capacitor C 2 chargings, thereby postpone the time that drive circuit obtains operating voltage, guarantee that metal-oxide-semiconductor can not provide effective operating voltage to drive circuit in setup time T1, thus, guarantee that further HDLC sends controlled during CPU powers on.
In above embodiment, while having avoided interface board to power on by the cooperation of logic control element and metal-oxide-semiconductor, the transmission of HDLC is controlled and is enabled not controlled problem, and hardware realization is simple, and reliability is high.
In another embodiment, ON-OFF control circuit can adopt the mode of other delayed output, for example, ON-OFF control circuit comprises: the logic controller of exporting according to preset logic after powering on, and switch element, the control end of described switch element is connected with the output of described logic controller, in described logic controller, be provided with timer, after powering on, only has described timer timing then just according to the on off state of preset logic output control switch element, now, the output of described switch element is still connected with the described drive circuit signal of telecommunication, according to preset logic switch, control described drive circuit works.Thereby also can make the work of CPU delayed startup.
In sum, utilize the HDLC sending controling circuit proposing in the embodiment of the present invention and the inter-board communication system that comprises this circuit, in the time of can preventing that the network equipment from powering on or interface board powers on, CPU is in power up, as the I/O port of the CPU of the transmission Enable Pin of HDLC in output level nondeterministic statement (, it is not subject to the control of CPU) situation occur, guarantee accuracy and the fail safe of system.
Certainly; the utility model also can have other various embodiments; in the situation that not deviating from the utility model spirit and essence thereof; those of ordinary skill in the art are when making various corresponding changes and distortion according to the utility model, but these corresponding changes and distortion all should belong to the protection range of claim of the present utility model.
Claims (9)
1. a High-Level Data Link Control sending controling circuit, comprise: drive circuit, described drive circuit is connected with the CPU signal of telecommunication of this drive circuit place interface board, it is characterized in that, described High-Level Data Link Control sending controling circuit also comprises: ON-OFF control circuit;
The output of described ON-OFF control circuit is connected with the described drive circuit signal of telecommunication, according to preset logic switch, controls described drive circuit works.
2. High-Level Data Link Control sending controling circuit as claimed in claim 1, is characterized in that,
The output of described ON-OFF control circuit is connected with the power input signal of telecommunication of described drive circuit.
3. High-Level Data Link Control sending controling circuit as claimed in claim 2, is characterized in that,
Described ON-OFF control circuit comprises: logic controller and the P channel MOS tube after powering on, according to preset logic, exported, the grid of described metal-oxide-semiconductor is connected with the output signal of telecommunication of described logic controller, the source electrode of described metal-oxide-semiconductor is connected with external threshold voltage source, and the drain electrode of described metal-oxide-semiconductor is connected with the power input of described drive circuit.
4. High-Level Data Link Control sending controling circuit as claimed in claim 3, is characterized in that, between the source electrode of described metal-oxide-semiconductor and described logic controller output, is provided with RC charge-discharge circuit.
5. High-Level Data Link Control sending controling circuit as claimed in claim 4, is characterized in that,
The charging interval of described RC charge-discharge circuit is not less than powering on setup time of described logic controller.
6. as the High-Level Data Link Control sending controling circuit as described in any one in claim 3 to 5, it is characterized in that,
Between the drain electrode of described metal-oxide-semiconductor and power supply ground, be provided with the second electric capacity.
7. High-Level Data Link Control sending controling circuit as claimed in claim 1, is characterized in that,
Described ON-OFF control circuit comprises: logic controller and the switch element after powering on, according to preset logic, exported, the control end of described switch element is connected with the output of described logic controller, in described logic controller, be provided with timer, after powering on, only have described timer timing then just according to the on off state of preset logic output control switch element.
8. the High-Level Data Link Control sending controling circuit as described in claim 3 or 7, is characterized in that, described logic controller is CPLD or FPGA.
9. an inter-board communication system, comprise: the master control borad communicating by hdlc bus and a plurality of interface board, it is characterized in that, described in each, interface board comprises: via it, realize the mutual drive circuit of signal between described interface board and described master control borad, and High-Level Data Link Control sending controling circuit
Described High-Level Data Link Control sending controling circuit also comprises: ON-OFF control circuit; The output of described ON-OFF control circuit is connected with the described drive circuit signal of telecommunication, according to preset logic switch, controls described drive circuit works.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320577102.0U CN203504601U (en) | 2013-09-17 | 2013-09-17 | Transmission control circuit for high-level data link control (HDLC), and inter-board communication system |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201320577102.0U CN203504601U (en) | 2013-09-17 | 2013-09-17 | Transmission control circuit for high-level data link control (HDLC), and inter-board communication system |
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| CN203504601U true CN203504601U (en) | 2014-03-26 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105277924A (en) * | 2015-11-06 | 2016-01-27 | 中国科学院上海天文台 | Multiband noise switch control device |
| CN109188991A (en) * | 2018-11-20 | 2019-01-11 | 上海新纪元机器人有限公司 | Control the transmission method and device of signal |
-
2013
- 2013-09-17 CN CN201320577102.0U patent/CN203504601U/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105277924A (en) * | 2015-11-06 | 2016-01-27 | 中国科学院上海天文台 | Multiband noise switch control device |
| CN109188991A (en) * | 2018-11-20 | 2019-01-11 | 上海新纪元机器人有限公司 | Control the transmission method and device of signal |
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