CN112445740B - Data asynchronous acquisition method, system and equipment - Google Patents
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Abstract
The application provides a data asynchronous acquisition method, a system and equipment, wherein the method comprises the following steps: receiving an asynchronous clock signal output by a synchronous clock signal after passing through an IO output end, a SPAD, an IO input end and an SPI controller end, wherein the synchronous clock signal is generated by an SPI host end clock generator; receiving a data signal sent by an SPI slave terminal, and carrying out data acquisition on the data signal according to the asynchronous clock signal; according to the application, the SCK synchronous clock signal is pulled back from the PIN PIN to perform data asynchronous receiving and acquisition, so that the problems of time sequence tension and speed limitation of SPI communication caused by delay of clock and data signals in IO and wiring are solved, and the control of time sequence is more convenient when the layout is designed at the rear end, so that the communication speed of an SPI host end can be effectively improved.
Description
Technical Field
The present application relates to the field of clock synchronization technologies, and in particular, to a method, a system, and an apparatus for asynchronously collecting data.
Background
SPI (Serial Perripheral Interface) is a protocol standard for the serial device peripheral interface introduced by Motorola. The SPI serial interface can complete communication by occupying only four pin pins on the chip, so that the pin pins of the chip are saved, and the layout on the PCB is also simple and convenient, therefore, the SPI serial communication protocol has wide application on chips such as FLASH, an ADC converter, an OLED screen and the like.
In the SPI serial communication protocol, data interaction between the host and the slave is completed through a synchronous clock signal SCK. When the host end needs to read data from the slave end, the basic workflow is as follows: according to the SPI protocol, the synchronous clock signal SCK is generated by the host end and output to the slave end, the slave end triggers the internal slave MISO to output data according to the falling edge of the SCK (taking SPI mode 0 as an example), and the host end performs data acquisition according to the rising edge of the SCK. The method for the host to receive the data comprises the following steps: SCK is obtained by dividing the frequency of the internal clock (IP CLK) of the controller IP, when the internal of the controller is a jump edge of SCK, when the controller needs to collect data, the MISO data is collected and latched at the rising edge time of SCK or waiting n (n > =1) IP CLK (but must be before the falling edge).
However, the delay time t net_out is needed from the generation of the SCK signal to the transmission of the IO, the delay t IO_out is needed from the output of the IO, the delay t IO_in is needed from the output of the IO or the consumption of the received SCK output data signal from the slave terminal, and the delay t net_in is needed from the internal wiring to the data acquisition terminal. If the sum of the delay time is larger than half SCK clock period, the controller is directly caused to be incapable of correctly collecting data, and only SCK frequency-reducing processing can be carried out on the data; in addition, if the SPI has a plurality of outlets, the delay of the internal wiring of the SPI also has obvious difference, so that the difficulty of the rear-end timing sequence is increased, and the communication speed of the SPI host end is reduced.
Therefore, a method, system and device for asynchronously collecting data are needed to solve the problems of timing tension and difficult subsequent timing correction caused by delay of clock and data signals in IO and wiring.
Disclosure of Invention
Aiming at the defects of the prior art, the application provides a data asynchronous acquisition method, a system and equipment, which are used for solving the problems of time sequence tension and subsequent time sequence correction difficulty caused by delay of clock and data signals in IO and wiring in the prior art.
In order to solve the above technical problems, in a first aspect, the present application provides a data asynchronous acquisition method, including:
Receiving an asynchronous clock signal output by a synchronous clock signal after passing through an IO output end, a SPAD, an IO input end and an SPI controller end, wherein the synchronous clock signal is generated by an SPI host end clock generator;
Receiving a data signal sent by an SPI slave terminal, and carrying out data acquisition on the data signal according to the asynchronous clock signal;
and after the received data signal is full of one frame, carrying out FIFO data caching on the acquired data.
Preferably, the receiving the asynchronous clock signal output by the synchronous clock signal through the IO output end, the SPAD, the IO input end and the SPI controller end includes:
the data receiving shift register receives an asynchronous clock signal output by the synchronous clock signal after passing through the IO output end, the SPAD, the IO input end and the SPI controller end, and sends the asynchronous clock signal to the data receiving latch;
Preferably, the receiving the data signal sent by the SPI slave, and performing data acquisition on the data signal according to the asynchronous clock signal, includes:
receiving a data signal sent by an SPI slave terminal and an asynchronous clock signal output by a controller terminal, and shifting and latching data sent by the slave terminal according to the asynchronous clock signal;
According to the asynchronous clock signal, the data sent from the machine side and the N-1 bit data stored in the data receiving shift register are latched together; where N is the frame size in SPI communications.
Preferably, the receiving the data signal sent by the SPI slave side, and performing data acquisition on the data signal according to the asynchronous clock signal, further includes:
the data receiving shift register receives data signals sent by the SPI slave terminal;
the data receiving shift register shifts and latches the data sent by the slave terminal under the drive of the rising edge of the asynchronous clock signal;
The data receiving latch latches the data sent from the slave terminal and the N-1 bit data stored in the data receiving shift register into the latch together under the driving of the rising edge of the asynchronous clock signal, and simultaneously generates a frame ready pulse signal.
Preferably, after the received data signal is full of one frame, the data collected is subjected to FIFO data buffering, including:
And when the data signal is full of one frame, receiving the frame ready pulse signal, and taking the frame ready pulse signal as write enable to carry out FIFO data caching on the data registered by the data receiving shift register.
In a second aspect, the present application provides a data asynchronous acquisition system comprising:
A receiving unit configured to receive an asynchronous clock signal output by a synchronous clock signal through an IO output end, a SPAD, an IO input end and an SPI controller end, the synchronous clock signal being generated by an SPI host end clock generator,
The receiving unit is also configured to receive a data signal sent by the SPI slave terminal and perform data acquisition on the data signal according to the asynchronous clock signal;
And the caching unit is configured to perform FIFO data caching on the acquired data after the received data signal is full of one frame.
Preferably, the receiving unit is specifically configured to:
Receiving an asynchronous clock signal output by the synchronous clock signal through the IO output end, the SPAD, the IO input end and the SPI controller end, and sending the asynchronous clock signal to the data receiving latch;
receiving a data signal sent by an SPI slave terminal, and shifting and latching the data sent by the slave terminal according to the asynchronous clock signal;
And according to the asynchronous clock signal, the data transmitted from the machine side and the N-1 bit data stored in the data receiving shift register are latched together.
Preferably, the buffer unit is specifically configured to:
And when the data signal is full of one frame, receiving the frame ready pulse signal, and taking the frame ready pulse signal as write enable to carry out FIFO data caching on the data registered by the data receiving shift register.
Preferably, the system further comprises:
A clock generation unit configured to generate an SCK synchronous clock signal;
The logic control unit is respectively connected with the clock generation unit and the buffer memory unit and is configured to control the clock generation and the data receiving buffer memory.
In a third aspect, the present application provides a data asynchronous acquisition device comprising:
The data receiving shift register, the data receiving latch, the synchronous logic chip and the FIFO data receiving buffer are connected in sequence, wherein,
The synchronous clock signal generated by the SPI host end is divided into two paths after passing through the IO output end and the SPAD, one path of the synchronous clock signal is output to the peripheral SPI slave end, and the other path of the synchronous clock signal is output to the data receiving shift register through the IO input end and the SPI controller end;
the data signal output by the SPI slave terminal is output to the data receiving shift register through the SPAD and the IO input terminal of the IO.
Preferably, the data asynchronous acquisition device further comprises a clock generator and an SPI logic controller, wherein the clock generator generates SCK synchronous clock signals based on IP_CLK frequency division, and the SPI logic controller is respectively connected with the clock generator and the FIFO data receiving buffer and used for controlling clock generation and data receiving buffer.
In a fourth aspect, the present application provides a terminal, comprising:
a processor, a memory, wherein,
The memory is used for storing a computer program,
The processor is configured to call and run the computer program from the memory, so that the terminal performs the method of the terminal as described above.
In a fifth aspect, the present application provides a computer storage medium having instructions stored therein which, when run on a computer, cause the computer to perform the method of the above aspects.
Compared with the prior art, the application has the following beneficial effects:
According to the application, the SCK synchronous clock signal is pulled back from the PIN PIN to perform data asynchronous receiving and acquisition, so that the problems of time sequence tension and speed limitation of SPI communication caused by delay of clock and data signals in IO and wiring are solved, and the control of time sequence is more convenient when the layout is designed at the rear end, so that the communication speed of an SPI host end can be effectively improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present application, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a data asynchronous collection method according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a data asynchronous acquisition system according to an embodiment of the present application;
Fig. 3 is an SPI master-slave wiring diagram of a data asynchronous collection device according to an embodiment of the present application;
FIG. 4 is a schematic block diagram of an SPI module of a data asynchronous collecting device according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of a terminal according to an embodiment of the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Referring to fig. 1, fig. 1 is a flowchart of a data asynchronous collection method according to an embodiment of the present application, and the compensation method 100 includes:
s101: receiving an asynchronous clock signal output by a synchronous clock signal after passing through an IO output end, a SPAD, an IO input end and an SPI controller end, wherein the synchronous clock signal is generated by an SPI host end clock generator;
S102: receiving a data signal sent by an SPI slave terminal, and carrying out data acquisition on the data signal according to the asynchronous clock signal;
S103: and after the received data signal is full of one frame, carrying out FIFO data caching on the acquired data.
Based on the foregoing embodiments, as described in the preferred embodiments, the step S101 of receiving an asynchronous clock signal output by a synchronous clock signal through an IO output terminal, SPAD, an IO input terminal, and an SPI controller terminal includes:
the data receiving shift register receives an asynchronous clock signal output by the synchronous clock signal after passing through the IO output end, the SPAD, the IO input end and the SPI controller end, and sends the asynchronous clock signal to the data receiving latch;
the SPI controller comprises a data receiving shift register and a data receiving latch.
Based on the foregoing embodiments, as a preferred embodiment, the step S102 of receiving a data signal sent by an SPI slave side, and performing data acquisition on the data signal according to the asynchronous clock signal includes:
receiving a data signal sent by an SPI slave terminal and an asynchronous clock signal output by a controller terminal, and shifting and latching data sent by the slave terminal according to the asynchronous clock signal;
According to the asynchronous clock signal, the data sent from the machine side and the N-1 bit data stored in the data receiving shift register are latched together; where N is the frame size in SPI communications.
Based on the foregoing embodiment, as a preferred embodiment, the step 102 receives a data signal sent by the SPI slave, and performs data acquisition on the data signal according to the asynchronous clock signal, and further includes:
the data receiving shift register receives data signals sent by the SPI slave terminal;
the data receiving shift register shifts and latches the data sent by the slave terminal under the drive of the rising edge of the asynchronous clock signal;
The data receiving latch latches the data sent from the slave terminal and the N-1 bit data stored in the data receiving shift register into the latch together under the driving of the rising edge of the asynchronous clock signal, and simultaneously generates a frame ready pulse signal.
Based on the foregoing embodiment, as a preferred embodiment, step 103 performs FIFO data buffering on the collected data after the received data signal is full of one frame, including:
And when the data signal is full of one frame, receiving the frame ready pulse signal, and taking the frame ready pulse signal as write enable to carry out FIFO data caching on the data registered by the data receiving shift register.
It should be noted that the method is applicable to two-wire mode and four-wire mode of SPI FLASH, and the above method and the following embodiments are not limited to the other three modes, namely modes 1-3, with reference to SPI mode 0.
Specifically, taking SPI mode 0 as an example, the synchronous clock signal is generated by the host end by frequency division of the controller IP internal clock (IP CLK), one SCK synchronous clock signal is output to the slave end through the IO output end and SPAD, the slave end triggers its internal output data signal according to the falling edge of SCK, and the other SCK synchronous clock signal is input again through the IO output end, SPAD, IO input end and SPI controller end, so as to obtain the asynchronous clock signal.
When the controller needs to collect data, the SPI controller collects and latches the data signal at the rising edge time of SCK or waiting n (n > =1) IP CLK (but before the falling edge), and puts the data signal into a buffer in a receiving FIFO after being synchronized after one frame is full of the received data.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a data asynchronous acquisition system according to an embodiment of the present application, and the compensation system 200 includes:
The receiving unit 201 is configured to receive an asynchronous clock signal output by a synchronous clock signal through an IO output end, a SPAD, an IO input end and an SPI controller end, the synchronous clock signal is generated by an SPI master end clock generator,
The receiving unit 201 is further configured to receive a data signal sent by the SPI slave, and perform data acquisition on the data signal according to the asynchronous clock signal;
and the caching unit 202 is configured to perform FIFO data caching on the acquired data after the received data signal is full of one frame.
Based on the above embodiments, as a preferred embodiment, the receiving unit 201 is specifically configured to:
Receiving an asynchronous clock signal output by the synchronous clock signal through the IO output end, the SPAD, the IO input end and the SPI controller end, and sending the asynchronous clock signal to the data receiving latch;
receiving a data signal sent by an SPI slave terminal, and shifting and latching the data sent by the slave terminal according to the asynchronous clock signal;
And according to the asynchronous clock signal, the data transmitted from the machine side and the N-1 bit data stored in the data receiving shift register are latched together.
Based on the above embodiments, as a preferred embodiment, the buffer unit 202 is specifically configured to:
And when the data signal is full of one frame, receiving the frame ready pulse signal, and taking the frame ready pulse signal as write enable to carry out FIFO data caching on the data registered by the data receiving shift register.
Based on the above embodiments, as a preferred embodiment, the system 200 further includes: a logic control unit 203, a clock generation unit 204;
The clock generation unit 204 is configured to generate an SCK synchronous clock signal;
The logic control unit 204 is respectively connected with the clock generation unit 203 and the buffer unit 202, and is configured to control clock generation and data receiving buffer.
Referring to fig. 3, fig. 3 is a wiring diagram of an SPI master slave machine of a data asynchronous collecting device according to an embodiment of the present application, and as can be seen from fig. 3, in the design of an SPI chip, four essential signals, i.e., a synchronous clock Signal (SCK), a clock Control Signal (CS), a Master Output Slave Input (MOSI), and a Master Input Slave Output (MISO), are required to be placed adjacently, so that the situation that distances SPI IP are different due to scattered placement is avoided, the difference of routing lengths is not too large, and the requirement of a routing delay phase difference is as small as possible.
Referring to fig. 4, fig. 4 is a schematic block diagram of an SPI module of a data asynchronous collecting device according to an embodiment of the present application. As can be seen from fig. 4, the present application further provides a data asynchronous collecting device, including:
The data receiving shift register, the data receiving latch, the synchronous logic chip and the FIFO data receiving buffer are connected in sequence, wherein,
The synchronous clock signal generated by the SPI host end is divided into two paths after passing through the IO output end and the SPAD, one path of the synchronous clock signal is output to the peripheral SPI slave end, and the other path of the synchronous clock signal is output to the data receiving shift register through the IO input end and the SPI controller end;
the data signal output by the SPI slave terminal is output to the data receiving shift register through the SPAD and the IO input terminal of the IO.
Based on the above embodiment, as a preferred embodiment, the data asynchronous collecting device further includes a clock generator, and an SPI logic controller, where the clock generator generates an SCK synchronous clock signal based on the ip_clk frequency division, and the SPI logic controller is connected to the clock generator and the FIFO data receiving buffer, respectively, and is used to control the clock generation and the data receiving buffer.
Specifically, the data asynchronous acquisition device has the following structure:
1. clk_ GENERTOR: a clock generator for generating SCK based on the ip_clk divide, which can support the ip_clk divide by two at the highest in the present application;
2. RX_FIFO: the data receiving buffer is used for buffering the processed received slave data, so that the CPU and the like can directly read the data conveniently;
3. CONTROL: the control logic of the SPI controller is used for controlling the modules such as a 1/2 clock generator, a data receiving buffer and the like to work;
4. IO: the input/output port is a necessary module for the interaction communication between the chip and the external equipment.
5. RX_SHF: a data receiving shift register for shift-latching the input data miso_in under the driving of the rising edge of the clock signal sck_in;
6. RX_LATCH: a data receiving latch for latching the input data miso_in together with the N-1 bit data already stored IN rx_shf, where N is a frame size IN SPI communication, driven by a rising edge of the clock signal sck_in;
7. SYNC: and the synchronous logic is used for acquiring a received data frame stabilizing pulse signal by utilizing an IP clock signal aiming at the rising edge of a frame synchronous signal generated by the receiving module, and storing the received frame data into the RX_FIFO as write enable.
Specifically, the working principle of the data asynchronous acquisition device is explained as follows:
1. The SCK is output to the peripheral SPI slave terminal, is generated by a clock generator, is input to the DIN terminal after passing through the IO SPAD device, and is finally transmitted to the SPI controller terminal to be used as the working clock of the RX_SHF & RX_LATCH module;
2. The clock signal input to the SPI IP by the SCK is SCK_IN, the clock signal input to the SPI IP by the MISO is MOSI_IN, and the delay t net_in sent to the SPI IP through the internal wiring is not greatly different because the placing positions of the SCK and the IO where the MISO are positioned are adjacent, so that the clock signal has a remarkable help effect on the process of time sequence optimization.
3. According to the principle of time sequence analysis, using the SCK of the IO SPAD as an analysis starting point, analyzing how the SPI collects signals of MISO:
Delay time t dat of data path:
t dat＝tclqv+tio_in_dat+tnet_in_dat, where t clqv is the SCK falling edge value MISO data settling time, t io_in_dat is the delay time for MISO transfer from SPAD to DIN, and t net_in_dat is the delay time for MISO_IN transfer from IO DIN to data latch D
Delay time t sck of clock path:
t sck＝tio_in_sck+tnet_in_sck, where t io_in_sck is the delay time of SCK transfer from SPAD to DIN and t net_in_sck is the delay time of SCK_IN transfer from IO DIN to data latch clock
Data latch setup time t setup:
tsetup＝Tsck/2+tsck-tdat＝Tsck/2+(tio_in_sck+tnet_in_sck)–(tclqv+tio_in_dat+tnet_in_dat)
＝(Tsck/2–tclqv)+(tio_in_sck-tio_in_dat)+(tnet_in_sck-tnet_in_dat)
Since t io_in_sck≈tio_in_dat,tio_in_sck-tio_in_dat≈0,tnet_in_sck≈tnet_in_dat,tnet_in_sck-tnet_in_dat.apprxeq.0
So t setup≈(Tsck/2–tclqv)
According to the expression of the data latch establishing time, the method can basically eliminate the influence of IO delay and internal wiring delay on SPI communication speed.
Referring to fig. 5, fig. 5 is a schematic structural diagram of a terminal 500 according to an embodiment of the present application, and the terminal system 500 may be used to execute the data asynchronous collection method according to the embodiment of the present application.
The terminal system 500 may include: a processor 510, a memory 520 and a communication unit 530. The components may communicate via one or more buses, and it will be appreciated by those skilled in the art that the configuration of the server as shown in the drawings is not limiting of the invention, as it may be a bus-like structure, a star-like structure, or include more or fewer components than shown, or may be a combination of certain components or a different arrangement of components.
The memory 520 may be used to store instructions for execution by the processor 510, and the memory 520 may be implemented by any type of volatile or non-volatile memory terminal or combination thereof, such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk, or optical disk. The execution of the instructions in memory 520, when executed by processor 510, enables terminal 500 to perform some or all of the steps in the method embodiments described below.
The processor 510 is a control center of the storage terminal, connects various parts of the entire electronic terminal using various interfaces and lines, and performs various functions of the electronic terminal and/or processes data by running or executing software programs and/or modules stored in the memory 520, and invoking data stored in the memory. The processor may be comprised of an integrated circuit (INTEGRATED CIRCUIT, simply referred to as an IC), for example, a single packaged IC, or may be comprised of multiple packaged ICs connected to one another for the same function or for different functions. For example, the processor 510 may include only a central processing unit (Central Processing Unit, CPU for short). In the embodiment of the invention, the CPU can be a single operation core or can comprise multiple operation cores.
A communication unit 530 for establishing a communication channel so that the storage terminal can communicate with other terminals. Receiving user data sent by other terminals or sending the user data to other terminals.
The present application also provides a computer storage medium in which a program may be stored, which program may include some or all of the steps in the embodiments provided by the present application when executed. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), a random-access memory (random access memory RAM), or the like.
According to the application, the SCK synchronous clock signal is pulled back from the PIN PIN to perform data asynchronous receiving and acquisition, so that the problems of time sequence tension and speed limitation of SPI communication caused by delay of clock and data signals in IO and wiring are solved, and the control of time sequence is more convenient when the layout is designed at the rear end, so that the communication speed of an SPI host end can be effectively improved.
In the description, each embodiment is described in a progressive manner, and each embodiment is mainly described by the differences from other embodiments, so that the same similar parts among the embodiments are mutually referred. The system provided by the embodiment is relatively simple to describe as it corresponds to the method provided by the embodiment, and the relevant points are referred to in the description of the method section.
The principles and embodiments of the present application have been described herein with reference to specific examples, the description of which is intended only to facilitate an understanding of the method of the present application and its core ideas. It should be noted that it will be apparent to those skilled in the art that various modifications and adaptations of the application can be made without departing from the principles of the application and these modifications and adaptations are intended to be within the scope of the application as defined in the following claims.
It should also be noted that in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Claims (8)
1. The data asynchronous acquisition method is characterized by comprising the following steps of:
Receiving an asynchronous clock signal output by a synchronous clock signal after passing through an IO output end, a SPAD, an IO input end and an SPI controller end, and comprises the following steps: the data receiving shift register receives an asynchronous clock signal which is output by a synchronous clock signal through an IO output end, a SPAD, an IO input end and an SPI controller end and sends the asynchronous clock signal to the data receiving latch, wherein the synchronous clock signal is generated by an SPI host end clock generator;
Receiving a data signal sent by an SPI slave terminal, and carrying out data acquisition on the data signal according to the asynchronous clock signal, wherein the data acquisition comprises the following steps: receiving a data signal sent by an SPI slave terminal and an asynchronous clock signal output by a controller terminal, and shifting and latching data sent by the slave terminal according to the asynchronous clock signal; according to the asynchronous clock signal, the data sent from the machine side and the N-1 bit data stored in the data receiving shift register are latched together; where N is the frame size in SPI communications;
and after the received data signal is full of one frame, carrying out FIFO data caching on the acquired data.
2. The method of claim 1, wherein the receiving the data signal sent by the SPI slave, and performing data acquisition on the data signal according to the asynchronous clock signal, comprises:
the data receiving shift register receives data signals sent by the SPI slave terminal;
the data receiving shift register shifts and latches the data sent by the slave terminal under the drive of the rising edge of the asynchronous clock signal;
The data receiving latch latches the data sent from the slave terminal and the N-1 bit data stored in the data receiving shift register into the latch together under the driving of the rising edge of the asynchronous clock signal, and simultaneously generates a frame ready pulse signal.
3. The method for asynchronous data collection according to claim 2, wherein said performing FIFO data buffering on the collected data after the received data signal is full of one frame comprises:
And when the data signal is full of one frame, receiving the frame ready pulse signal, and taking the frame ready pulse signal as write enable to carry out FIFO data caching on the data registered by the data receiving shift register.
4.A data asynchronous acquisition system, comprising:
The receiving unit is configured to receive an asynchronous clock signal output by a synchronous clock signal after passing through an IO output end, a SPAD, an IO input end and an SPI controller end, and comprises: the data receiving shift register receives the synchronous clock signal, which is output by the IO output end, SPAD, IO input end and SPI controller end, and sends the synchronous clock signal to the data receiving latch, the synchronous clock signal is generated by the SPI host end clock generator,
The receiving unit is further configured to receive a data signal sent by the SPI slave, and perform data acquisition on the data signal according to the asynchronous clock signal, and includes: receiving a data signal sent by an SPI slave terminal and an asynchronous clock signal output by a controller terminal, and shifting and latching data sent by the slave terminal according to the asynchronous clock signal; according to the asynchronous clock signal, the data sent from the machine side and the N-1 bit data stored in the data receiving shift register are latched together; where N is the frame size in SPI communications; further comprises: the data receiving shift register receives data signals sent by the SPI slave terminal; the data receiving shift register shifts and latches the data sent by the slave terminal under the drive of the rising edge of the asynchronous clock signal; the data receiving latch latches the data sent by the slave terminal and the N-1 bit data stored in the data receiving shift register into the latch together under the drive of the rising edge of the asynchronous clock signal, and simultaneously generates a frame ready pulse signal;
And the caching unit is configured to perform FIFO data caching on the acquired data after the received data signal is full of one frame.
5. The data asynchronous collection system according to claim 4, wherein the buffer unit is specifically configured to:
And when the data signal is full of one frame, receiving the frame ready pulse signal, and taking the frame ready pulse signal as write enable to carry out FIFO data caching on the data registered by the data receiving shift register.
6. The data asynchronous acquisition system of claim 4, further comprising:
A clock generation unit configured to generate an SCK synchronous clock signal;
The logic control unit is respectively connected with the clock generation unit and the buffer memory unit and is configured to control the clock generation and the data receiving buffer memory.
7. A data asynchronous acquisition device, comprising:
The data receiving shift register, the data receiving latch, the synchronous logic chip and the FIFO data receiving buffer are connected in sequence, wherein,
The synchronous clock signal generated by the SPI host end is divided into two paths after passing through the IO output end and the SPAD, one path of the synchronous clock signal is output to the peripheral SPI slave end, and the other path of the synchronous clock signal is output to the data receiving shift register through the IO input end and the SPI controller end;
the data signal output by the SPI slave terminal is output to the data receiving shift register through the SPAD and the IO input terminal of the IO.
8. The data asynchronous collection device of claim 7, further comprising:
The clock generator generates SCK synchronous clock signals based on IP_CLK frequency division, and the SPI logic controller is respectively connected with the clock generator and the FIFO data receiving buffer and is used for controlling clock generation and data receiving buffer.
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