CN112445740A - Data asynchronous acquisition method, system and equipment - Google Patents
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Abstract
The application provides a method, a system and equipment for asynchronously acquiring data, wherein the method comprises the following steps: receiving an asynchronous clock signal output by a synchronous clock signal after the synchronous clock signal passes through an IO output end, an SPAD, an IO input end and an SPI controller end, wherein the synchronous clock signal is generated by an SPI host end clock generator; receiving a data signal sent by an SPI slave terminal, and carrying out data acquisition on the data signal according to the asynchronous clock signal; this application carries out data asynchronous receiving, collection through drawing back SCK synchronous clock signal from the PIN foot, has solved SPI communication because of the clock and data signal in IO and the problem that the time sequence that the delay of walking the line caused is nervous and speed is limited, and it is also more convenient to the accuse of time sequence when rear end design territory simultaneously, can effectual improvement SPI host computer end communication speed.
Description
Technical Field
The present application relates to the field of clock synchronization technologies, and in particular, to a method, a system, and a device for asynchronous data acquisition.
Background
Spi (serial peripheral interface) is a protocol standard introduced by Motorola corporation for serial device peripheral interfaces. The SPI serial interface only occupies four pins on the chip to finish communication, saves the use of the pins of the chip, and is also simple and convenient to arrange on a PCB board, so that the SPI serial communication protocol has wide application on chips such as FLASH, ADC converters, OLED screens and the like.
In the SPI serial port communication protocol, data interaction between a host and a slave is completed through a synchronous clock signal SCK. When the master end needs to read data from the slave end, the basic working flow is as follows: according to the SPI protocol, a synchronous clock signal SCK is generated by the master and output to the slave, the slave triggers its internal slave MISO to output data according to the falling edge of SCK (for example, SPI mode 0), and the master performs data acquisition according to the rising edge of SCK. The method for receiving data by the host comprises the following steps: the SCK is obtained by dividing frequency by an IP internal clock (IP CLK) of the controller, the controller is internally used for determining when the transition edge of the SCK is, and when the controller needs to collect data, the controller waits for n (n > ═ 1) IP CLK (but before the falling edge) to collect and latch MISO data at the rising edge time of the SCK.
However, the delay time t is required from the generation of the SCK signal to the transmission of IOnet_outThe delay t is also required for the output from IOIO_outThe slave outputs the data signal from IO again according to the received SCK or consumes the delay tIO_inFinally, the delay t is needed when the signal is sent to a data acquisition end through internal routingnet_in. If the sum of the delay times is more than half SCK clock period, the controller can not correctly acquire data, and only the SCK can be subjected to frequency reduction treatment; in addition, if the SPI has a plurality of exits, the delay of its internal routing also has obvious difference, from the degree of difficulty that increases the back end and repaiies the chronogenesis, reduces SPI host computer end communication speed.
Therefore, a method, a system and a device for data asynchronous acquisition are needed to solve the problems of time sequence tension and difficulty in subsequent time sequence correction caused by the delay of clock and data signals at IO and wires.
Disclosure of Invention
Aiming at the defects of the prior art, the application provides a data asynchronous acquisition method, a system and equipment, so as to solve the problems of time sequence tension and follow-up time sequence correction difficulty caused by the delay of clock and data signals at IO and routing in the prior art.
In order to solve the above technical problem, in a first aspect, the present application provides a data asynchronous acquisition method, including:
receiving an asynchronous clock signal output by a synchronous clock signal after the synchronous clock signal passes through an IO output end, an SPAD, an IO input end and an SPI controller end, wherein the synchronous clock signal is generated by an SPI host end clock generator;
receiving a data signal sent by an SPI slave terminal, and carrying out data acquisition on the data signal according to the asynchronous clock signal;
and when the received data signal is full of one frame, carrying out FIFO data buffering on the acquired data.
Preferably, the receiving of the asynchronous clock signal output by the synchronous clock signal after passing through the IO output terminal, the SPAD, the IO input terminal, and the SPI controller terminal includes:
the data receiving shift register receives an asynchronous clock signal output by a synchronous clock signal after passing through an IO output end, an SPAD (spatial adaptive detection), an IO input end and an SPI (serial peripheral interface) controller end, and sends the asynchronous clock signal to the data receiving latch;
preferably, the receiving a data signal sent by the SPI slave and performing data acquisition on the data signal according to the asynchronous clock signal includes:
receiving a data signal sent by an SPI slave terminal and an asynchronous clock signal output by a controller terminal, and shifting and latching data sent by the slave terminal according to the asynchronous clock signal;
the data sent from the slave end and the N-1 bit data stored by the data receiving shift register are latched together according to the asynchronous clock signal; where N is the frame size in SPI communication.
Preferably, the receiving a data signal sent by the SPI slave and performing data acquisition on the data signal according to the asynchronous clock signal further includes:
the data receiving shift register receives a data signal sent by the SPI slave terminal;
the data receiving shift register shifts and latches the data sent from the slave end under the driving of the rising edge of the asynchronous clock signal;
the data receiving latch latches the data sent from the slave end and the N-1 bit data already stored in the data receiving shift register into the latch under the driving of the rising edge of the asynchronous clock signal, and simultaneously generates a frame ready pulse signal.
Preferably, when the received data signal is full of one frame, performing FIFO data buffering on the acquired data includes:
and when the data signal is full of one frame, receiving the frame ready pulse signal, and performing FIFO data caching on the data registered by the data receiving shift register by taking the frame ready pulse signal as write enable.
In a second aspect, the present application provides an asynchronous data acquisition system, including:
a receiving unit configured to receive an asynchronous clock signal output by a synchronous clock signal via an IO output terminal, an SPAD, an IO input terminal, and an SPI controller terminal, the synchronous clock signal being generated by an SPI host terminal clock generator,
the receiving unit is also configured to receive a data signal sent by an SPI (serial peripheral interface) slave terminal and perform data acquisition on the data signal according to the asynchronous clock signal;
and the buffer unit is configured to perform FIFO data buffer on the acquired data after the received data signal is full of one frame.
Preferably, the receiving unit is specifically configured to:
receiving an asynchronous clock signal output by a synchronous clock signal after passing through an IO output end, an SPAD, an IO input end and an SPI controller end, and sending the asynchronous clock signal to a data receiving latch;
receiving a data signal sent by an SPI slave terminal, and shifting and latching the data sent by the slave terminal according to the asynchronous clock signal;
and latching the data sent from the slave end and the N-1 bit data stored by the data receiving shift register together according to the asynchronous clock signal.
Preferably, the cache unit is specifically configured to:
and when the data signal is full of one frame, receiving the frame ready pulse signal, and performing FIFO data caching on the data registered by the data receiving shift register by taking the frame ready pulse signal as write enable.
Preferably, the system further comprises:
a clock generation unit configured to generate an SCK synchronous clock signal;
and the logic control unit is respectively connected with the clock generation unit and the cache unit and is configured for controlling clock generation and data receiving cache.
In a third aspect, the present application provides an asynchronous data acquisition device, including:
a data receiving shift register, a data receiving latch, a synchronous logic chip and an FIFO data receiving buffer, which are connected in turn, wherein,
a synchronous clock signal generated by the SPI host end is divided into two paths after passing through an IO output end and an SPAD, one path is output to a peripheral SPI slave end, and the other path is output to a data receiving shift register through the IO input end and an SPI controller end;
and a data signal output by the SPI slave terminal is output to the data receiving shift register through the SPAD and the IO input terminal of the IO.
Preferably, the data asynchronous acquisition device further comprises a clock generator and an SPI logic controller, wherein the clock generator generates an SCK synchronous clock signal based on IP _ CLK frequency division, and the SPI logic controller is connected to the clock generator and the FIFO data receiving buffer respectively, and is configured to control clock generation and data receiving buffer.
In a fourth aspect, the present application provides a terminal, comprising:
a processor, a memory, wherein,
the memory is used for storing a computer program which,
the processor is used for calling and running the computer program from the memory so as to make the terminal execute the method of the terminal.
In a fifth aspect, the present application provides a computer storage medium having stored therein instructions, which when executed on a computer, cause the computer to perform the method of the above aspects.
Compared with the prior art, the method has the following beneficial effects:
this application carries out data asynchronous receiving, collection through drawing back SCK synchronous clock signal from the PIN foot, has solved SPI communication because of the clock and data signal in IO and the problem that the time sequence that the delay of walking the line caused is nervous and speed is limited, and it is also more convenient to the accuse of time sequence when rear end design territory simultaneously, can effectual improvement SPI host computer end communication speed.
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In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a flowchart of a data asynchronous acquisition method according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of an asynchronous data acquisition system according to an embodiment of the present disclosure;
fig. 3 is a SPI master-slave connection diagram of a data asynchronous acquisition device according to an embodiment of the present application;
fig. 4 is a schematic block diagram of an SPI module of the data asynchronous acquisition device according to the embodiment of the present application;
fig. 5 is a schematic structural diagram of a terminal according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, fig. 1 is a flowchart of a data asynchronous acquisition method according to an embodiment of the present application, where the compensation method 100 includes:
s101: receiving an asynchronous clock signal output by a synchronous clock signal after the synchronous clock signal passes through an IO output end, an SPAD, an IO input end and an SPI controller end, wherein the synchronous clock signal is generated by an SPI host end clock generator;
s102: receiving a data signal sent by an SPI slave terminal, and carrying out data acquisition on the data signal according to the asynchronous clock signal;
s103: and when the received data signal is full of one frame, carrying out FIFO data buffering on the acquired data.
Based on the foregoing embodiment, as a preferred embodiment, the step S101 receives an asynchronous clock signal output by a synchronous clock signal after passing through an IO output terminal, an SPAD, an IO input terminal, and an SPI controller terminal, and includes:
the data receiving shift register receives an asynchronous clock signal output by a synchronous clock signal after passing through an IO output end, an SPAD (spatial adaptive detection), an IO input end and an SPI (serial peripheral interface) controller end, and sends the asynchronous clock signal to the data receiving latch;
the SPI controller comprises a data receiving shift register and a data receiving latch.
Based on the foregoing embodiment, as a preferred embodiment, the step S102 receives a data signal sent by an SPI slave, and performs data acquisition on the data signal according to the asynchronous clock signal, and includes:
receiving a data signal sent by an SPI slave terminal and an asynchronous clock signal output by a controller terminal, and shifting and latching data sent by the slave terminal according to the asynchronous clock signal;
the data sent from the slave end and the N-1 bit data stored by the data receiving shift register are latched together according to the asynchronous clock signal; where N is the frame size in SPI communication.
Based on the foregoing embodiment, as a preferred embodiment, the step 102 receives a data signal sent by an SPI slave, and performs data acquisition on the data signal according to the asynchronous clock signal, and further includes:
the data receiving shift register receives a data signal sent by the SPI slave terminal;
the data receiving shift register shifts and latches the data sent from the slave end under the driving of the rising edge of the asynchronous clock signal;
the data receiving latch latches the data sent from the slave end and the N-1 bit data already stored in the data receiving shift register into the latch under the driving of the rising edge of the asynchronous clock signal, and simultaneously generates a frame ready pulse signal.
Based on the foregoing embodiment, as a preferred embodiment, the step 103 performs FIFO data buffering on the collected data after the received data signal is full of one frame, and includes:
and when the data signal is full of one frame, receiving the frame ready pulse signal, and performing FIFO data caching on the data registered by the data receiving shift register by taking the frame ready pulse signal as write enable.
It should be noted that the method is applicable to two-wire mode and four-wire mode of SPI FLASH, and the above method and the following embodiments are referred to as SPI mode 0, and are not limited to the other three modes, i.e., modes 1-3.
Specifically, taking SPI mode 0 as an example, the synchronous clock signal is generated by frequency division of a controller IP internal clock (IP CLK) at the host end, one path of SCK synchronous clock signal is output to the slave end through the IO output end and the SPAD, the slave end triggers its internal output data signal according to a falling edge of SCK, and the other path of SCK synchronous clock signal is re-input through the IO output end, the SPAD, the IO input end, and the SPI controller end, so as to obtain an asynchronous clock signal.
When the controller needs to collect data, the SPI controller collects and latches the data signal at the rising edge of SCK or waits for n (n > ═ 1) IP CLKs (but must be before the falling edge) based on the asynchronous clock signal pulled back from the controller, and when the received data is full of one frame, the data signal is synchronized and put into the buffer of the receiving FIFO.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a data asynchronous acquisition system according to an embodiment of the present application, where the compensation system 200 includes:
a receiving unit 201, wherein the receiving unit 201 is configured to receive an asynchronous clock signal output by a synchronous clock signal through an IO output terminal, a SPAD, an IO input terminal, and an SPI controller terminal, the synchronous clock signal is generated by an SPI host terminal clock generator,
the receiving unit 201 is further configured to receive a data signal sent by an SPI slave, and perform data acquisition on the data signal according to the asynchronous clock signal;
a buffer unit 202 configured to perform FIFO data buffering on the acquired data when the received data signal is full of one frame.
Based on the foregoing embodiment, as a preferred embodiment, the receiving unit 201 is specifically configured to:
receiving an asynchronous clock signal output by a synchronous clock signal after passing through an IO output end, an SPAD, an IO input end and an SPI controller end, and sending the asynchronous clock signal to a data receiving latch;
receiving a data signal sent by an SPI slave terminal, and shifting and latching the data sent by the slave terminal according to the asynchronous clock signal;
and latching the data sent from the slave end and the N-1 bit data stored by the data receiving shift register together according to the asynchronous clock signal.
Based on the foregoing embodiment, as a preferred embodiment, the cache unit 202 is specifically configured to:
and when the data signal is full of one frame, receiving the frame ready pulse signal, and performing FIFO data caching on the data registered by the data receiving shift register by taking the frame ready pulse signal as write enable.
Based on the above embodiment, as a preferred embodiment, the system 200 further includes: a logic control unit 203, a clock generation unit 204;
the clock generation unit 204 is configured to generate an SCK synchronization clock signal;
the logic control unit 204 is connected to the clock generation unit 203 and the buffer unit 202, and configured to control clock generation and data receiving buffer.
Please refer to fig. 3, fig. 3 is a SPI master-slave wiring diagram of the data asynchronous acquisition device according to the embodiment of the present application, as shown in fig. 3, in the design of the SPI chip, the IO requirements of the SPI chip, where the four necessary signals, namely, synchronous clock Signal (SCK), clock Control Signal (CS), Master Output Slave Input (MOSI), and Master Input Slave Output (MISO), are placed adjacently, so as to avoid the situation that the distances from the SPI chip are different from the IPs IP due to the scattered placement, and the difference between the routing lengths is not too large, and the requirement of the routing delay difference is as small as possible.
Referring to fig. 4, fig. 4 is a schematic block diagram of an SPI module of a data asynchronous acquisition device according to an embodiment of the present application. As can be seen from fig. 4, the present application further provides a data asynchronous acquisition device, including:
a data receiving shift register, a data receiving latch, a synchronous logic chip and an FIFO data receiving buffer, which are connected in turn, wherein,
a synchronous clock signal generated by the SPI host end is divided into two paths after passing through an IO output end and an SPAD, one path is output to a peripheral SPI slave end, and the other path is output to a data receiving shift register through the IO input end and an SPI controller end;
and a data signal output by the SPI slave terminal is output to the data receiving shift register through the SPAD and the IO input terminal of the IO.
Based on the above embodiment, as a preferred embodiment, the data asynchronous acquisition device further includes a clock generator and an SPI logic controller, the clock generator generates an SCK synchronous clock signal based on IP _ CLK frequency division, and the SPI logic controller is connected to the clock generator and the FIFO data receiving buffer, respectively, and is configured to control clock generation and data receiving buffer.
Specifically, the data asynchronous acquisition device has the following structure:
1. CLK _ GENERTOR: the clock generator is used for generating the SCK based on the frequency division of the IP _ CLK, and the frequency division of the IP _ CLK can be supported to be two times as fast in the application;
2. RX _ FIFO: the data receiving cache is used for caching the processed received slave data, so that a CPU (central processing unit) and the like can read the data directly;
3. CONTROL: the control logic of the SPI controller is positioned to control 1/2 the modules of a clock generator, a data receiving buffer and the like to work;
4. IO: the input/output port is a necessary module for the chip to negotiate and communicate with external equipment.
5. RX _ SHF: the data receiving shift register is used for shifting and latching the input data MISO _ IN under the drive of the rising edge of the clock signal SCK _ IN;
6. RX _ LATCH: a data receiving latch for latching the input data MISO _ IN and the N-1 bit data already stored IN RX _ SHF together driven by the rising edge of the clock signal SCK _ IN, where N is the frame size IN SPI communication;
7. SYNC: and the synchronization logic acquires a received data frame stabilization pulse signal aiming at the rising edge of the frame synchronization signal generated by the receiving module by using the IP clock signal, and stores the received frame data into the RX _ FIFO as write enable.
Specifically, the working principle of the data asynchronous acquisition device is described as follows:
1. the SCK output to the peripheral SPI slave end is generated by a clock generator, is input to a DIN end after passing through an IO SPAD device, and is finally transmitted to the SPI controller end to be used as a working clock of an RX _ SHF & RX _ LATCH module;
2. the clock signal that SCK input to SPI IP is SCK _ IN, and the clock signal that MISO input to SPI IP is MOSI _ IN, because SCK and MISO place IO's locating position are adjacent, send to SPI IP delay t through inside walking line sonet_inThe phase difference is not large, and the method has a remarkable help effect on the timing optimization process.
3. According to the principle of time sequence analysis, the SCK of the IO SPAD is used as an analysis starting point, and how the SPI acquires the MISO signal is analyzed:
delay time t of data pathdat：
tdat＝tclqv+tio_in_dat+tnet_in_dat,Wherein t isclqvIs the SCK falling edge value MISO data settling time, tio_in_datIs the delay time, t, for the MISO to pass from SPAD to DINnet_in_datIs the delay time of MISO _ IN from IO DIN terminal to D terminal of data latch
Delay time t of clock pathsck：
tsck＝tio_in_sck+tnet_in_sck,Wherein, tio_in_sckIs the delay time, t, for the transfer of SCK from SPAD to DINnet_in_sckIs the delay time of SCK _ IN from IO DIN terminal to data latch clock terminal
Data latch setup time tsetup：
tsetup＝Tsck/2+tsck-tdat＝Tsck/2+(tio_in_sck+tnet_in_sck)–(tclqv+tio_in_dat+tnet_in_dat)
＝(Tsck/2–tclqv)+(tio_in_sck-tio_in_dat)+(tnet_in_sck-tnet_in_dat)
Due to tio_in_sck≈tio_in_dat，tio_in_sck-tio_in_dat≈0，tnet_in_sck≈tnet_in_dat,tnet_in_sck-tnet_in_dat≈0
So tsetup≈(Tsck/2–tclqv)
According to the expression of the data latch establishing time, the method can basically eliminate the influence of IO delay and internal wiring delay on the SPI communication speed.
Referring to fig. 5, fig. 5 is a schematic structural diagram of a terminal 500 according to an embodiment of the present disclosure, where the terminal system 500 may be used to execute the data asynchronous acquisition method according to the embodiment of the present disclosure.
The terminal system 500 may include: a processor 510, a memory 520, and a communication unit 530. The components communicate via one or more buses, and those skilled in the art will appreciate that the architecture of the servers shown in the figures is not intended to be limiting, and may be a bus architecture, a star architecture, a combination of more or less components than those shown, or a different arrangement of components.
The memory 520 may be used for storing instructions executed by the processor 510, and the memory 520 may be implemented by any type of volatile or non-volatile storage terminal or combination thereof, such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk. The executable instructions in memory 520, when executed by processor 510, enable terminal 500 to perform some or all of the steps in the method embodiments described below.
The processor 510 is a control center of the storage terminal, connects various parts of the entire electronic terminal using various interfaces and lines, and performs various functions of the electronic terminal and/or processes data by operating or executing software programs and/or modules stored in the memory 520 and calling data stored in the memory. The processor may be composed of an Integrated Circuit (IC), for example, a single packaged IC, or a plurality of packaged ICs connected with the same or different functions. For example, processor 510 may include only a Central Processing Unit (CPU). In the embodiment of the present invention, the CPU may be a single operation core, or may include multiple operation cores.
A communication unit 530 for establishing a communication channel so that the storage terminal can communicate with other terminals. And receiving user data sent by other terminals or sending the user data to other terminals.
The present application also provides a computer storage medium, wherein the computer storage medium may store a program, and the program may include some or all of the steps in the embodiments provided by the present invention when executed. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM) or a Random Access Memory (RAM).
This application carries out data asynchronous receiving, collection through drawing back SCK synchronous clock signal from the PIN foot, has solved SPI communication because of the clock and data signal in IO and the problem that the time sequence that the delay of walking the line caused is nervous and speed is limited, and it is also more convenient to the accuse of time sequence when rear end design territory simultaneously, can effectual improvement SPI host computer end communication speed.
The embodiments are described in a progressive manner in the specification, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the system provided by the embodiment, the description is relatively simple because the system corresponds to the method provided by the embodiment, and the relevant points can be referred to the method part for description.
The principles and embodiments of the present application are explained herein using specific examples, which are provided only to help understand the method and the core idea of the present application. It should be noted that, for those skilled in the art, it is possible to make several improvements and modifications to the present application without departing from the principle of the present application, and such improvements and modifications also fall within the scope of the claims of the present application.
It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Claims (11)
1. A data asynchronous acquisition method is characterized by comprising the following steps:
receiving an asynchronous clock signal output by a synchronous clock signal after the synchronous clock signal passes through an IO output end, an SPAD, an IO input end and an SPI controller end, wherein the synchronous clock signal is generated by an SPI host end clock generator;
receiving a data signal sent by an SPI slave terminal, and carrying out data acquisition on the data signal according to the asynchronous clock signal;
and when the received data signal is full of one frame, carrying out FIFO data buffering on the acquired data.
2. The asynchronous data acquisition method of claim 1, wherein receiving the asynchronous clock signal output by the synchronous clock signal via the IO output terminal, the SPAD, the IO input terminal, and the SPI controller terminal comprises:
and the data receiving shift register receives an asynchronous clock signal output by a synchronous clock signal after passing through an IO output end, an SPAD (spatial adaptive differential amplifier), an IO input end and an SPI (serial peripheral interface) controller end, and sends the asynchronous clock signal to the data receiving latch.
3. The asynchronous data collection method according to claim 1, wherein the receiving a data signal sent by an SPI slave and performing data collection on the data signal according to the asynchronous clock signal comprises:
receiving a data signal sent by an SPI slave terminal and an asynchronous clock signal output by a controller terminal, and shifting and latching data sent by the slave terminal according to the asynchronous clock signal;
the data sent from the slave end and the N-1 bit data stored by the data receiving shift register are latched together according to the asynchronous clock signal; where N is the frame size in SPI communication.
4. The asynchronous data collection method according to claim 1, wherein the receiving a data signal sent by an SPI slave and performing data collection on the data signal according to the asynchronous clock signal comprises:
the data receiving shift register receives a data signal sent by the SPI slave terminal;
the data receiving shift register shifts and latches the data sent from the slave end under the driving of the rising edge of the asynchronous clock signal;
the data receiving latch latches the data sent from the slave end and the N-1 bit data already stored in the data receiving shift register into the latch under the driving of the rising edge of the asynchronous clock signal, and simultaneously generates a frame ready pulse signal.
5. The asynchronous data acquisition method as claimed in claim 1, wherein said step of buffering the acquired data in a FIFO after the received data signal is full of one frame comprises:
and when the data signal is full of one frame, receiving the frame ready pulse signal, and performing FIFO data caching on the data registered by the data receiving shift register by taking the frame ready pulse signal as write enable.
6. An asynchronous data acquisition system, comprising:
a receiving unit configured to receive an asynchronous clock signal output by a synchronous clock signal via an IO output terminal, an SPAD, an IO input terminal, and an SPI controller terminal, the synchronous clock signal being generated by an SPI host terminal clock generator,
the receiving unit is also configured to receive a data signal sent by an SPI (serial peripheral interface) slave terminal and perform data acquisition on the data signal according to the asynchronous clock signal;
and the buffer unit is configured to perform FIFO data buffer on the acquired data after the received data signal is full of one frame.
7. The data asynchronous acquisition system of claim 6, wherein the receiving unit is specifically configured to:
receiving an asynchronous clock signal output by a synchronous clock signal after passing through an IO output end, an SPAD, an IO input end and an SPI controller end, and sending the asynchronous clock signal to a data receiving latch;
receiving a data signal sent by an SPI slave terminal, and shifting and latching the data sent by the slave terminal according to the asynchronous clock signal;
and latching the data sent from the slave end and the N-1 bit data stored by the data receiving shift register together according to the asynchronous clock signal.
8. The data asynchronous acquisition system of claim 6, wherein the cache unit is specifically configured to:
and when the data signal is full of one frame, receiving the frame ready pulse signal, and performing FIFO data caching on the data registered by the data receiving shift register by taking the frame ready pulse signal as write enable.
9. The asynchronous data acquisition system of claim 6, further comprising:
a clock generation unit configured to generate an SCK synchronous clock signal;
and the logic control unit is respectively connected with the clock generation unit and the cache unit and is configured for controlling clock generation and data receiving cache.
10. An asynchronous data acquisition device, comprising:
a data receiving shift register, a data receiving latch, a synchronous logic chip and an FIFO data receiving buffer, which are connected in turn, wherein,
a synchronous clock signal generated by the SPI host end is divided into two paths after passing through an IO output end and an SPAD, one path is output to a peripheral SPI slave end, and the other path is output to a data receiving shift register through the IO input end and an SPI controller end;
and a data signal output by the SPI slave terminal is output to the data receiving shift register through the SPAD and the IO input terminal of the IO.
11. The data asynchronous acquisition device of claim 10, further comprising:
the SCK synchronous clock signal is generated by the clock generator based on IP _ CLK frequency division, and the SPI logic controller is respectively connected with the clock generator and the FIFO data receiving buffer and used for controlling clock generation and data receiving buffer.
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