CN117118777B - Communication system and method - Google Patents
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- CN117118777B CN117118777B CN202311368797.6A CN202311368797A CN117118777B CN 117118777 B CN117118777 B CN 117118777B CN 202311368797 A CN202311368797 A CN 202311368797A CN 117118777 B CN117118777 B CN 117118777B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L2012/40208—Bus networks characterized by the use of a particular bus standard
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Abstract
The application provides a communication system and a method, wherein a clock signal pin of a host unit is connected with a first clock signal pin of a 1 st slave unit, and a second clock signal pin of an i-th slave unit is connected with a first clock signal pin of an i+1th slave unit; the data signal pin of the host unit is connected to the first data signal pin of the 1 st slave unit, and the second data signal pin of the i-th slave unit is connected to the first data signal pin of the i+1-th slave unit. The jumper function is completed through two pins inside the slave unit, and signal wires for connecting the slave units in parallel do not need to be led out independently, so that conflict with other wiring of the slave unit can be avoided, and the jumper can be avoided.
Description
Technical Field
The present application relates to the field of communications, and in particular, to a communication system and method.
Background
Among communication protocols, the S-wire, I2C and SPI protocols are common. The S-wire (Single wire) protocol only needs one signal wire, and the connection mode is simple, but the signal bandwidth capable of being transmitted is limited because CLK (clock synchronous) is not available. The I2C (Inter-Integrated Circuit) protocol requires two signal lines, one of which is CLK (SCL) and the other of which is Data (SDA), commonly used for signal frequencies of hundreds of k to several MHz. The SPI (Seriel Peripheral Interface) standard protocol requires four signal lines, MISO, MOSI, SCLK and CS, respectively, which can reach speeds of tens of MHz because the input and output signal lines are separated.
The SPI protocol is adopted in the system requiring the communication speed (bandwidth), and meanwhile, the wiring layout is plagued due to the large number of signal wires.
Disclosure of Invention
It is an object of the present application to provide a communication system and method to at least partially ameliorate the above problems.
In order to achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:
in a first aspect, embodiments of the present application provide a communication system including a master unit and N slave units; the clock signal pin of the host unit is connected with the first clock signal pin of the 1 st slave unit, the second clock signal pin of the i th slave unit is connected with the first clock signal pin of the i+1 th slave unit, and a clock signal channel is formed; the data signal pins of the host unit are connected with the first data signal pins of the 1 st slave unit, the second data signal pins of the i th slave unit are connected with the first data signal pins of the i+1 th slave unit, and a data signal channel is formed; the first clock signal pin and the first data signal pin of the ith slave unit are arranged on the first side of the ith slave unit, and the second clock signal pin and the second data signal pin of the ith slave unit are arranged on the second side of the ith slave unit.
A second aspect, on the basis of the first aspect, the synchronization signal pin of the master unit is connected to the first synchronization signal pin of the 1 st slave unit, and the second synchronization signal pin of the i-th slave unit is connected to the first synchronization signal pin of the i+1-th slave unit, so as to form a synchronization signal channel; the first synchronous signal pin of the ith slave unit is arranged on the first side of the ith slave unit, and the second synchronous signal pin of the ith slave unit is arranged on the second side of the ith slave unit.
In a third aspect, an embodiment of the present application provides a communication method, which is applied to the communication system of the second aspect, and the method includes: the host unit sends clock signals to the N slave units through the clock signal channels; the host unit sends data signals to the N slave units through the data signal channels; the host unit sends synchronizing signals to the N slave units through the synchronizing signal channels; after receiving the synchronous signals, the N slave units respectively wait for corresponding delay and execute corresponding control instructions; when the received data signals are the host requests of the first preset type, the N slave units wait for a second preset time interval and feed back slave data to the host units through the synchronous signal channels; and/or, after receiving the synchronization signal, the N slave units wait for a second preset time interval, and feed back slave data to the master unit through the synchronization signal channel.
In a fourth aspect, embodiments of the present application provide a communication method, which is applied to the communication system of the first aspect, and the method includes: the host unit sends clock signals to the N slave units through the clock signal channels; the host unit sends data signals to the N slave units through the data signal channels; after receiving the data signals and encoding the synchronous signals, the N slave units respectively wait for corresponding delay and execute corresponding control instructions; and the N slave units wait for a first preset time interval when the received data signals are the first preset type of host requests, and feed back slave data to the host units through the data signal channels.
Compared with the prior art, the communication system and the method provided by the embodiment of the application comprise a host unit and N slave units; the clock signal pin of the host unit is connected with the first clock signal pin of the 1 st slave unit, the second clock signal pin of the i-th slave unit is connected with the first clock signal pin of the i+1-th slave unit, and a clock signal channel is formed; the data signal pin of the host unit is connected with the first data signal pin of the 1 st slave unit, and the second data signal pin of the i-th slave unit is connected with the first data signal pin of the i+1-th slave unit to form a data signal channel; wherein i < N is not less than 1, the first clock signal pin and the first data signal pin of the ith slave unit are arranged on the first side of the ith slave unit, and the second clock signal pin and the second data signal pin of the ith slave unit are arranged on the second side of the ith slave unit. The jumper function is completed through two pins inside the slave unit, a clock signal line, a chip selection signal line and a synchronous signal line which are used for connecting all the slave units in parallel do not need to be independently led out, and serial connection is completed through two pins inside the slave unit, so that conflict with other wiring of the slave unit can be avoided, and the condition of jumper wire can be avoided.
In order to make the above objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered limiting in scope, and that other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a daisy chain topology structure based on SPI provided in an embodiment of the present application;
fig. 2 is a schematic diagram of a topology of a communication system according to an embodiment of the present application;
fig. 3 is a second schematic topology diagram of a communication system according to an embodiment of the present application;
fig. 4 is a schematic diagram of dual edge triggering according to an embodiment of the present application.
In the figure: 100-a host unit; 200-slave units.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, as provided in the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
In the description of the present application, it should be noted that, the terms "upper," "lower," "inner," "outer," and the like indicate an orientation or a positional relationship based on the orientation or the positional relationship shown in the drawings, or an orientation or a positional relationship conventionally put in use of the product of the application, merely for convenience of description and simplification of the description, and do not indicate or imply that the apparatus or element to be referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present application.
In the description of the present application, it should also be noted that, unless explicitly specified and limited otherwise, the terms "disposed," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context.
Some embodiments of the present application are described in detail below with reference to the accompanying drawings. The following embodiments and features of the embodiments may be combined with each other without conflict.
Bandwidth limitations in the SPI communication architecture or the SPI protocol are many times due to insufficient speed of internal signal processing of the chip (Slave IC) therein. At this time, the line delay of the PCB substrate may be ignored.
In addition, in many systems requiring communication, such as but not limited to local dimming backlight, mini-LED backlight, micro-LED, etc. applications of a display system, not only SPI communication is required, but also a Daisy Chain topology (Daisy Chain) structure is required for the communication system because as few jumpers as possible are desired. Referring to fig. 1, fig. 1 is a schematic diagram of a daisy chain topology based on SPI according to an embodiment of the present application. The architecture shown in fig. 1 is different from the conventional addressing SPI connection scheme in that a plurality of slave units 200 are connected in series in a Daisy-Chain topology (Daisy Chain) topology. The slave unit 200 may be, but is not limited to, a slave IC.
Specifically, the SPI-based daisy-chain topology shown in fig. 1 includes a master unit 100 and N slave units 200. The host unit 100 is also referred to as a master (master), and may be, but not limited to, an MCU or an FPGA. Pin 1 (MOSI) and pin 2 (MISO) of each slave unit 200 in FIG. 1 are connected in an internal conduction. The pins are described as follows:
(1) MISO-Master Input Slave Output, a master unit data input, a slave unit data output;
(2) MOSI-Master Output Slave Input, master unit data out, slave unit data in;
(3) SCLK-Serial Clock, clock signal, generated by the host unit;
(4) CSB-Chip Select, slave unit enable signal, by the host unit control;
(5) Vsync-Vertical Synchronization, vertical sync signal, is controlled by the host unit.
As shown in FIG. 1, pin 1 (MOSI) of the master unit 100 is connected to pin 1 (MOSI) of the 1 st slave unit 200, pin 2 (MISO) of the i-th slave unit 200 is connected to pin 2 (MISO) of the (i+1) -th slave unit 200, and pin 2 (MISO) of the Nth slave unit 200 is connected back to pin 2 (MISO) of the master unit 100, constituting a data signal path, 1.ltoreq.i < N.
The pin 3 (SCLK) of the master unit 100 leads out a clock signal line, and the pin 3 (SCLK) of the N slave units 200 are connected in parallel on the clock signal line.
Pin 4 (CSB) of the master unit 100 leads out a chip select signal line, and pin 4 (CSB) of the N slave units 200 are connected in parallel to the chip select signal line.
The pin 5 (Vsync) of the master unit 100 leads out a synchronization signal line, and the pin 5 (Vsync) of the N slave units 200 are connected in parallel to the synchronization signal line.
In some alternative scenarios, there are some substrates where a single layer board (i.e., a single layer trace) is required, and no jumper is required, for example, a new type of liquid crystal panel, where a glass substrate is used, and no jumper is required. It should be noted that, for the Slave unit 200 (e.g., slave IC), the power lines and the ground lines are necessary, and the jumper cannot be required, so that in the daisy chain topology shown in fig. 1, the power lines and the ground lines of the Slave unit 200 are connected from the upper and lower sides of the row of Slave units 200, and it is difficult to input or output other signal lines in parallel.
In the daisy-chain topology shown in fig. 1, the last Slave unit 200 (e.g., slave IC) must have a line connected back to the master unit 100 (also known as master). This affects the routing on the substrate as required by the glass substrate described above.
In the daisy chain topology shown in fig. 1, although the writing of data by the master unit 100 (also referred to as master) to the Slave units 200 (e.g., slave ICs) is not synchronized, each Slave unit 200 (e.g., slave ICs) responds to the written data, and more synchronization (simultaneous) is required. Each Slave unit 200 (e.g., slave IC) needs to have a pin 5 (Vsync pin) for receiving synchronization information (alternatively, also called a synchronization signal, e.g., a narrow pulse signal) of the master unit 100 (also called master). For applications such as local dimming backlight, mini-LED backlight, micro-LED, etc. of the display system, the frequency of the synchronization signal is the image refresh rate. The time interval between the two synchronization signals will typically be greater than 1ms, for example an image refresh rate of 120Hz, with the interval between the two synchronization signals being approximately 8.3ms.
In addition, the line delay of the substrate in the daisy-chain topology shown in fig. 1 may be relatively large (reaching the order of hundreds ns), and the communication speed (bandwidth) of the SPI may be limited by the delay of the communication line.
In order to overcome the above problems, the embodiments of the present application further provide an alternative implementation, please refer to fig. 2, fig. 2 is a schematic diagram of a topology of the communication system provided by the embodiments of the present application. As shown in fig. 2, the communication system includes a master unit 100 and N slave units 200.
The clock signal pins (pins 1, sclk) of the master unit 100 are connected to the first clock signal pin (pins 1, sclki) of the 1 st slave unit 200, and the second clock signal pin (pins 2, sclko) of the i-th slave unit 200 is connected to the first clock signal pin (pins 1, sclki) of the i+1th slave unit 200, constituting a clock signal path.
Wherein the first clock signal pin and the second clock signal pin of the ith slave unit 200 are internally turned on.
The data signal pin (pin 3, mosi) of the master unit 100 is connected to the first data signal pin (pin 3, mosi) of the 1 st slave unit 200, and the second data signal pin (pin 4, miso) of the i-th slave unit 200 is connected to the first data signal pin (pin 3, mosi) of the i+1th slave unit 200, constituting a data signal path.
Wherein the first data signal pin and the second data signal pin of the ith slave unit 200 are internally turned on.
Wherein 1 is less than or equal to i < N, the first clock signal pin and the first data signal pin of the ith slave unit 200 are arranged on the first side of the ith slave unit 200, and the second clock signal pin and the second data signal pin of the ith slave unit 200 are arranged on the second side of the ith slave unit 200.
Alternatively, the first side of the ith slave unit 200 and the second side of the ith slave unit 200 may be any of the different sides of the ith slave unit 200. It should be noted that, for convenience of illustration, in fig. 2, the first side of the i-th slave unit 200 and the second side of the i-th slave unit 200 are opposite to each other, but the disclosure is not limited thereto.
In an alternative embodiment, the first side of the ith slave unit 200 is opposite the second side of the ith slave unit 200.
In order to meet the requirement that the substrate cannot be jumped, in the present application, the jumper function is performed through two pins (also called pins or pads) inside the Slave unit 200 (e.g., a Slave IC), for example, the corresponding jumper function is performed through any one of the first clock signal pin and the second clock signal pin and the first data signal pin and the second data signal pin. Compared to the topology structure shown in fig. 1, fig. 2 does not need to separately lead out the clock signal line, the chip select signal line and the synchronization signal line for connecting the Slave units 200 in parallel, and serial connection is completed through two pins inside the Slave units 200 (e.g., slave ICs), so that no conflict with other wires (e.g., power lines and ground lines) of the Slave units 200 occurs, and a jumper situation can be avoided.
In an alternative embodiment, the number of data signal pins of the master unit 100 may be plural (greater than 1), and the number of first data signal pins (pin 3, mosi) and second data signal pins (pin 4, miso) of each slave unit 200 may be plural (greater than 1), and H data signal channels may be configured.
Optionally, the H data signal pin (pin 3, mosi) of the host unit 100 is connected to the H first data signal pin (pin 3, mosi) of the 1 st slave unit 200, the H second data signal pin (pin 4, miso) of the i th slave unit 200 is connected to the H first data signal pin (pin 3, mosi) of the i+1 th slave unit 200, and the H data signal channels are formed, wherein 1.ltoreq.h.ltoreq.h, and H represents the number of data signal channels.
In the daisy-chain topology shown in fig. 1, the last Slave unit 200 (e.g., slave IC) must have a line (e.g., data line, MISO) connected back to the master unit 100 (also known as master). The last slave unit 200 transmits parameters such as the operation state of the slave unit 200 to the master unit 100 through the data line. When the data line exists, the basic wiring difficulty is greatly increased in order to meet the requirement of no jumper wire. To overcome this problem, the present embodiment provides an alternative implementation based on fig. 2, please refer to the following. Alternatively, the master unit 100 is configured to transmit clock signals to the N slave units 200 through the clock signal channels.
Alternatively, the master unit 100 is configured to transmit data signals to the N slave units 200 through the data signal channels.
Alternatively, the slave unit 200 may perform data exchange, including reading or writing, on the data signal path based on the received clock signal, so that interaction with the host unit 100 is performed through the data signal path under the control of the clock signal, including receiving the data signal sent by the host unit 100.
Optionally, the N slave units 200 are configured to execute the corresponding control instruction after waiting for the corresponding delay after receiving the data signal and encoding the synchronization signal.
Optionally, the delays corresponding to the N slave units 200 are all equal to a preset delay length, and the preset delay length may have a value of 0 or greater than 0. Or, the delays corresponding to the N slave units 200 are sequentially reduced, that is, the delay corresponding to the i-th slave unit 200 is greater than the delay corresponding to the i+1th slave unit 200, so that the N slave units 200 synchronously execute the corresponding control instructions after waiting for the corresponding delays respectively.
Optionally, the N slave units 200 are configured to wait for a first preset time interval when the received data signal is a first preset type of host request, and feed back the slave data to the host unit 100 through the data signal channel.
The first preset type of host request in the present application may be a read instruction type of host request, or may be any type of host request, including a host request encoded for a synchronization signal.
For how N slave units feed back slave data to the master unit 100, an alternative implementation is provided in the embodiments herein, please refer to the following.
The N slave units 200 respectively correspond to the N first preset time intervals, and sequentially increase from the first preset time interval corresponding to the 1 st slave unit 200 to the preset time interval corresponding to the nth slave unit 200.
After receiving the host request of the first preset type, the mth slave unit 200 waits for a first preset time interval corresponding to the first preset time interval, and serially transmits slave data of the mth slave unit 200 to the host unit 100 through the data signal channel, wherein m is greater than or equal to 1 and less than or equal to N.
That is, the 1 st slave unit 200 has the shortest corresponding first preset time interval, and the 1 st slave unit 200 feeds back corresponding slave data to the master unit 100 first, which is the 2 nd and 3 rd slave units in turn, until reaching the nth slave unit 200. In this case, the waiting time of the master unit 100 can be reduced as much as possible, and the slave data feedback can be completed as soon as possible.
It should be noted that, the preset time interval (including the first preset time interval and the second preset time interval hereinafter) in the present application may be obtained by the host unit 100 automatically arranging the slave unit 200 after the communication with the host unit 100 based on the communication delay, and the host unit 100 may write the obtained preset time interval into the register of the corresponding slave unit 200.
For how N slave units feed back slave data to the master unit 100, an alternative implementation is provided in the embodiments herein, please refer to the following.
Optionally, the first preset time intervals corresponding to the N slave units 200 are equal to or 0. Each slave unit 200 is provided with a buffer memory, and the buffer memory of the mth slave unit 200 is used for storing data returned by the (m+1) th slave unit 200 through a data signal channel, wherein m < N is more than or equal to 1.
After receiving the request of the first preset type of the host, the kth slave unit 200 transmits own slave data to the kth-1 slave unit 200 through a data signal channel, and after the transmission of own slave data is completed, the slave data in the buffer memory of the kth slave unit 200 is transmitted to the kth-1 slave unit 200,2, wherein k is less than or equal to N.
The 1 st slave unit 200 transmits own slave data to the master unit 100 through the data signal channel after receiving the first preset type of master request, and transmits the slave data in its buffer memory to the master unit 100 after the own slave data transmission is completed.
It should be understood that, by setting the buffer to store the slave data of the back end, and feeding back the slave data of the back end in the buffer to the front end after the feedback of the slave data of the back end is completed, it is ensured that the host unit 100 can obtain the slave data of all the slave units 200.
On the basis of fig. 2, regarding how to overcome the problem in fig. 1, an alternative implementation manner is further provided in the embodiment of the present application, please refer to fig. 3, and fig. 3 is a second schematic diagram of the topology of the communication system provided in the embodiment of the present application.
As shown in fig. 3, the master unit 100 is further provided with a synchronization signal pin, and the slave unit 200 is further provided with a first synchronization signal pin (pin 5, vsyncio) and a second synchronization signal pin. Optionally, the synchronization signal pin (pin 5, vsync) of the master unit 100 is connected to the first synchronization signal pin (pin 5, vsyncio) of the 1 st slave unit 200, and the second synchronization signal pin (pin 6, vsyncoi) of the i-th slave unit 200 is connected to the first synchronization signal pin (pin 5, vsyncio) of the i+1th slave unit 200, so as to form a synchronization signal channel.
Wherein the first and second sync signal pins of the ith slave unit 200 are turned on internally.
The first synchronization signal pin of the ith slave unit 200 is disposed on the first side of the ith slave unit 200, and the second synchronization signal pin of the ith slave unit 200 is disposed on the second side of the ith slave unit 200.
In the daisy-chain topology shown in fig. 1, the last Slave unit 200 (e.g., slave IC) must have a line (e.g., data line, MISO) connected back to the master unit 100 (also known as master). The last slave unit 200 transmits parameters such as the operation state of the slave unit 200 to the master unit 100 through the data line. When the data line exists, the basic wiring difficulty is greatly increased in order to meet the requirement of no jumper wire. And because the data length of slave unit 200 may be different each time slave unit 100 is written. The data transmitted by the slave unit 200 to the host unit 100 through the MISO must be serially concatenated in time with the data transmitted by the host unit 100 to the slave unit 200.
To overcome this problem, the present embodiment provides an alternative implementation based on fig. 3, please refer to the following.
The master unit 100 is configured to transmit clock signals to the N slave units 200 through the clock signal path.
The master unit 100 is configured to transmit data signals to the N slave units 200 through the data signal path.
The master unit 100 is configured to transmit a synchronization signal to the N slave units 200 through the synchronization signal path.
The N slave units 200 are configured to execute corresponding control instructions after waiting for corresponding delays after receiving the synchronization signals.
Optionally, the delays corresponding to the N slave units 200 are all equal to a preset delay length, and the preset delay length may have a value of 0 or greater than 0. Or, the delays corresponding to the N slave units 200 are sequentially reduced, that is, the delay corresponding to the i-th slave unit 200 is greater than the delay corresponding to the i+1th slave unit 200, so that the N slave units 200 synchronously execute the corresponding control instructions after waiting for the corresponding delays respectively.
The N slave units 200 are configured to wait for a second preset time interval when the received data signal is a first preset type of host request, and feed back slave data to the host unit 100 through the synchronization signal channel.
And/or, the N slave units 200 are configured to wait for a second preset time interval after receiving the synchronization signal, and feed back slave data to the master unit 100 through the synchronization signal channel.
In the case of the ith slave unit 200 (the case of performing the slave data feedback based on the first preset type of the master request and the case of performing the slave data feedback based on the synchronization signal), the corresponding second preset time intervals may be the same or different.
It should be noted that, the host unit 100 does not send a synchronization signal through the synchronization signal channel in a specified period after sending a first preset type of host request through the data channel, so that multiplexing the synchronization signal channel feedback slave data does not collide.
Alternatively, the slave data may be, but not limited to, the working state data (e.g. the chip junction temperature) of the slave unit 200 or the data corresponding to the read request when the master request is the read request.
As described above, the time interval between the two synchronization signals is long, for example, greater than 1ms, and the time required for the N slave units 200 to feed back the slave data to the master unit 100 is smaller than the time interval between the two synchronization signals, so that the synchronization signal channel is multiplexed as the data feedback channel of the slave unit 200. The signal transmission direction of the data feedback channel is opposite to the signal transmission direction of the data signal channel. And new pins and wires are not required to be introduced, so that the wiring difficulty can be greatly reduced, and the jumper problem is improved.
In an alternative embodiment, the time interval of the two synchronization signals (narrow pulses) is 1ms. After the synchronization signal transmitted from the host unit 100 is completed, the slave unit 200 feeds back slave data to the host unit 100 while waiting for 100 us. Alternatively, the feedback data may be started by the last slave unit 200, or may be started by the first slave unit 200, which is not limited herein. Within the time interval of two synchronization signals (narrow pulses), optionally within 800us, the data is input by Vsyncoi and the data is output by Vsyncio, serially transferred to the host unit 100. After all slave units 200 have completed feedback, the synchronization signal path is reset, waiting for the next arrival of a synchronization signal (narrow pulse) issued by the host unit 100.
Optionally, compared with the topology structure shown in fig. 1, the scheme of the application does not need to introduce new pins and wires, so that wiring difficulty can be greatly reduced, and jumper problem can be improved. Moreover, by multiplexing the synchronization signal channel as a data feedback channel of the slave unit 200, the bandwidth of data transmission can be greatly improved, for example, by nearly one time.
For how N slave units feed back slave data to the master unit 100, an alternative implementation is provided in the embodiments herein, please refer to the following.
In an alternative embodiment, the N slave units 200 respectively correspond to the N second preset time intervals, the mth slave unit 200 waits for the corresponding second preset time interval after receiving the synchronization signal, and serially transmits the slave data of the mth slave unit 200 to the host unit 100 through the synchronization signal channel, where 1 is less than or equal to m is less than or equal to N, so that the feedback of the slave data is completed by multiplexing the synchronization signal channel as a data feedback channel of the slave unit 200.
Alternatively, the N slave units 200 respectively correspond to N second preset time intervals, and sequentially increase from the second preset time interval corresponding to the 1 st slave unit 200 to the second preset time interval corresponding to the nth slave unit 200. That is, the second preset time interval corresponding to the 1 st slave unit 200 is shortest, and the 1 st slave unit 200 feeds back corresponding slave data to the master unit 100 first, which is the 2 nd and 3 rd slave units in turn, until reaching the nth slave unit 200. In this case, the waiting time of the master unit 100 can be reduced as much as possible, and the slave data feedback can be completed as soon as possible.
Alternatively, the N slave units 200 respectively correspond to N second preset time intervals, and sequentially increase from the second preset time interval corresponding to the nth slave unit 200 to the second preset time interval corresponding to the 1 st slave unit 200. That is, the second preset time interval corresponding to the nth slave unit 200 is shortest, and the nth slave unit 200 feeds back corresponding slave data to the master unit 100 first, which is sequentially the nth-1 and the nth-2, until reaching the 1 st slave unit 200.
For how N slave units feed back slave data to the master unit 100, an alternative implementation is provided in the embodiments herein, please refer to the following.
Optionally, the second preset time intervals corresponding to the N slave units 200 are equal to or 0. Each slave unit 200 is provided with a buffer memory, and the buffer memory of the mth slave unit 200 is used for storing data returned by the (m+1) th slave unit 200 through a synchronous signal channel, wherein m < N is more than or equal to 1.
After receiving the request of the first preset type of the host, the kth slave unit 200 transmits own slave data to the kth-1 slave unit 200 through a synchronous signal channel, and after the transmission of own slave data is completed, the slave data in the buffer memory of the kth slave unit 200 is transmitted to the kth-1 slave unit 200,2, wherein k is less than or equal to N.
The 1 st slave unit 200 transmits its own slave data to the master unit 100 through the synchronization signal channel after receiving the first preset type of master request, and transmits its own slave data in the buffer to the master unit 100 after its own slave data transmission is completed.
Alternatively, the first side of the ith slave unit 200 and the second side of the ith slave unit 200 are opposite to each other. The first clock signal pin and the second clock signal pin of the ith slave unit 200 are symmetrically arranged based on the center line of the ith slave unit 200. The first data signal pin and the second data signal pin of the ith slave unit 200 are symmetrically arranged based on the center line of the ith slave unit 200. The first and second sync signal pins of the ith slave unit 200 are symmetrically arranged based on the center line of the ith slave unit 200.
Optionally, in this application, the mating pins are disposed opposite to each other, so as to avoid cross-jumper of the wires of the slave units 200, and the mating pins may also be referred to as Twin-Pin.
Optionally, the pair of pins refers to any one of the first clock signal pin and the second clock signal pin, the first data signal pin and the second data signal pin, and the first synchronization signal pin and the second synchronization signal pin.
Alternatively, the mating pins may be wired inside the slave unit 200, such as by RDL wires.
In order to increase the driving capability, the embodiment of the present application further provides an alternative implementation, please refer to the following.
A relay component is provided between the mating pins of the ith slave unit 200.
The matched pins refer to any one group of a first clock signal pin and a second clock signal pin, a first data signal pin and a second data signal pin, and a first synchronous signal pin and a second synchronous signal pin.
Optionally, the relay component includes, but is not limited to, an even-numbered stage inverter.
In an alternative embodiment, the first data signal pin and the second data signal pin and/or the first synchronization signal pin and the second synchronization signal pin are paired pins requiring bidirectional interaction. Two sets of relay components, namely a middle relay component and an inverse relay component, are arranged between the paired pins of the bi-directional interaction of the ith slave unit 200, and only one set of the middle relay component and the inverse relay component is in an on state at the same time, for example, when the master unit 100 sends a signal to the slave unit 200, the middle relay component is started, and when the slave unit 200 sends a signal to the master unit 100, the inverse relay component is started.
The slave unit 200 and the master unit 100 may control the channels according to the corresponding signal transfer directions, for example, perform reset, etc., to switch the on states of the respective relay components in the data signal channels and/or the synchronization signal channels.
Optionally, a relay component may also be disposed between the paired pins of the nth slave unit 200.
Optionally, in the scheme of the present application, the data signal channel and the clock signal channel process data in a dual-edge triggering manner.
In contrast to clock (SCLK) single edge (rising edge or falling edge) triggers, clock (SCLK) double edge (rising edge and falling edge) triggers may be defined in the present application. Specifically, referring to fig. 4, fig. 4 is a schematic diagram of dual edge triggering according to an embodiment of the present application. Where CLK represents a clock signal and DATA represents a DATA signal. Optionally, SCLK is delayed for a time t1, and then exclusive OR operation is performed with the original SCLK, so as to obtain the frequency multiplication clk, and then the rising or falling edge of clk is used for processing data. In so doing, the transmission bandwidth of the data can be doubled.
It should be noted that, on a high-delay substrate, a bottleneck in data transmission is not the processing speed of signals inside the integrated circuit. But rather the delay of the signal on the substrate trace. According to the scheme, through methods of double-edge triggering, multiplexing synchronous signal channel transmission and the like, the speed of a transmission protocol similar to an SPI architecture can be improved by 4 times or more. This is very valuable for applications requiring high speed transmission.
Optionally, in the scheme of the present application, the synchronous signal channel and the clock signal channel process data in a dual-edge triggering manner.
In an alternative embodiment, the second power pin of the ith slave unit 200 is connected to the first power pin of the (i+1) th slave unit 200 to form a power channel; the first power pin of the 1 st slave unit 200 is used for accessing power, or the second power pin of the nth slave unit 200 is used for accessing power, or the power channel is used for accessing power, i.e. any point in the power channel can be used for accessing power.
The first power pin of the ith slave unit 200 is disposed on the third side of the ith slave unit 200, and the second power pin of the ith slave unit 200 is disposed on the fourth side of the ith slave unit 200.
In an alternative embodiment, the number of the first power pins and the second power pins of each slave unit 200 may be plural (greater than 1), and W power channels, that is, W power lines may be formed. It should be noted that, the ground wire may also be used as a power wire, and the power connected to the ground wire may also be a power ground.
The third side of the ith slave unit 200 and the fourth side of the ith slave unit 200 are different sides of the ith slave unit 200, e.g. opposite sides from each other.
In an alternative embodiment, the first side and the third side of the ith slave unit 200 are the same side, and the second side and the fourth side of the ith slave unit 200 are the same side.
Optionally, the first side, the second side, the third side, and the fourth side of the ith slave unit 200 are different sides, respectively. Taking the 1 st slave unit 200 as an example, a side of the 1 st slave unit 200 connected to the master unit 100 is a first side (left side), a side of the 1 st slave unit 200 connected to the second slave unit 200 is a second side (right side), an upper or lower part of the 1 st slave unit 200 is a third side, and the other one of the upper and lower parts of the 1 st slave unit 200 is a fourth side.
Optionally, the parasitic resistance of the internal connection between the first power pin and the second power pin of the ith slave unit 200 is smaller than a preset resistance value.
The embodiment of the application also provides a communication method, which is applied to the communication system shown in fig. 3, please refer to the following, and the communication method includes: s101, S102, S103, S104, and S105 are specifically described below.
S101, the master unit sends clock signals to N slave units through the clock signal channels.
S102, the master unit sends data signals to the N slave units through the data signal channels.
S103, the master unit sends synchronous signals to the N slave units through synchronous signal channels.
And S104, after receiving the synchronous signals, the N slave units respectively wait for corresponding delay and execute corresponding control instructions.
S105, when the received data signal is a first preset type of host request, the N slave units wait for a second preset time interval, and the slave data is fed back to the host unit through the synchronous signal channel.
And/or, the N slave units are used for waiting for a second preset time interval after receiving the synchronization signal, and feeding back slave data to the master unit through the synchronization signal channel.
The embodiment of the application also provides a communication method, which is applied to the communication system shown in fig. 2, please refer to the following, and the communication method includes: s111, S112, S113, and S114 are specifically described below.
S111, the master unit sends clock signals to the N slave units through the clock signal channels.
S112, the master unit transmits data signals to the N slave units through the data signal channels.
S113, after receiving the data signals and encoding the synchronous signals, the N slave units respectively wait for corresponding delay and execute corresponding control instructions.
And S114, when the received data signals are the host requests of the first preset type, the N slave units wait for a first preset time interval, and the slave data are fed back to the host units through the data signal channels.
It should be noted that, the communication method provided in this embodiment is applied to the above-mentioned communication system, and may perform the functional uses shown in the above-mentioned system embodiment, so as to achieve the corresponding technical effects. For a brief description, reference is made to the corresponding parts of the above embodiments, where this embodiment is not mentioned.
In summary, the embodiments of the present application provide a communication system and a method, where the communication system includes a master unit and N slave units; the clock signal pin of the host unit is connected with the first clock signal pin of the 1 st slave unit, the second clock signal pin of the i-th slave unit is connected with the first clock signal pin of the i+1-th slave unit, and a clock signal channel is formed; the data signal pin of the host unit is connected with the first data signal pin of the 1 st slave unit, and the second data signal pin of the i-th slave unit is connected with the first data signal pin of the i+1-th slave unit to form a data signal channel; wherein i < N is not less than 1, the first clock signal pin and the first data signal pin of the ith slave unit are arranged on the first side of the ith slave unit, and the second clock signal pin and the second data signal pin of the ith slave unit are arranged on the second side of the ith slave unit. The jumper function is completed through two pins inside the slave unit, a clock signal line, a chip selection signal line and a synchronous signal line which are used for connecting all the slave units in parallel do not need to be independently led out, and serial connection is completed through two pins inside the slave unit, so that conflict with other wiring of the slave unit can be avoided, and the condition of jumper wire can be avoided.
The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the same, but rather, various modifications and variations may be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.
It will be evident to those skilled in the art that the present application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Claims (21)
1. A communication system comprising a master unit and N slave units;
the clock signal pin of the host unit is connected with the first clock signal pin of the 1 st slave unit, the second clock signal pin of the i th slave unit is connected with the first clock signal pin of the i+1 th slave unit, and a clock signal channel is formed;
The data signal pins of the host unit are connected with the first data signal pins of the 1 st slave unit, the second data signal pins of the i th slave unit are connected with the first data signal pins of the i+1 th slave unit, and a data signal channel is formed;
wherein i < N is not less than 1, a first clock signal pin and a first data signal pin of an ith slave unit are arranged on a first side of the ith slave unit, and a second clock signal pin and a second data signal pin of the ith slave unit are arranged on a second side of the ith slave unit;
the host unit is used for sending clock signals to the N slave units through the clock signal channels;
the host unit is used for sending data signals to the N slave units through the data signal channels;
the N slave units are used for executing corresponding control instructions after waiting for corresponding delay after receiving the data signals which are synchronous signal codes;
the N slave units are used for waiting for a first preset time interval when the received data signals are the first preset type of host requests, and feeding back slave data to the host units through the data signal channels;
The N slave units respectively correspond to N first preset time intervals, the mth slave unit waits for the corresponding first preset time interval after receiving a first preset type of host request, and the data signal channel is used for serially transmitting the slave data of the mth slave unit to the host unit, wherein m is more than or equal to 1 and less than or equal to N.
2. The communication system of claim 1, wherein the first preset time interval increases sequentially from the first preset time interval corresponding to the 1 st slave unit to the first preset time interval corresponding to the nth slave unit.
3. The communication system of claim 1, wherein a relay component is disposed between mating pins of an ith of the slave units;
the pair of pins refers to any one group of the first clock signal pin and the second clock signal pin and the first data signal pin and the second data signal pin.
4. A communication system as claimed in claim 3, wherein the relay component comprises an even number of stages of inverters.
5. A communication system as claimed in any one of claims 1 to 4, wherein the data signal path and the clock signal path process data in a double edge triggered manner.
6. A communication system as claimed in any one of claims 1 to 4, characterized in that,
the second power supply pin of the ith slave unit is connected with the first power supply pin of the (i+1) th slave unit to form a power supply channel;
the first power supply pin of the 1 st slave unit is used for being connected with a power supply, or the second power supply pin of the N th slave unit is used for being connected with the power supply, or the power supply channel is used for being connected with the power supply;
the first power pin of the ith slave unit is arranged on the third side of the ith slave unit, and the second power pin of the ith slave unit is arranged on the fourth side of the ith slave unit.
7. A communication system comprising a master unit and N slave units;
the clock signal pin of the host unit is connected with the first clock signal pin of the 1 st slave unit, the second clock signal pin of the i th slave unit is connected with the first clock signal pin of the i+1 th slave unit, and a clock signal channel is formed;
the data signal pins of the host unit are connected with the first data signal pins of the 1 st slave unit, the second data signal pins of the i th slave unit are connected with the first data signal pins of the i+1 th slave unit, and a data signal channel is formed;
Wherein i < N is not less than 1, a first clock signal pin and a first data signal pin of an ith slave unit are arranged on a first side of the ith slave unit, and a second clock signal pin and a second data signal pin of the ith slave unit are arranged on a second side of the ith slave unit;
the host unit is used for sending clock signals to the N slave units through the clock signal channels;
the host unit is used for sending data signals to the N slave units through the data signal channels;
the N slave units are used for executing corresponding control instructions after waiting for corresponding delay after receiving the data signals which are synchronous signal codes;
the N slave units are used for waiting for a first preset time interval when the received data signals are the first preset type of host requests, and feeding back slave data to the host units through the data signal channels;
each slave unit is provided with a cache, and the m-th cache of the slave unit is used for storing data returned by the m+1th slave unit through the data signal channel, wherein m is more than or equal to 1 and less than N;
the kth slave unit transmits own slave data to the kth-1 slave unit through the data signal channel after receiving a first preset type of host request, and transmits slave data in a cache of the kth slave unit to the kth-1 slave unit after completing own slave data transmission, wherein k is more than or equal to 2 and less than or equal to N;
And after receiving a first preset type of host request, the 1 st slave unit transmits own slave data to the host unit through the data signal channel, and after the own slave data transmission is completed, the slave data in the cache is transmitted to the host unit.
8. The communication system of claim 7, wherein a relay component is disposed between mating pins of an ith of the slave units;
the pair of pins refers to any one group of the first clock signal pin and the second clock signal pin and the first data signal pin and the second data signal pin.
9. The communication system of claim 8, wherein the relay component comprises an even-numbered stage of inverters.
10. A communication system as claimed in any one of claims 7 to 9, wherein the data signal path and the clock signal path process data in a double edge triggered manner.
11. A communication system as claimed in any one of claims 7 to 9, characterized in that,
the second power supply pin of the ith slave unit is connected with the first power supply pin of the (i+1) th slave unit to form a power supply channel;
the first power supply pin of the 1 st slave unit is used for being connected with a power supply, or the second power supply pin of the N th slave unit is used for being connected with the power supply, or the power supply channel is used for being connected with the power supply;
The first power pin of the ith slave unit is arranged on the third side of the ith slave unit, and the second power pin of the ith slave unit is arranged on the fourth side of the ith slave unit.
12. A communication system comprising a master unit and N slave units;
the clock signal pin of the host unit is connected with the first clock signal pin of the 1 st slave unit, the second clock signal pin of the i th slave unit is connected with the first clock signal pin of the i+1 th slave unit, and a clock signal channel is formed;
the data signal pins of the host unit are connected with the first data signal pins of the 1 st slave unit, the second data signal pins of the i th slave unit are connected with the first data signal pins of the i+1 th slave unit, and a data signal channel is formed;
wherein i < N is not less than 1, a first clock signal pin and a first data signal pin of an ith slave unit are arranged on a first side of the ith slave unit, and a second clock signal pin and a second data signal pin of the ith slave unit are arranged on a second side of the ith slave unit; the synchronous signal pin of the host unit is connected with the first synchronous signal pin of the 1 st slave unit, the second synchronous signal pin of the i th slave unit is connected with the first synchronous signal pin of the i+1 th slave unit, and a synchronous signal channel is formed;
The first synchronous signal pin of the ith slave unit is arranged on the first side of the ith slave unit, and the second synchronous signal pin of the ith slave unit is arranged on the second side of the ith slave unit.
13. The communication system of claim 12, wherein,
the host unit is used for sending clock signals to the N slave units through the clock signal channels;
the host unit is used for sending data signals to the N slave units through the data signal channels;
the host unit is used for sending synchronous signals to the N slave units through the synchronous signal channels;
the N slave units are used for executing corresponding control instructions after waiting for corresponding delay after receiving the synchronous signals respectively;
the N slave units are used for waiting for a second preset time interval when the received data signals are the first preset type of host requests, and feeding back slave data to the host units through the synchronous signal channels;
and/or the N slave units are used for waiting for a second preset time interval after receiving the synchronizing signals, and feeding back slave data to the master unit through the synchronizing signal channels.
14. The communication system according to claim 13, wherein the N slave units correspond to N second preset time intervals, respectively, and sequentially increase from a second preset time interval corresponding to a 1 st slave unit to a second preset time interval corresponding to an nth slave unit;
and after receiving the synchronizing signal, the mth slave unit waits for a second preset time interval corresponding to the synchronizing signal, and serially transmits slave data of the mth slave unit to the host unit through the synchronizing signal channel, wherein m is more than or equal to 1 and less than or equal to N.
15. The communication system of claim 13, wherein each of said slave units is provided with a buffer, and an mth of said buffers of said slave units is used for storing data returned by an mth+1th of said slave units through said synchronization signal path, wherein 1.ltoreq.m < N;
the kth slave unit transmits own slave data to the kth-1 slave unit through the synchronous signal channel after receiving a first preset type of host request, and transmits slave data in a cache to the kth-1 slave unit after the own slave data transmission is completed, wherein k is more than or equal to 2 and less than or equal to N;
And after receiving a first preset type of host request, the 1 st slave unit transmits own slave data to the host unit through the synchronous signal channel, and after the own slave data transmission is completed, the slave data in the cache of the 1 st slave unit is transmitted to the host unit.
16. The communication system of claim 12, wherein a relay component is disposed between mating pins of an ith of the slave units;
the pair of pins refers to any one group of the first clock signal pin and the second clock signal pin and the first data signal pin and the second data signal pin.
17. The communication system of claim 16, wherein the relay component comprises an even-numbered stage of inverters.
18. A communication system as claimed in any one of claims 12 to 17, wherein the data signal path and the clock signal path process data in a double edge triggered manner.
19. A communication system as claimed in any one of claims 12 to 17, characterized in that,
the second power supply pin of the ith slave unit is connected with the first power supply pin of the (i+1) th slave unit to form a power supply channel;
The first power supply pin of the 1 st slave unit is used for being connected with a power supply, or the second power supply pin of the N th slave unit is used for being connected with the power supply, or the power supply channel is used for being connected with the power supply;
the first power pin of the ith slave unit is arranged on the third side of the ith slave unit, and the second power pin of the ith slave unit is arranged on the fourth side of the ith slave unit.
20. A communication method applied to the communication system of claim 12, the method comprising:
the host unit sends clock signals to the N slave units through the clock signal channels;
the host unit sends data signals to the N slave units through the data signal channels;
the host unit sends synchronizing signals to the N slave units through the synchronizing signal channels;
after receiving the synchronous signals, the N slave units respectively wait for corresponding delay and execute corresponding control instructions;
when the received data signals are the host requests of the first preset type, the N slave units wait for a second preset time interval and feed back slave data to the host units through the synchronous signal channels;
And/or the N slave units are used for waiting for a second preset time interval after receiving the synchronizing signals, and feeding back slave data to the master unit through the synchronizing signal channels.
21. A communication method applied to the communication system of claim 1 or 7, the method comprising:
the host unit sends clock signals to the N slave units through the clock signal channels;
the host unit sends data signals to the N slave units through the data signal channels;
after receiving the data signals and encoding the synchronous signals, the N slave units respectively wait for corresponding delay and execute corresponding control instructions;
and the N slave units wait for a first preset time interval when the received data signals are the first preset type of host requests, and feed back slave data to the host units through the data signal channels.
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