TWI550573B - Display device and method for transmitting and processing clock embedded data - Google Patents

Description

Display device and embedded clock data transmission and processing method

The invention relates to an image compensating element and a manufacturing method thereof, in particular to an image compensating element arranged above a display panel and a manufacturing method thereof.

Existing display devices generally include a plurality of functional circuits for driving a display panel, such as a timing control circuit, a data driving circuit, and a scan driving circuit, which are generally present in the form of integrated circuit chips. Due to the driving needs, data transmission is required between the functional circuits. However, due to the fixed and high operating frequency of each functional circuit, there is a large electromagnetic interference in the data transmission process. Especially for the circuit architecture of multi-channel point-to-point transmission of clock embedded data, the electromagnetic interference phenomenon is more serious due to the higher operating frequency.

In view of this, it is necessary to provide a display device capable of improving electromagnetic interference.

In view of this, it is necessary to provide a method for processing embedded clock data that can improve electromagnetic interference.

A display device includes a timing control circuit, a data driving circuit and a display panel, wherein the timing control circuit is configured to transmit embedded clock data to the data driving circuit, and the data driving circuit is configured to output a driving voltage to the display panel, and the timing control An embedded clock data transmission interface is included between the circuit and the data driving circuit, and the timing control is The circuit includes a first output unit and a second output unit, the data driving circuit includes a first receiving unit and a second receiving unit, the embedded clock data transmission interface includes a first transmission channel and a second transmission channel, the first transmission The channel is connected between the first output unit and the first receiving unit, and the second transmission channel is connected between the first output unit and the second receiving unit, the embedded clock data includes N first data packets and N a second data packet, the first output unit sequentially outputs the N first data packets through the first transmission channel to the first receiving unit, and the second output unit sequentially outputs the N second data packets through the second a transmission channel to the second receiving unit, in the embedded clock data transmission interface, the ith second data packet has a predetermined time delay relative to the ith first data packet in a transmission time, where N is greater than A natural number of 1, i is a natural number greater than or equal to 1 and less than or equal to N.

An embedded clock data transmission and processing method includes the following steps: providing an embedded clock data, wherein the embedded clock data includes N first data packets and N second data packets, where N is greater than 1 Providing a first transmission channel and a second transmission channel, the first transmission channel being connected between the first output unit and the first receiving unit, the second transmission channel being connected between the first output unit and the second receiving unit The first output unit sequentially outputs the N first data packets through the first transmission channel to the first receiving unit; and the second output unit sequentially outputs the N second data packets through the second transmission channel to The second receiving unit, wherein the ith second data packet has a delay time of a predetermined time with respect to the ith first data packet, and i is a natural number greater than or equal to 1 and less than or equal to N.

In the display device and method of the present invention, the data packet transmission time of the first transmission channel and the second transmission channel are not consistent, but the second data packet has a delay relative to the first data packet, which can effectively improve the first and second The electromagnetic interference phenomenon caused by the synchronous transmission of the data packet is a serious problem, and the electromagnetic interference in the transmission process of the display device and its embedded clock data is reduced.

100, 200, 300, 400, 500, 600‧‧‧ display devices

110, 410‧‧‧ timing control circuit

120, 220, 320, 420, 520, 620‧‧‧ data drive circuit

130, 430‧‧‧ display panel

140, 240, 440, 540, 640‧‧‧ embedded clock data transmission interface

141, 441‧‧‧ first transmission channel

142, 442‧‧‧ second transmission channel

111‧‧‧First output unit

112‧‧‧Second output unit

113, 413‧‧‧ data processing circuit

114, 414‧‧‧ Delay Control Unit

121, 221, 321‧‧‧ first receiving unit

122, 222, 322‧‧‧second receiving unit

T0‧‧‧ basic transmission time

Td‧‧‧ scheduled time

141a, 142a‧‧‧ transmission line

141b, 142b‧‧‧ negative transmission line

111a, 112a‧‧‧ positive output

111b, 112b‧‧‧ negative output

121a, 122a‧‧‧ receiving end

121b, 122b‧‧‧ negative receiving end

123, 223, 323‧‧‧ first amplifier

124, 224, 324, 524‧‧ second amplifier

125, 225, 325‧‧‧ first data recovery circuit

126, 226, 326, 526‧‧‧ second data recovery circuit

127, 227, 327‧‧‧ first clock recovery circuit

128, 228, 328‧‧‧ second clock recovery circuit

229, 326a‧‧ ‧ inverter

326b‧‧‧Data Recovery Unit

443‧‧‧ third transmission channel

444‧‧‧fourth transmission channel

415‧‧‧ third output unit

416‧‧‧fourth output unit

451‧‧‧ third receiving unit

452‧‧‧fourth receiving unit

453, 653‧‧ Third amplifier

454, 554, 654‧‧ ‧ fourth amplifier

455, 655‧‧‧ third data recovery circuit

456, 556, 656‧‧‧ fourth data recovery circuit

457‧‧‧ Third clock recovery circuit

458‧‧‧ Fourth clock recovery circuit

529, 629‧‧‧ first inverter

559, 659‧‧‧ second inverter

S1~S4‧‧‧ steps

1 is a circuit block diagram of a display device according to a first embodiment of the present invention.

2 is a timing diagram of embedded clock data transmitted on the embedded clock data transmission interface shown in FIG. 1.

3 is a timing diagram of embedded clock data of a modified embodiment of the display device shown in FIG. 1.

4 is a block diagram of a display device according to a second embodiment of the present invention.

FIG. 5 is a timing diagram of embedded clock data transmitted on the embedded clock data transmission interface shown in FIG.

Fig. 6 is a block diagram of a display device according to a third embodiment of the present invention.

Fig. 7 is a block diagram of a display device according to a fourth embodiment of the present invention.

8 is a timing diagram of embedded clock data transmitted on the embedded clock data transmission interface shown in FIG.

Fig. 9 is a block diagram of a display device according to a fifth embodiment of the present invention.

10 is a timing diagram of embedded clock data transmitted on the embedded clock data transmission interface shown in FIG.

Figure 11 is a block diagram of a display device according to a sixth embodiment of the present invention.

12 is a timing diagram of embedded clock data transmitted on the embedded clock data transmission interface shown in FIG.

13 is a flow chart of a method for transmitting and processing embedded clock data of the present invention.

The invention will now be further described in detail in conjunction with the drawings.

Please refer to FIG. 1. FIG. 1 is a circuit block diagram of a display device 100 according to a first embodiment of the present invention. The display device 100 includes a timing control circuit 110, a data driving circuit 120, and a display panel 130. The timing control circuit 110 is configured to transmit embedded clock data to the data driving circuit 120. The data driving circuit 120 is for outputting a driving voltage to the display panel 130. The timing control circuit 110 and the data driving circuit 120 include an embedded clock data transmission interface 140.

The timing control circuit 110 includes a first output unit 111 and a second output unit 112. The data driving circuit 120 includes a first receiving unit 121 and a second receiving unit 122. The embedded clock data transmission interface 140 includes a first transmission channel 141 and a second transmission channel 142. The first transmission channel 141 is connected between the first output unit 111 and the first receiving unit 121. The second transmission channel 142 is connected between the second output unit 112 and the second receiving unit 122.

The embedded clock data includes N first data packets and N second data packets. The N first data packets sequentially output by the first output unit 111 pass through the first transmission channel 141 to the first receiving unit 121, and the N second data packets sequentially output by the second output unit 112 pass the first The second transmission channel 142 is to the second receiving unit 122. Specifically, in the embedded clock data transmission interface, the i-th The second packet has a delay of a predetermined time Td with respect to the i-th first packet, wherein N is a natural number greater than 1, and i is a natural number greater than or equal to 1 and less than or equal to N. Please refer to FIG. 2. FIG. 2 is a timing diagram of the ith first data packet and the ith second data packet transmitted on the embedded clock data transmission interface.

It can be understood that, for one type of transmission interface, the N first data packets and the N second data packets have substantially the same length, and each of the first data packets and each of the second data packets can be a binary code. , which includes M bits, such as H0, H1, D0, D1, ..., D(M-3) and H0', H1', D0', D1', ..., D (M-3) )'. The values of M may be different for different transmission interfaces. Preferably, the value of M may be in the range of 12-27, as in one embodiment, M is 14, and in another embodiment, M is 27.

Further, it is assumed that the basic transmission time of each bit is T0. Preferably, the delay time Td is greater than or equal to T0/2 ^x and less than T0, where x is a natural number, and for different types of transmission interfaces, the value of x may be Differently, preferably, X is in the range of 3 to 5, such as when x = 4, Td is greater than or equal to T0/2 ⁴ and less than T0, and when x = 5, Td is greater than or equal to T0/2 ⁵ and less than T0.

Specifically, for different transmission interfaces, the basic transmission time of each bit may be different, but it can be understood that the basic transmission time of each bit is related to the transmission rate of the transmission interface, and the embedded clock data transmission interface is set. The transmission rate is V bits per second, and the basic transmission time of each bit is T0=1/V seconds. For example, in the present embodiment, the transmission rate V ranges from 200 megabits per picosecond (200 Mb/ps) to 4 gigabits per picosecond (4 Gb/ps), so that the basic transmission time T0 of each bit The range is from 5 nanoseconds (ns) to 250 picoseconds (ps). Among them, 1 nanosecond = 0.000000000001 seconds (that is, 10 ^{-9 wonderful} ), 1 picosecond = 0.0000000000001 seconds (10 ^{-12 wonderful} ).

In particular, in the transmission interface provided by the embodiment, the first two bits of each data packet (such as H0, H1, and H0', H1') belong to the clock signal bit, and the remaining bits (D0, D1, ...) D(M-3) and D0', D1', ..., D(M-3)') belong to the data signal bit. Of course, in a modified implementation manner, in another embedded data transmission interface, the clock signal of each data packet may not be located in the first two bits, but embedded in the data signal, and located in other bits. . Further, in an embodiment of the present embodiment, the clock signal bit of the ith first data packet is opposite to the clock signal bit of the ith second data packet, such as H0 and H0' is opposite in phase, H1 is opposite to H1', and the data signal bit of the i-th first data packet is in the same phase as the data signal bit of the i-th second data packet, such as D0, D1, ..., D(M-3) is the same phase as D0', D1', ..., D(M-3)', respectively. Of course, in another embodiment of the present embodiment, the clock signal bit of the ith first data packet and the clock signal bit phase of the ith second data packet may be the same, such as the H0 and H0' phases. Similarly, H1 and H1' are in the same phase, and the data signal bit of the i-th first data packet is in the same phase as the data signal bit of the i-th second data packet.

Further, in the embodiment, the first transmission channel 141 and the second transmission channel 142 respectively transmit the N first data packets and the N second data packets in a differential transmission manner. Therefore, each transmission channel 141 And 142 includes positive transmission lines 141a, 142a and negative transmission lines 141b, 142b. Correspondingly, each of the output units 111 and 112 includes positive output ends 111a, 112a and negative output ends 111b, 112b, and each receiving unit 121 and 122 includes positive The receiving ends 121a and 122a and the negative receiving ends 121b and 122b.

The timing control circuit 110 further includes a data processing circuit 113 and a delay control unit 114. The data processing circuit 113 receives the image data and processes the image data to Obtaining the first data signal, the first clock signal, the second data signal, and the second clock signal. The first output unit 111 is further configured to embed the first clock signal into the first data signal to obtain the N first data packets. The second output unit 112 is further configured to embed the second clock signal into the second data signal to obtain the N second data packets. The delay control unit 114 is configured to control the start time of the N first data packets and the N second data packets by the first output unit 111 and the second output unit 112 to control the ith second data. The packet has a delay of the predetermined time Td with respect to the ith first data packet at the transmission time. It can be understood that the delay control unit 114 can control the predetermined time Td according to the value of x.

The data driving circuit 120 further includes a first amplifier 123, a second amplifier 124, a first data recovery circuit 125, a second data recovery circuit 126, a first clock recovery circuit 127, and a second clock recovery circuit 128. The first amplifier 123 receives the first data packet from the first receiving unit 121. The first data recovery circuit 125 receives the first data packet from the first amplifier 123 and performs data recovery on the first data packet to obtain a first data signal. The first clock recovery circuit 127 receives the first data packet from the first amplifier 123 and clock-recovers the first data packet to obtain a first clock signal. The second amplifier 124 receives the second data packet from the second receiving unit 122. The second data recovery circuit 126 is configured to receive the second data packet from the second amplifier 124 and perform data recovery on the second data packet to obtain a second data signal. The second clock recovery circuit 128 is configured to receive a second data packet from the second amplifier 124 and perform clock recovery on the second data packet to obtain a second clock signal.

Further, the data driving circuit 120 outputs a driving voltage to the display panel 130 based on the first data signal, the second data signal, the first clock signal, and the second clock signal obtained by the data recovery and clock recovery to drive the display panel 130. Screen display Show.

In the display device 100 of the present invention, since the data packet transmission times of the first transmission channel 141 and the second transmission channel 142 are inconsistent, that is, the second data packet has a delay relative to the first data packet, the first and second can be improved. The electromagnetic interference phenomenon caused by the synchronous transmission of the data packet is a serious problem, and the electromagnetic interference in the transmission process of the display device 100 and its embedded clock data is reduced.

In addition, in an embodiment of the present embodiment, when the clock signal bit of the ith first data packet is opposite to the clock signal bit of the ith second data packet, the phase is opposite to H0' The opposite phase of H1 and H1' can improve the phenomenon of electromagnetic interference caused by the simultaneous transmission of the i-th first data packet and the i-th second data packet having the same phase, and the electromagnetic interference of the display device 100 is small.

In addition, as shown in FIG. 2, in the embodiment, each data packet includes two clock signal bits and (M-2) data signal bits, and the two clock signal bits precede the (M-2). A data signal bit transmission, however, referring to FIG. 3, in a modified embodiment of the present embodiment, each data packet may also include three clock signal bits (H0, H1, and H2; H0', H1). 'and H2') and (M-3) data signal bits (D0, ..., D(M-4); D0', ..., D(M-4)'), preferably, each data The three clock signal bits of the packet are also transmitted before the (M-3) data signal bits.

Moreover, in an embodiment of the modified embodiment, the clock signal bit of the ith first data packet is opposite to the clock signal bit of the ith second data packet, such as H0 and H0. 'The opposite phase, H1 and H1' are opposite in phase, H2 is opposite to H2', and the data signal bit of the i-th first packet is in the same phase as the data signal bit of the i-th second packet, such as D0. ,..., D(M-4) and D0' respectively , ..., D(M-4)' have the same phase.

4 and FIG. 5, FIG. 4 is a block diagram of a display device 200 according to a second embodiment of the present invention, and FIG. 4 is a timing chart of embedded clock data transmitted on the embedded clock data transmission interface 240 shown in FIG. The display device 200 is substantially the same as the display device 100 of the first embodiment, that is, the above description of the display device 100 of the first embodiment can be basically applied to the display device 200 of the second embodiment. The main difference between the two is that in the display device 100 of the second embodiment, the ith first data packet is opposite to the ith second data packet, and the ith first data is opposite to the phase A packet and the i-th second packet, the circuit structure of the data driving circuit 220 is also different from that of the first embodiment.

Specifically, the data driving circuit 220 includes a first receiving unit 221, a second receiving unit 222, a first amplifier 223, a second amplifier 224, a first data recovery circuit 225, a second data recovery circuit 226, and a first clock recovery circuit. 227, a second clock recovery circuit 228 and an inverter 229, the first amplifier 223 is configured to receive the first data packet from the first receiving unit 221, and the first data recovery circuit 225 is configured to receive from the first amplifier 223. The first data packet is recovered from the first data packet to obtain a first data signal, and the first clock recovery circuit 227 is configured to receive the first data packet from the first amplifier 223 and clock the first data packet. Recovering to obtain a first clock signal, the second amplifier 224 is configured to receive the second data packet from the second receiving unit 222, and the inverter 229 is connected between the second amplifier 224 and the second data recovery circuit 226 And performing a reverse processing on the second data packet outputted by the second amplifier 224, where the second data recovery circuit 226 is configured to perform data recovery according to the inverted second data packet output by the inverter 229. To obtain a second information signal, the second clock recovery circuit according to the second data packet 228 for the inverted output of the inverter 229 is connected to a second The packet is clocked to obtain a second clock signal.

M bits H0, H1, D0, D1, ..., D(M-3) of the i-th first data packet and M bits of the i-th second data packet, respectively, such as H0' H1', D0', D1', ..., D(M-3)' are opposite in phase. In other words, each bit of the i-th first data packet is opposite in phase to a corresponding one bit of the i-th second data packet. For example, H0 and H0' are opposite in phase, and D0 and D0' are opposite in phase.

In the display device 200 of the second embodiment, since the phase of the ith first data packet and the ith second data packet are opposite, the ith first data packet and the ith second data having the same phase can be avoided. The electromagnetic interference caused by the simultaneous transmission of the data packet, the electromagnetic interference of the display device 200 is small.

Please refer to FIG. 6. FIG. 6 is a block diagram of a display device 300 according to a third embodiment of the present invention. The display device is substantially the same as the display device 100 of the first embodiment, that is, the above description of the display device 100 of the first embodiment can be basically applied to the display device 300 of the third embodiment, however, The main difference between the two is that in the display device 300 of the third embodiment, the ith first data packet is opposite to the ith second data packet, and the ith first is opposite to the phase. The data packet and the i-th second data packet, the circuit structure of the data driving circuit 320 are also different from the circuit structure of the first embodiment.

Specifically, the data driving circuit 320 includes a first receiving unit 321, a second receiving unit 322, a first amplifier 323, a second amplifier 324, a first data recovery circuit 325, a second data recovery circuit 326, and a first clock recovery circuit. 327. The second clock recovery circuit 328 is configured to receive the first data packet from the first receiving unit 321 , where the first data recovery circuit 325 is configured to receive the first data packet from the first amplifier 323. And recovering the data of the first data packet to obtain the first data signal The first clock recovery circuit 327 is configured to receive the first data packet from the first amplifier 323 and perform clock recovery on the first data packet to obtain a first clock signal, and the second amplifier 324 is configured to receive the second data packet. The unit 322 receives the second data packet, and the second data recovery circuit 326 further includes an inverter 326a and a data recovery unit 326b, and the inverter 326a is configured to invert the second data packet output by the second amplifier 324. Processing, the data recovery unit 326b performs data recovery according to the inverted second data packet output by the inverter 326a to obtain a second data signal, and the second clock recovery circuit 328 is configured to receive the second data from the second amplifier 324. The second packet is clocked back to the second packet to obtain a second clock signal.

In the display device 300 of the third embodiment, since the phase of the ith first data packet and the ith second data packet are opposite, the ith first data packet and the ith second data having the same phase can be avoided. The electromagnetic interference caused by the simultaneous transmission of the data packet, the electromagnetic interference of the display device 300 is small.

Please refer to FIG. 7 and FIG. 8. FIG. 7 is a block diagram of a display device 400 according to a fourth embodiment of the present invention. FIG. 8 is a timing diagram of embedded clock data transmitted on the embedded clock data transmission interface 440 of FIG. The display device 400 is substantially the same as the display device 100 of the first embodiment, that is, the above description of the display device 100 of the first embodiment can be basically applied to the display device 400 of the fourth embodiment, however The main difference between the two is that the embedded clock data transmission interface 440 further includes a third transmission channel 443 and a fourth transmission channel 444. Correspondingly, the timing control circuit 410 further includes a third output unit 415 and a fourth output unit 416. The data driving circuit 420 further includes a third receiving unit 451, a fourth receiving unit 452, a third amplifier 453, a fourth amplifier 454, a third clock recovery circuit 455, a fourth clock recovery circuit 456, and a third data recovery circuit 457. And a fourth data recovery circuit 458.

Specifically, the first transmission channel 441 and the second transmission channel 442 may be substantially the same as the first transmission channel 141 and the second transmission channel 142 of the first embodiment, that is, the first transmission in the first embodiment described above. The description of the channel 141 and the second transmission channel 142 can be basically used for the first transmission channel 441 and the second transmission channel 442. Therefore, the structures and features of the two are not described herein. The third transmission channel 443 is electrically connected between the third output unit 415 and the third receiving unit 451. The fourth transmission channel 444 is electrically connected between the fourth output unit 416 and the fourth receiving unit 452.

The embedded clock data transmitted by the timing control circuit 410 to the data driving circuit 420 further includes N third data packets and N fourth data packets. The N third data packets sequentially output by the third output unit 415 pass through the third transmission channel 443 to the third receiving unit 451, and the N fourth data packets sequentially output by the fourth output unit 416 pass the first Four transmission channels 444 to the fourth receiving unit 452. Specifically, in the embedded clock data transmission interface 440, the ith fourth data packet has a delay of a predetermined time Td with respect to the ith third data packet, wherein N is a natural number greater than 1. , i is a natural number greater than or equal to 1 and less than or equal to N. Referring to FIG. 7, FIG. 7 is an ith first data packet, an ith second data packet, an ith third data packet, and an ith fourth packet transmitted on the embedded clock data transmission interface 440. Timing diagram of the data package.

It can be seen that the four data packets have substantially the same length, and each data packet can be a binary code including M bits, such as H0, H1, D0, D1, ..., D. (M-3); H0', H1', D0', D1', ..., D(M-3)';H0'',H1'',D0'',D1'', ..., D ( M-3) ''; and H0''', H1''', D0''', D1''', ..., D(M-3)'''. The values of M may be different for different transmission interfaces. Preferably, the value of M may be in the range of 12-27, as in one embodiment, M is 14, and in another embodiment, M is 27. Further, it is assumed that the basic transmission time of each bit is T0. Preferably, the delay time Td is greater than or equal to T0/2 ^x and less than T0, where x is a natural number, and for different types of transmission interfaces, the value of x may be Differently, preferably, X is in the range of 3 to 5, such as when x = 4, Td is greater than or equal to T0/2 ⁴ and less than T0, and when x = 5, Td is greater than or equal to T0/2 ⁵ and less than T0.

Specifically, for different transmission interfaces, the basic transmission time of each bit may be different, but it can be understood that the basic transmission time of each bit is related to the transmission rate of the transmission interface, and the embedded clock data transmission interface is set. The transmission rate is V bits per second, and the basic transmission time of each bit is T0=1/V seconds. For example, in the present embodiment, the transmission rate V ranges from 200 megabits per picosecond (200 Mb/ps) to 4 gigabits per picosecond (4 Gb/ps), so that the basic transmission time T0 of each bit The range is from 5 nanoseconds (ns) to 250 picoseconds (ps).

In particular, in the transmission interface provided by this embodiment, the first two bits of each data packet (such as H0'', H1'', and H0''', H1''') belong to the clock signal, and the remaining bits ( D0'', D1'', ..., D(M-3)'' and D0''', D1''', ..., D(M-3)''') belong to the data signal. In one embodiment, M can be 9. Of course, in the modified implementation manner, in another embedded data transmission interface, the clock signal of each data packet may not be located in the first two bits, but embedded in the data signal and located in other bits.

Further, preferably, in an embodiment of the embodiment, the clock signal bit of the ith third data packet is opposite to the clock signal bit of the ith fourth data packet, such as H0' 'In contrast to the H0''' phase, the H1'' is opposite to the H1''' phase, the data signal bit of the i-th third packet and the i-th fourth asset The information signal bits of the packet have the same phase, such as D0'', D1'', ..., D(M-3)'' and D0''', D1''', ..., D(M-3 respectively) ) '''The same phase. Of course, in another embodiment of the present embodiment, the clock signal bit of the ith third data packet and the clock signal bit phase of the ith fourth data packet may be the same, such as H0'' and H0. '''The same phase, H1'' is the same as H1''', the data signal bit of the i-th third data packet is in the same phase as the data signal bit of the i-th fourth data packet.

Further, in the embodiment, the third transmission channel 443 and the first transmission channel 441 simultaneously transmit data packets, and the fourth transmission channel 444 and the second transmission channel 442 simultaneously transmit data packets. Specifically, the ith first data packet and the ith third data packet are completely simultaneously and synchronously transmitted, and the ith second data packet and the ith fourth data packet are completely simultaneously and synchronously transmitted. In addition, the third transmission channel 443 and the fourth transmission channel 444 respectively transmit the third data packet and the fourth data packet in a differential transmission manner.

Further, the delay control unit 414 of the timing control circuit 410 is also electrically connected to the third output unit 415 and the fourth output unit 416 for controlling the third output unit 415 and the fourth output unit 416 to output the N a start time of the third data packet and the N fourth data packets to control a delay of the ith fourth data packet with respect to the ith third data packet for the predetermined time Td in the transmission time, and The i third data packets are completely simultaneously and synchronously transmitted with respect to the ith first data packet, and the ith fourth data packet is completely simultaneously with respect to the ith second data packet in transmission time. And synchronized.

Further, the data processing circuit 413 further receives the image data and processes the image data to obtain a third data signal, a third clock signal, a fourth data signal, and a fourth clock signal. The third output unit 415 is further configured to embed the third clock signal Enter the third data signal to obtain the N third data packets. The fourth output unit 416 is further configured to embed the fourth clock signal into the fourth data signal to obtain the N fourth data packets.

The third amplifier 453 receives the third data packet from the third receiving unit 451. The third data recovery circuit 455 receives the third data packet from the third amplifier 453 and performs data recovery on the third data packet to obtain a third data signal. The third clock recovery circuit 457 receives the third data packet from the third amplifier 453 and clocks the third data packet to obtain a third clock signal. The fourth amplifier 454 receives the fourth data packet from the fourth receiving unit 452. The fourth data recovery circuit 456 is configured to receive a fourth data packet from the fourth amplifier 454 and perform data recovery on the fourth data packet to obtain a fourth data signal. The fourth clock recovery circuit 458 is configured to receive a fourth data packet from the fourth amplifier 454 and perform clock recovery on the fourth data packet to obtain a fourth clock signal.

The data driving circuit 420 further outputs a driving voltage to the display panel 430 based on the third data signal, the fourth data signal, the third clock signal, and the fourth clock signal obtained by the data recovery and clock recovery, to drive the display panel 430 to perform a screen. display.

In the fourth embodiment, the embedded data transmission interface 440 has more transmission channels, so that the data transmission speed of the display device 400 is faster.

9 and 10, FIG. 9 is a block diagram of a display device 500 according to a fifth embodiment of the present invention, and FIG. 10 is a timing chart of embedded clock data transmitted on the embedded clock data transmission interface 540 shown in FIG. The display device 500 is substantially the same as the display device 400 of the fourth embodiment, that is, the above description of the display device 400 of the fourth embodiment can be basically applied to the display device 500 of the fifth embodiment, however The main difference between the two is that the display device 500 of the fourth embodiment is The ith first data packet is opposite to the phase of the ith second data packet, the ith third data packet is opposite in phase to the ith fourth data packet, and the ith is opposite to the phase 191 The first data packet and the ith second data packet and the ith third data packet and the ith fourth data packet, the circuit structure of the data driving circuit 520 is also different from the circuit structure of the fourth embodiment.

Specifically, the data driving circuit 520 further includes a first inverter 529 and a second inverter 559, wherein the first inverter 529 is connected between the second amplifier 524 and the second data recovery circuit 526. The second data packet for outputting the second amplifier 524 is inverted, and the second inverter 559 is connected between the fourth amplifier 554 and the fourth data recovery circuit 556 and used for the fourth amplifier The fourth packet outputted by 554 is inverted.

In the display device 500 of the second embodiment, the phase of the ith first data packet is opposite to the ith second data packet, and the ith third data packet and the ith fourth data packet are In the opposite phase, electromagnetic interference caused by simultaneous transmission of packets of the same phase can be avoided, and the electromagnetic interference of the display device 500 is small.

11 and FIG. 12, FIG. 11 is a block diagram of a display device 600 according to a sixth embodiment of the present invention, and FIG. 12 is a timing chart of embedded clock data transmitted on the embedded clock data transmission interface 640 of FIG. The display device 600 is substantially the same as the display device 400 of the fourth embodiment, that is, the above description of the display device 400 of the fourth embodiment can be basically applied to the display device 600 of the sixth embodiment, however The main difference between the two is that in the display device 600 of the sixth embodiment, the ith first data packet is opposite to the ith third data packet, and the ith second data packet and the ith first data packet The four packets are opposite in phase, and the i-th first data packet and the i-th second data packet and the i-th The circuit structure of the data driving circuit 620 and the circuit structure of the first embodiment are also different from the third data packet and the ith fourth data packet.

Specifically, the data driving circuit 620 further includes a first inverter 629 and a second inverter 659. The first inverter 629 is connected between the third amplifier 653 and the third data recovery circuit 655. The third data packet outputted by the third amplifier 653 is inverted, and the second inverter 659 is connected between the fourth amplifier 654 and the fourth data recovery circuit 656 and used for the fourth amplifier 654. The output fourth packet is inverted.

In the display device 600 of the second embodiment, the ith first data packet and the ith third data packet are simultaneously transmitted, and the ith second data packet and the ith are simultaneously transmitted. The fourth packet has the opposite phase, which can avoid electromagnetic interference caused by the simultaneous transmission of the same phase packets, and the electromagnetic interference of the display device 600 is small.

Please refer to FIG. 13, which is a flowchart of a method for transmitting and processing embedded clock data of the present invention. It can be understood that the transmission and processing method of the embedded clock data can be applied to the display devices of the above six embodiments. Since the above embodiment has introduced the transmission and processing methods of the embedded clock data of the display device in detail. That is to say, the method for transmitting and processing the embedded clock data by the display device of the above six embodiments can also be applied to the method for transmitting and processing the embedded clock data in the embodiment, and details are not described herein again. Introduce the main steps.

Specifically, the method for transmitting and processing the embedded clock data includes the following steps:

Step S1, providing an embedded clock data, where the embedded clock data includes N The first data packet and the N second data packets, where N is a natural number greater than one.

Step S2, providing a first transmission channel and a second transmission channel, the first transmission channel being connected between the first output unit and the first receiving unit, wherein the second transmission channel is connected to the first output unit and the second receiving unit between.

In step S3, the first output unit sequentially outputs the N first data packets to the first receiving unit through the first transmission channel.

Step S4, the second output unit sequentially outputs the N second data packets to the second receiving unit by using the second transmission channel, wherein the ith second data packet is relative to the ith first data packet. There is a delay of a predetermined time in the transmission time, and i is a natural number greater than or equal to 1 and less than or equal to N.

Further, the ith first data packet and the ith second data packet each include M bits. For different transmission interfaces, the value of M may be different. Preferably, the value of M may be 12~27. Within the scope of, as in one embodiment, M is 14, and in another embodiment, M is 27. Further, it is assumed that the basic transmission time of each bit is T0. Preferably, the delay time Td is greater than or equal to T0/2 ^x and less than T0, where x is a natural number, and for different types of transmission interfaces, the value of x may be Differently, preferably, X is in the range of 3 to 5, such as when x = 4, Td is greater than or equal to T0/2 ⁴ and less than T0, and when x = 5, Td is greater than or equal to T0/2 ⁵ and less than T0.

Further, the Mth bit of the ith first data packet and the ith second data packet both include a clock signal bit and a data signal bit. In each data packet, the clock signal bit is transmitted before the data signal bit, and the number of the clock signal bits is two or three. And, preferably, the clock signal bit of the ith first data packet is opposite to the clock signal bit of the ith second data packet, and the ith first data is The data signal bit of the packet is in the same phase as the data signal bit of the i-th second data packet.

Further, the method may further include: performing data recovery and clock recovery on the first data packet to obtain the first data signal and the first clock signal.

In an embodiment, the ith first data packet and the ith second data packet have opposite phases, and the method further includes: performing inverse processing on the second data packet, and The second data packet is subjected to data recovery and clock recovery to obtain the first data signal and the first clock signal.

In summary, the present invention has indeed met the requirements of the invention patent, and has filed a patent application according to law. However, the above description is only a preferred embodiment of the present invention, and it is not possible to limit the scope of the patent application of the present invention. Equivalent modifications or variations made by persons skilled in the art in light of the spirit of the invention are intended to be included within the scope of the following claims.

100‧‧‧ display device

110‧‧‧Sequence Control Circuit

120‧‧‧Data Drive Circuit

130‧‧‧ display panel

140‧‧‧ embedded clock data transmission interface

141‧‧‧First transmission channel

142‧‧‧Second transmission channel

111‧‧‧First output unit

112‧‧‧Second output unit

113‧‧‧ Data Processing Circuit

114‧‧‧ Delay Control Unit

121‧‧‧First receiving unit

122‧‧‧second receiving unit

141a, 142a‧‧‧ transmission line

141b, 142b‧‧‧ negative transmission line

111a, 112a‧‧‧ positive output

111b, 112b, ‧‧‧negative output

121a, 122a‧‧‧ receiving end

121b, 122b‧‧‧ negative receiving end

123‧‧‧First amplifier

124‧‧‧second amplifier

125‧‧‧First data recovery circuit

126‧‧‧Second data recovery circuit

127‧‧‧First clock recovery circuit

128‧‧‧Second clock recovery circuit

Claims (17)

A display device includes a timing control circuit, a data driving circuit and a display panel, wherein the timing control circuit is configured to transmit embedded clock data to the data driving circuit, and the data driving circuit is configured to output a driving voltage to the display panel, and the timing control An embedded clock data transmission interface is included between the circuit and the data driving circuit, the timing control circuit includes a first output unit and a second output unit, the data driving circuit includes a first receiving unit and a second receiving unit, the embedded clock The data transmission interface includes a first transmission channel and a second transmission channel. The first transmission channel is connected between the first output unit and the first receiving unit, and the second transmission channel is connected to the second output unit and the second receiving unit. The embedded clock data includes N first data packets and N second data packets, and the first output unit sequentially outputs the N first data packets to the first receiving unit through the first transmission channel. The second output unit sequentially outputs the N second data packets to the second receiving unit through the second transmission channel, where In the embedded clock data transmission interface, the ith second data packet has a predetermined time delay with respect to the ith first data packet in a transmission time, where N is a natural number greater than 1, and i is greater than or equal to 1 And a natural number less than or equal to N. The display device according to claim 1, wherein the basic transmission time of each bit is T0, the delay time is greater than or equal to T0/2 ^x and less than T0, and x is in the range of 3 to 5. The display device of claim 2, wherein the basic transmission time T0 of each bit is in the range of 5 nanoseconds to 250 picoseconds. The display device of claim 1, wherein the data driving circuit further comprises a first amplifier, a second amplifier, a first data recovery circuit, a second data recovery circuit, a first clock recovery circuit, and a second clock recovery circuit, The first amplifier is configured to receive the first data packet from the first receiving unit, where the first data recovery circuit is configured to receive the first data packet from the first amplifier and Performing data recovery on the first data packet to obtain a first data signal, where the first clock recovery circuit is configured to receive the first data packet from the first amplifier and perform clock recovery on the first data packet to obtain a first clock signal. The second amplifier is configured to receive the second data packet from the second receiving unit, where the second data recovery circuit is configured to receive the second data packet from the second amplifier and perform data recovery on the second data packet to obtain And a second data recovery circuit, the second clock recovery circuit is configured to receive the second data packet from the second amplifier and perform clock recovery on the second data packet to obtain a second clock signal. The display device of claim 1 or 4, wherein the ith first data packet and the ith second data packet each comprise M bits, the M bits including clock signal bits and data a signal bit, the clock signal bit of the i-th first data packet is opposite to the clock signal bit of the i-th second data packet, and the data signal bit of the i-th first data packet and the first The data signal bits of the i second data packets have the same phase, and the value of the M is in the range of 12 to 27. The display device of claim 5, wherein in each data packet, the clock signal bit is transmitted before the data signal bit, and the number of the clock signal bits is two or three. The display device of claim 1, wherein the ith first data packet is opposite in phase to the ith second data packet. The display device of claim 7, wherein the data driving circuit further comprises a first amplifier, a second amplifier, a first data recovery circuit, a second data recovery circuit, a first clock recovery circuit, a second clock recovery circuit, and An inverter, the first amplifier is configured to receive the first data packet from the first receiving unit, where the first data recovery circuit is configured to receive a first data packet from the first amplifier and perform data on the first data packet Recovering to obtain the first data signal, the first clock recovery circuit is configured to receive the first data packet from the first amplifier and perform clock recovery on the first data packet to obtain a first clock signal, where the second amplifier is used for Receiving, by the second receiving unit, the second data packet, the inverter is connected between the second amplifier and the second data recovery circuit, and is configured to perform inverse processing on the second data packet output by the second amplifier, where Second data recovery The complex circuit is configured to perform data recovery according to the inverted second data packet outputted by the inverter to obtain a second data signal, and the second clock recovery circuit is configured to perform the second inverted signal according to the output of the inverter The data packet is connected to the second data packet for clock recovery to obtain a second clock signal. The display device of claim 7, wherein the data driving circuit further comprises a first amplifier, a second amplifier, a first data recovery circuit, a second data recovery circuit, a first clock recovery circuit, and a second clock recovery circuit, The first amplifier is configured to receive the first data packet from the first receiving unit, where the first data recovery circuit is configured to receive a first data packet from the first amplifier and perform data recovery on the first data packet to obtain a first data packet. a data signal, the first clock recovery circuit is configured to receive a first data packet from the first amplifier and perform clock recovery on the first data packet to obtain a first clock signal, and the second amplifier is configured to receive the second data signal The unit receives the second data packet, the second data recovery circuit further includes an inverter and a data recovery unit, and the inverter is configured to perform inverse processing on the second data packet output by the second amplifier, where the data recovery unit is based The inverted second data packet of the inverter output recovers data to obtain a second data signal, and the second clock recovery circuit is configured to receive a second data from the second amplifier The data packet is clocked back to the second data packet to obtain a second clock signal. The display device of claim 1, wherein the timing control circuit further comprises a data processing circuit and a delay control unit, wherein the data processing circuit receives the image data and processes the image data to obtain the first data signal, The first output unit is further configured to embed the first clock signal into the first data signal to obtain the first data packet, and the second output unit is further used to: the clock signal, the second data signal, and the second clock signal. The second clock signal is embedded in the second data signal to obtain the second data packet, and the delay control unit is configured to control the first output unit and the second output unit to output the first data packet and the second data packet. a start time to control a delay of the ith second data packet with respect to the ith first data packet for a predetermined time in transmission time. A method for transmitting and processing embedded clock data, comprising the following steps: Providing an embedded clock data, where the embedded clock data includes N first data packets and N second data packets, where N is a natural number greater than 1; providing a first transmission channel and a second transmission channel, the first The transmission channel is connected between the first output unit and the first receiving unit, and the second transmission channel is connected between the second output unit and the second receiving unit; the first output unit sequentially outputs the N first data packets to pass The first transmission channel to the first receiving unit; and the second output unit sequentially outputs the N second data packets through the second transmission channel to the second receiving unit, wherein the ith second data packet Relative to the delay of the ith first data packet having a predetermined time in the transmission time, i is a natural number greater than or equal to 1 and less than or equal to N. The method for transmitting and processing embedded clock data according to claim 11, wherein the basic transmission time of each bit is T0, the delay time is greater than or equal to T0/2 ^x and less than T0, and x is 3 to 5. Within the scope. The method for transmitting and processing embedded clock data according to claim 12, wherein the basic transmission time T0 of each bit is in a range of 5 nanoseconds to 250 picoseconds. The method for transmitting and processing embedded clock data according to claim 11, wherein the method further comprises: performing data recovery and clock recovery on the first data packet to obtain the first data signal and the first clock signal. The method for transmitting and processing embedded clock data according to claim 11, wherein the ith first data packet and the ith second data packet have opposite phases, the method further comprising: the second data The packet is subjected to inversion processing, and the data recovery and clock recovery of the second data packet after the inversion are performed to obtain the first data signal and the first clock signal. The method for transmitting and processing embedded clock data according to claim 11, wherein the ith first data packet and the ith second data packet each include M bits, and the M bits include a clock. a signal bit and a data signal bit, a clock signal bit of the i-th first packet and the i-th bit The clock signal bit of the second data packet is opposite in phase, and the data signal bit of the i-th first data packet is in the same phase as the data signal bit of the i-th second data packet, and the value of the M is in the range of 12-27. Inside. The method for transmitting and processing embedded clock data according to claim 16, wherein in each data packet, the clock signal bit is transmitted before the data signal bit, and the number of the clock signal bits is two or three.