KR20130011173A - Interface driving circuit and flat display device inculding the same - Google Patents

Interface driving circuit and flat display device inculding the same Download PDF

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Publication number
KR20130011173A
KR20130011173A KR1020110072140A KR20110072140A KR20130011173A KR 20130011173 A KR20130011173 A KR 20130011173A KR 1020110072140 A KR1020110072140 A KR 1020110072140A KR 20110072140 A KR20110072140 A KR 20110072140A KR 20130011173 A KR20130011173 A KR 20130011173A
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KR
South Korea
Prior art keywords
signal
input signal
inverting input
gate
inverted
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KR1020110072140A
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Korean (ko)
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이상용
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엘지디스플레이 주식회사
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Publication of KR20130011173A publication Critical patent/KR20130011173A/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G3/2096—Details of the interface to the display terminal specific for a flat panel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/14—Use of low voltage differential signaling [LVDS] for display data communication
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00195—Layout of the delay element using FET's

Abstract

The present invention discloses an interface driving circuit. In particular, the present invention relates to an interface driving circuit provided in an electronic information display device such as a liquid crystal display device for transmitting and receiving data with an external system.
According to a control of the common mode feedback circuit, the interface driving circuit according to the preferred embodiment of the present invention corresponds to a pair of transistors serving as a constant current source, a non-inverting input signal, and an inverting input signal. The first and second CMOS buffers for supplying a current corresponding to the data to be transmitted in the second direction, and the termination resistor in response to the non-inverted EQ signal and the inverted EQ signal delayed from the non-inverted input signal and the inverted input signal. And a pre-emphasis section for supplying additional current.
Accordingly, the present invention omits the pre-emphasis driver implemented in a plurality of CMOS by high-speed data transfer in the interface driving circuit, and further includes an auxiliary switching element for supplying additional current to each switching element of the main driver. By supplying a half bit delay signal, it is possible to provide an interface circuit and a flat panel display device including the same, which implement a pre-emphasis technique and improve ground bounce.

Description

INTERFACE DRIVING CIRCUIT AND FLAT DISPLAY DEVICE INCULDING THE SAME}

The present invention relates to an interface driving circuit, and more particularly, to an interface driving circuit provided in an electronic information display device such as a liquid crystal display device for transmitting and receiving data with an external system.

Electronic information flat display devices such as liquid crystal displays (LCDs) and organic light emitting display devices (OLEDs) are replacing conventional display devices due to their characteristics.

A conventional flat panel display device displays a desired image on a screen by adjusting a transmission amount of a light beam according to an image signal applied to a plurality of control switches arranged in a matrix form. To this end, the flat panel display device is connected to an external system, for example, an output terminal of a computer main body by a predetermined connector, and receives a video signal (RGB), a clock signal, and a synchronization signal output from the computer main body. Implement

1 is a block diagram schematically illustrating a conventional flat panel display structure and a connection form of an external system connected thereto.

As shown, a conventional flat panel display apparatus includes an external system 1 that provides various data for displaying an image, and a timing controller that receives data from the external system 1 through an interface 3 and arranges and converts the data. (5), a gate and data driver 7 for generating a scan signal and a video signal under the control of the timing controller 5, and a display panel 9 for displaying an image under the control of the gate and data driver 7; )

In the flat panel display having such a structure, a low voltage differential signal (LVDS) driving circuit is used as the interface 3 for data transmission and reception between the external system 1 and the timing controller 5.

The aforementioned LVDS digitizes and compresses signals such as video signals, clock signals, and synchronization signals output from the external system 1, lowers the voltage to 1 V or less, and is used as a low voltage differential signal through the transmitter {(tx) (3a)}. The low voltage differential signal transmitted to the display device and transmitted through the receiver {(RX)} (3b)} mounted on the flat panel display device is restored to its original state. Such LVDS has an advantage of suppressing the emission of electromagnetic waves and noise.

However, the LVDS interface may generate noise due to inter-symbol interference (ISI) of a channel. ISI is due to the low-pass characteristic that high frequency components are attenuated when data is transmitted over the data channel.

 In order to overcome this problem, a method of implementing equalization by applying a pre-emphasis technique or a de-emphasis technique in the transmitter 3a has been proposed.

The above-described pre-emphasis technique is a method of predicting the amount of high frequency components attenuated in a channel and amplifying and transmitting the high frequency components by the amount of the high frequency component, and de-emphasis. ) Is a method in which the high frequency component is made larger and transmitted by reducing the size of the low frequency component while leaving the high frequency component unchanged.

2 is an equivalent circuit diagram of an interface driving circuit to which a conventional pre-emphasis technique is applied, and FIGS. 3A and 3B illustrate signal waveforms input and output to the interface driving circuit of FIG. 2.

As shown in the drawing, the conventional pre-emphasis interface driving circuit 3a receives a non-inverting input signal DIN and an inverting input signal DIN_B and applies a voltage signal to the termination resistor Load. The receiving unit (not shown) compares the polarity and magnitude of the voltage applied to the termination resistor (Load) and restores the digital signal.

In the interface driving circuit having such a structure, as the initial non-inverting input signal DIN and the inverting input signal DIN_B are input to the main driver, the first current a flowing through the termination resistor Load is caused by the first current a. Supply the data signal.

Subsequently, a period in which the phases of the non-inverting input signal DIN and the inverting input signal DIN_B are converted, that is, the inverting input signal DIN and the inverting input signal DIN_B are low level at a high level. non-inverted delay signal DIN_d and inverted delay signal DINB_d delayed by half a bit from the input signal in the period of transition from -level or low level to high level It is input to a pre-emphasis driver (Pre Driver), and accordingly implements a high speed operation by temporarily supplying a second current b through the transistors PP1 and PN1.

However, in the above-described pre-emphasis driver (pre driver), the transistors PP1 and PN1 serving as constant current sources supplying additional current repeat on / off operation at high speed. The current flows momentarily through the transistor, causing ground bounce on the output signal (G1, G2).

This ground bounce is a major cause of malfunction of the interface driving circuit.

The present invention has been made to solve the above-described problem, the present invention is provided in the flat panel display device connected to the external system noise due to the ground bounce of the interface driving circuit for transmitting and receiving data for displaying an image An object of the present invention is to provide an interface driving circuit having improved noise generation and a flat panel display device including the same.

In addition, another object of the present invention is to provide an interface driving circuit that implements high-speed data transmission by applying a pre-emphasis technique while simplifying the structure of the interface driving circuit, and a flat panel display device including the same.

In order to achieve the above object, the interface driving circuit according to a preferred embodiment of the present invention, the common mode feedback circuit; A pair of transistors serving as a constant current source under the control of the common mode feedback circuit; First and second CMOS buffer units configured to supply current corresponding to data to be transmitted in the first and second directions to the termination resistors in response to the non-inverting input signal and the inverting input signal; And a pre-emphasis unit connected to the pair of transistors and supplying additional current to the termination resistor in response to the non-inverting EQ signal and the inverting EQ signal delayed from the non-inverting input signal and the inverting input signal.

The pair of transistors may include: a first PMOS transistor having a gate connected to the common mode feedback circuit, a power supply voltage applied to a source, and a drain connected to the first CMOS buffer unit; And a first NMOS transistor having a gate connected to the common mode feedback circuit, a drain connected to the first CMOS buffer, and a source grounded.

The first CMOS buffer unit may include: a second PMOS transistor to which a non-inverting input signal is applied to a gate, a source is connected to the first PMOS transistor, and a drain is connected to the first node; And a second NMOS transistor to which a non-inverting input signal is applied to a gate, a drain is connected to the first node, and a source is connected to the first NMOS transistor.

The second CMOS buffer unit may include: a third PMOS transistor to which the inverted input signal is applied to a gate, a source is connected to the first PMOS transistor, and a drain is connected to a second node; And a third NMOS transistor, to which a inverted input signal is applied to a gate, a drain is connected to the second node, and a source is connected to the first NMOS transistor.

The pre-emphasis unit may include: a fourth NMOS transistor to which the non-inverting EQ signal is applied to a gate, a drain is connected to a first node, and a source is connected to the first NMOS transistor; And a fifth NMOS transistor having a gate applied with the inverted EQ signal, a drain connected to a second node, and a source connected to the first NMOS transistor.

The pre-emphasis unit may include: a fifth PMOS transistor having a non-inverting EQ signal applied to a gate, a drain connected to a first node, and a source connected to the first PMOS transistor; And a sixth NMOS transistor having a gate applied with the inverted EQ signal, a drain connected to a second node, and a source connected to the first PMOS transistor.

The non-inverting EQ signal and the inverting EQ signal may be signals delayed by at least half a bit from the non-inverting input signal and the inverting input signal.

In order to achieve the above object, a flat panel display device including an interface driving circuit according to a preferred embodiment of the present invention, a display panel for implementing an image; A driver controlling the display panel; A timing controller generating a control signal of the driver; And an interface driving circuit configured to transmit and receive data for generating the control signal from an external system to the timing controller, wherein the interface driving circuit comprises: a pair of transistors serving as a constant current source; First and second CMOS buffer units configured to apply a current corresponding to the data to a termination resistor in response to the non-inverting input signal and the inverting input signal; And a pre-emphasis unit connected to the pair of transistors and providing an additional current to the termination resistor in response to the non-inverting EQ signal and the inverting EQ signal delayed from the non-inverting input signal and the inverting input signal.

The pre-emphasis unit may include a pair of NMOS transistors in which the non-inverting EQ signal is applied to a gate, a drain is connected to the first and second CMOS buffer units, and a source is connected to a constant current source. .

The pre-emphasis unit is connected to at least one of a high voltage terminal and a low voltage terminal of the constant current source.

The non-inverting EQ signal and the inverting EQ signal may be signals delayed by at least half a bit from the non-inverting input signal and the inverting input signal.

According to a preferred embodiment of the present invention, a pair of auxiliary transistors for supplying an additional current to each transistor of the main driver is omitted, omitting the pre-emphasis driver implemented by a plurality of devices by high-speed data transfer in the interface driving circuit. By providing a half-bit delay signal than the input signal, it is possible to provide an interface circuit having a pre-emphasis technique and an improved ground bounce and a flat panel display device including the same.

1 is a block diagram schematically illustrating a conventional flat panel display structure and a connection form of an external system connected thereto.
2 is an equivalent circuit diagram of an interface driving circuit to which a conventional pre-emphasis technique is applied.
3A and 3B illustrate signal waveforms input and output to the interface driving circuit of FIG. 2.
4 is a diagram illustrating an overall structure of a flat panel display device including an interface circuit according to an exemplary embodiment of the present invention.
5 is an equivalent circuit diagram of a transmitter of an interface driving circuit according to a first embodiment of the present invention.
6 is a diagram illustrating a signal waveform input to the interface driving circuit of FIG. 5.
FIG. 7 is a diagram illustrating an EYE diagram of an interface driving circuit to which a pre-emphasis technique is applied according to an exemplary embodiment of the present invention.
8 is an equivalent circuit diagram of a transmitter of an interface driving circuit according to a second embodiment of the present invention.
FIG. 9 is a diagram measuring noise caused by a ground bounce of a power supply voltage provided in an interface driving circuit according to the related art and the exemplary embodiment of the present invention.

Hereinafter, an interface circuit and a flat panel display device including the same according to an exemplary embodiment of the present invention will be described with reference to the drawings.

4 is a diagram illustrating an overall structure of a flat panel display device including an interface circuit according to an exemplary embodiment of the present invention.

As shown, the flat panel display device of the present invention receives various signals from the external system 110, and according to the control of the timing controller 150 and the timing controller 150 to align and convert the control signal and the image signal The gate driver 160 generates the scan signal, the data driver 170 provides the converted image signal to the display panel, and the display panel 190 implements the image.

First, although not illustrated, the external system 110 includes a plurality of video chips, a video controller, a CPU, and the like, and an image signal RGB for an image to be displayed, and a data enable signal for controlling the flat panel display device. DE), a horizontal synchronization signal Hsync, and a vertical synchronization signal Vsync.

The interface 130 is a low voltage differential signal (LVDS) driving circuit including a transmitter 130a and a receiver 130b. The interface 130 transmits an image signal and a control signal generated by the external system 110 to the receiver 130b through the transmitter 130a. If the interface 130 transmits / receives 7 bits of serialized data for one cycle of the system clock, 28 bits of both 8-bit video signals and 4-bit control signals of RGB are transmitted. Will be provided.

The interface 130 applies a pre-emphasis technique for high-speed transmission, and a non-inverted EQ signal delayed by a bit (BIT) than the non-inverted input signal DIN and the inverted input signal DIN_B, which are input signals for driving. Pre-emphasis is implemented by further inputting the EQ) and the inverted EQ signal EQ_B. In this case, by sharing a constant current source of the main driver rather than having a separate constant current source for driving the pre-emphasis, the voltage swing according to the pre-emphasis driving is excluded, so that the ground bounce can be removed. To this end, a separate device for pre-emphasis driving is further provided, and a more specific structure and operation of the interface driving circuit will be described with reference to an equivalent circuit diagram of the interface driving circuit described later.

The timing controller 150 generates a gate control signal and a data control signal for controlling the gate driver 160 and the data driver 170, which will be described later, and inputs them to the drivers 160 and 170.

First, the timing controller 150 generates a gate output signal GOE, a gate start pulse GSP, and a gate shift clock GSC, which are control signals of the gate driver 160, and outputs the generated gate output signal to the gate driver 160.

In addition, the timing controller 150 generates a source output signal SOE, a source start pulse SSP, a source shift clock SSC, and a polarity control signal POL, which are control signals of the data driver 170, and generate the generated signals. By using the signals, the image signal RGB is aligned and converted into an analog image signal RGB ′ through an internal logic and output to the display panel 190.

The gate driver 160 controls on / off of the switching element T arranged on the display panel 190 in response to control signals input from the timing controller 150. The output terminal of the gate driver 160 is connected to the gate line GL of the display panel 190. The gate driver 160 outputs the gate driving signal and sequentially turns on the switching element T by one horizontal line. The image signals output from the data driver 170 on the panel 190 to the display panel 190 are applied to the pixels connected to the respective switching elements TFTs.

The data driver 170 aligns the digital image signal RGB inputted corresponding to the control signals input from the timing controller 150, selects reference voltages gamma, and accordingly analog image signal ( RGB '). The generated image signal RGB ′ is latched by one horizontal line and input to the display panel 190 through all data lines DL.

The display panel 190 crosses a plurality of gate lines GL and a plurality of data lines DL in a matrix form on a transparent substrate, and defines a plurality of pixels at intersections thereof. The gate line GL is connected to the gate driver 160, the data line DL is connected to the data driver 170, and each pixel is provided with a switching element TFT. Therefore, the switching element TFT is turned on in correspondence with the signal input to each wiring, and an image signal is applied to the pixel to realize the image.

According to the above-described structure, the flat panel display device according to the embodiment of the present invention receives the control signal and the image signal from the external system 110 through the interface 130, and aligns and converts the gate driver 160 according to the signal. ), The scan signal GL is generated, the switching element on the display panel 190 is turned on / off, and an image signal is output to the pixel to display the screen.

Hereinafter, an interface driving circuit and a flat panel display device including the same according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings.

5 is an equivalent circuit diagram of a transmitter of an interface driving circuit according to a first embodiment of the present invention.

As shown, the transmission unit 130a of the interface driving circuit of the present invention includes a common-mode feedback circuit (CMFB) 102 for providing a reference signal Vref and a common signal Vcm, It consists of the main driver which consists of PMOS and NMOS which are some transistors.

Specifically, the interface driving circuit 130a of the present invention is a constant current source, the gate is connected to the common mode feedback circuit 102, the source is connected to the power supply voltage (VDD) stage, the drain is the first and second CMOS The first PMOS transistor MP1 connected to the buffer units 132 and 134, the gate is connected to the common mode feedback circuit 102, the source is grounded (GND), and the drain is the first and second CMOS buffer units. And a first NMOS transistor MN1 connected to the first and second 132 and 134.

In addition, the first CMOS buffer unit 132 has a gate connected to a non-inverting input signal DIN terminal (not shown), a source connected to a first PMOS transistor MP1, and a drain connected to a first node N1. A second PMOS transistor MP2 connected to the gate, a gate connected to a non-inverting input signal DIN terminal (not shown), a drain connected to a first node N1, and a source connected to the first NMOS transistor MN1. ) And a second NMOS transistor MN2.

The second CMOS buffer unit 134 has a gate connected to an inverted input signal DINB terminal (not shown), a source connected to a first PMOS transistor MP1, and a drain connected to a second node N2. The third PMOS transistor MP3, the gate is connected to the inverting input signal DINB terminal (not shown), the drain is connected to the second node N2, and the source is connected to the first NMOS transistor MN1. The third NMOS transistor MN3 is formed.

The pre-emphasis unit 136 has a gate connected to the non-inverting EQ signal EQ terminal (not shown), a drain connected to the first node N1, and a source connected to the first NMOS transistor MN1. A fourth NMOS transistor MN4 connected to the gate, a gate is connected to the inverted EQ signal EQB terminal (not shown), a drain is connected to the second node N2, and a source is connected to the first NMOS transistor MN1. The fifth NMOS transistor MN5 is connected.

In addition, the first node N1 and the second node N2 are respectively connected to both ends of the termination resistor Load.

Hereinafter, the operation of the interface driving circuit of the present invention having the above-described device connection structure will be described.

The common mode feedback circuit 102 is a common signal of a voltage applied to the first node N1 and the second node N2 by the two resistor dividers R1 and R2 of the main driver and applied to the termination circuit. Allow the bias voltage to remain constant. The common mode feedback circuit 102 compares the common signal Vcom and the reference signal Vref to determine the control timing of the pair of first PMOS transistor MP1 and the first NMOS transistor MN1. Accordingly, the first PMOS transistor MP1 and the first NMOS transistor MN1 are electrically connected to the power supply voltage terminal and the ground voltage terminal, and operate as a constant current source under the control of the common mode feedback circuit 102.

The main driver includes a first CMOS buffer unit 132, a second CMOS buffer unit 134, and a pre-emphasis unit 136.

First, in response to the application of the non-inverting input signal DIN, the first CMOS buffer unit 132 receives the current from the constant current source through the first node N1 through the second CMOS buffer in the low-level. The second PMOS transistor MP2 for flowing in the direction of the third NMOS transistor of the unit 134 and the second NMOS for flowing the current flowing in the termination load in the high-level to ground GND. The transistor MN2 is included.

In response to the inversion input signal DINB being applied, the second CMOS buffer unit 134 receives current from the constant current source when the low-level is applied to the second NMOS transistor MN2 of the first CMOS buffer unit 132. The third PMOS transistor MP3 to flow to the (), and the third NMOS transistor to flow the current flowing from the first node (N1) in the termination load (Load) direction to the ground (GND) in the case of a high-level (MN3).

In addition, the interface driving circuit of the present invention is electrically connected to the first node N1 and the second node N2 and the first NMOS transistor MN1 serving as a constant current source, so that the first and second CMOS buffer units 132, A non-inverted EQ signal EQ and an inverted EQ signal EQ, which are delayed by a half bit from the input signal of 134, are input to supply additional current when the second and third NMOS transistors MN2 and MN3 are turned on. The pre-emphasis unit 136 is included.

According to this structure, the operation of the interface driving circuit will be described with reference to the signal waveform of FIG. 6. The first PMOS transistor MP1 and the first NMOS transistor NM1 are conducted from the common mode feedback circuit 102 so that the constant current is conducted. After driving to a circle, when the high-level non-inverting input signal DIN and the inverting input signal DINB are applied to the first and second CMOS buffer units 132 and 134, the third signal is generated. The PMOS transistor MP3 and the second NMOS transistor NM2 are conducted so that current flows in the first direction c in the termination load Load.

At the same time, when the high-level non-inverting EQ signal EQ and the inverting EQ signal EQ are input to the pre-emphasis unit 136, the fourth NMOS transistor MN4 is turned on to conduct the second. The additional current is supplied to the current flowing through the NMOS transistor MN2.

That is, a period in which the data to be transmitted is converted in phase between the non-inverting input signal DIN and the inverting input signal DIN_B, that is, the inverting input signal DIN and the inverting input signal DIN_B are at a low level. In the period of transition to high-level or transition from low-level to high-level, the non-inverted EQ signal EQ and the inverted EQ signal (half-bit delayed from the input signal) EQB) is input to the pre-emphasis unit 136, thereby providing a high-speed operation by temporarily supplying additional current through the fourth NMOS transistor MN4.

Thereafter, the non-inverting input signal DIN is maintained at a high level so that the main driver continues to operate. However, the non-inverting EQ signal EQ transitions to a low-level and the first NMOS transistor MN1, which is a constant current source connected to the fourth NMOS transistor MN4, maintains a conductive state, thereby providing a grounded current. Since there is no change in the flow of ground, the bounce phenomenon is improved. In addition, the current direction is changed by subsequent circuit driving in the same manner as described above.

FIG. 7 is a diagram illustrating an EYE diagram of an interface driving circuit to which the pre-emphasis technique is applied according to the conventional and exemplary embodiments of the present invention. In the conventional interface driving circuit, a signal is applied to an end voltage as a voltage swings. Noise n is generated in the waveform, but it can be seen that the signal waveform of the interface driving circuit of the present invention has a gentle shape without noise.

According to the driving described above, the transmitter of the interface driving circuit of the present invention implements a pre-emphasis through a pair of NMOS transistors without complicated device configuration, and does not have a separate power supply, thereby providing stable data transmission with improved ground bounce. Can be performed. Hereinafter, an interface driving circuit according to a second embodiment of the present invention will be described with reference to the drawings.

8 is an equivalent circuit diagram of a transmitter of an interface driving circuit according to a second embodiment of the present invention. In the second embodiment to be described later, a second pre-emphasis unit for removing ground bounce generated on the power supply voltage VDD side as well as the ground voltage GND is further provided.

As shown in the drawing, the transmitter 230a of the interface driving circuit of the present invention includes a common mode feedback circuit (CMFB) 220 that provides a reference signal Vref and a common signal Vcm, and a plurality of switching elements PMOS. And a main driver consisting of an NMOS.

The common mode feedback circuit 220 is applied to the first node N1 and the second node N2 by two resistor dividers R1 and R2 provided in the main driver, and applied to both ends of the termination circuit Load. The common signal or bias voltage of the voltage is kept constant. The common mode feedback circuit 220 determines the control timing of the pair of the first PMOS transistor MP1 and the first NMOS transistor MN1 by comparing the common signal Vcom with the reference signal Vref. Accordingly, the first PMOS transistor MP1 and the first NMOS transistor MN1 are electrically connected to the power supply voltage terminal and the ground voltage terminal, and operate as the constant current source under the control of the common mode feedback circuit 220.

The main driver includes a first CMOS buffer unit 232, a second CMOS buffer unit 234, a first pre-emphasis unit 236, and a second pre-emphasis unit 238.

First, in response to the application of the non-inverting input signal DIN, the first CMOS buffer unit 232 receives the current from the constant current source through the first node N1 through the second CMOS buffer in the low-level. The second PMOS transistor MP2 for flowing in the direction of the third NMOS transistor of the unit 234 and the second NMOS for flowing a current flowing in the terminal load in the high-level to ground GND. The transistor MN2 is included.

In response to the inversion input signal DINB being applied, the second CMOS buffer unit 234 receives a current from the constant current source when the low-level is applied to the second NMOS transistor MN2 of the first CMOS buffer unit 232. Third PMOS transistor (MP3) to flow to the third NMOS transistor for flowing a current flowing in the terminal load direction from the first node (N1) to the ground (GND) in the case of high-level (high-level) (MN3).

In addition, the interface driving circuit of the present invention further includes a first pre-emphasis unit 236 for providing an additional current at the ground terminal and a second pre-emphasis unit 238 for providing an additional current at the power supply voltage terminal. .

The first pre-emphasis unit 236 is electrically connected to the first NMOS transistor MN1, which is a constant current source, and has a non-inverted EQ signal EQ that is half a bit delayed from the input signals of the first and second CMOS buffer units 232 and 234. ) And an inverted EQ signal EQ to receive additional current when the second and third NMOS transistors MN2 and MN3 are turned on.

In addition, the second pre-emphasis unit 238 is electrically connected to the first PMOS transistor MP1 which is a constant current source to receive the non-inverting EQ signal EQ and the inverting EQ signal EQ, and thus the second and third PMOS transistors. When (MP2, MP3) is on (on) further supply additional current.

According to this structure, in the interface driving circuit of the second embodiment of the present invention, the first PMOS transistor MP1 and the first NMOS transistor NM1 are conducted from the CMFB 220, and are driven as a constant current source. When the high-level non-inverting input signal DIN and the inverting input signal DINB are applied to the first and second CMOS buffer units 232 and 234, the third PMOS transistor MP3 and the second NMOS transistor are applied. NM2 is turned on so that a current flows in the first load d in the terminal load.

At the same time, when the high-level non-inverting EQ signal EQ and the inverting EQ signal EQ are input to the first pre-emphasis unit 236, the fourth NMOS transistor MN4 is turned on. The additional current is supplied to the current flowing through the second NMOS transistor MN2. In addition, the fifth PMOS transistor MP5 of the second pre-emphasis unit 238 is also turned on so that an additional current is also supplied to a current flowing through the third NMOS transistor MN3, thereby enabling faster data transfer.

Thereafter, the non-inverting input signal DIN is maintained at a high level so that the main driver continues to operate. At this time, the non-inverting EQ signal EQ transitions to a low level and the first NMOS transistor MN1, which is a constant current source connected to the fourth NMOS transistor MN4, maintains a conductive state, thereby providing a grounded current. Since there is no change in the flow of ground, the bounce phenomenon is improved.

In the above-described second embodiment of the present invention, an example in which the pre-emphasis unit is provided at the power supply voltage terminal and the ground voltage terminal has been described. However, the pre-emphasis unit may be provided only at the power supply voltage terminal.

9 is a view measuring noise caused by a ground bounce of a power supply voltage provided in an interface driving circuit according to the prior art and the embodiment of the present invention. Although greatly fluctuated to V, according to the present invention, it does not deviate greatly from 1.8V. That is, the interface driving circuit of the present invention can be seen that the jitter (jitter) characteristics in the power supply is improved.

Many details are set forth in the foregoing description but should be construed as illustrative of preferred embodiments rather than to limit the scope of the invention. Therefore, the invention should not be construed as limited to the embodiments described, but should be determined by equivalents to the appended claims and the claims.

Vcm: Common Voltage Vref: Reference Voltage
102: common mode feedback circuit (CMFB) 130a: interface transmitter
132: first CMOS buffer unit 134: second CMOS buffer unit
136: pre-emphasis unit N1, N2: first and second nodes
Load: Terminating resistor DIN: Non-inverting input signal
DINB: Inverted input signal EQ: Non-inverted EQ signal
EQB: Inverted EQ signal MP1 to MP3: First to third PMOS transistors
MN1 to MN5: First to fifth NMOS transistors

Claims (10)

Common mode feedback circuit;
A pair of transistors serving as a constant current source under the control of the common mode feedback circuit;
First and second CMOS buffer units configured to supply current corresponding to data to be transmitted in the first and second directions to the termination resistors in response to the non-inverting input signal and the inverting input signal; And
A pre-emphasis unit connected to the pair of transistors and supplying an additional current to the termination resistor in response to the non-inverted EQ signal and the inverted EQ signal delayed from the non-inverted input signal and the inverted input signal.
Interface driving circuit comprising a. The method of claim 1,
The pair of transistors,
A first PMOS transistor having a gate connected to the common mode feedback circuit, a power supply voltage applied to a source, and a drain connected to the first CMOS buffer unit; And
A first NMOS transistor having a gate connected to the common mode feedback circuit, a drain connected to the first CMOS buffer, and a source grounded
Interface drive circuit comprising a. The method of claim 2,
The first CMOS buffer unit,
A second PMOS transistor to which a non-inverting input signal is applied to a gate, a source is connected to the first PMOS transistor, and a drain is connected to the first node; And
A second NMOS transistor having a non-inverting input signal applied to a gate, a drain connected to the first node, and a source connected to the first NMOS transistor
Interface drive circuit comprising a. The method of claim 2,
The second CMOS buffer unit,
A third PMOS transistor to which the inverting input signal is applied to a gate, a source is connected to the first PMOS transistor, and a drain is connected to a second node; And
A third NMOS transistor having the inverting input signal applied to a gate, a drain connected to the second node, and a source connected to the first NMOS transistor
Interface drive circuit comprising a. The method of claim 2,
The pre-emphasis unit,
A fourth NMOS transistor having a non-inverting EQ signal applied to a gate, a drain connected to a first node, and a source connected to the first NMOS transistor; And
A fifth NMOS transistor having a gate applied with the inverted EQ signal, a drain connected to a second node, and a source connected to the first NMOS transistor
Interface drive circuit comprising a. The method of claim 2,
The pre-emphasis unit,
A fourth PMOS transistor having a non-inverting EQ signal applied to a gate, a drain connected to a first node, and a source connected to the first PMOS transistor; And
A fifth NMOS transistor having a gate applied with the inverted EQ signal, a drain connected to a second node, and a source connected to the first PMOS transistor
Interface drive circuit comprising a. The method of claim 1,
The non-inverting EQ signal and the inverted EQ signal,
And a non-inverting input signal and a signal delayed by at least a half bit period from the inverting input signal. A display panel for implementing an image;
A driver controlling the display panel;
A timing controller generating a control signal of the driver; And
Interface drive circuit for transmitting and receiving data for generating the control signal to the timing controller from an external system,
The interface driving circuit,
A pair of transistors serving as a constant current source;
First and second CMOS buffer units configured to apply a current corresponding to the data to a termination resistor in response to the non-inverting input signal and the inverting input signal; And
A pre-emphasis unit connected to the pair of transistors and providing an additional current to the termination resistor in response to the non-inverting EQ signal and the inverted EQ signal delayed from the non-inverting input signal and the inverting input signal.
Flat display device comprising a. The method of claim 8,
The pre-emphasis unit,
A pair of NMOS transistors having a non-inverting EQ signal applied to a gate, a drain connected to the first and second CMOS buffers, and a source connected to a constant current source.
Flat display device comprising a. The method of claim 9,
The pre-emphasis unit,
And at least one of a high voltage terminal and a low voltage terminal of the constant current source.
KR1020110072140A 2011-07-20 2011-07-20 Interface driving circuit and flat display device inculding the same KR20130011173A (en)

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KR20140098892A (en) * 2013-01-31 2014-08-11 엘지디스플레이 주식회사 Liquid crystal display device and driving method thereof
US9552783B2 (en) 2014-02-26 2017-01-24 Samsung Display Co., Ltd. Source driver and display device having the same
US9842526B2 (en) 2013-10-08 2017-12-12 Samsung Display Co., Ltd. Flat panel display and driving method thereof
CN109327217A (en) * 2018-11-21 2019-02-12 灿芯半导体(上海)有限公司 A kind of LVDS transmitting line
WO2019034379A1 (en) * 2017-08-14 2019-02-21 Robert Bosch Gmbh Electrical circuit for a common-mode feedback system
CN109450435A (en) * 2018-11-21 2019-03-08 灿芯半导体(上海)有限公司 A kind of LVDS interface circuit
KR20190039726A (en) * 2016-08-30 2019-04-15 가부시키가이샤 한도오따이 에네루기 켄큐쇼 A receiver that receives a differential signal, an IC that includes a receiver, and a display device
CN114006605A (en) * 2021-12-31 2022-02-01 峰岹科技(深圳)股份有限公司 Single-edge delay circuit
US11336313B2 (en) 2019-09-24 2022-05-17 Silicon Works Co., Ltd Data transmission circuit

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140098892A (en) * 2013-01-31 2014-08-11 엘지디스플레이 주식회사 Liquid crystal display device and driving method thereof
US9842526B2 (en) 2013-10-08 2017-12-12 Samsung Display Co., Ltd. Flat panel display and driving method thereof
US9552783B2 (en) 2014-02-26 2017-01-24 Samsung Display Co., Ltd. Source driver and display device having the same
KR20190039726A (en) * 2016-08-30 2019-04-15 가부시키가이샤 한도오따이 에네루기 켄큐쇼 A receiver that receives a differential signal, an IC that includes a receiver, and a display device
WO2019034379A1 (en) * 2017-08-14 2019-02-21 Robert Bosch Gmbh Electrical circuit for a common-mode feedback system
CN109327217A (en) * 2018-11-21 2019-02-12 灿芯半导体(上海)有限公司 A kind of LVDS transmitting line
CN109450435A (en) * 2018-11-21 2019-03-08 灿芯半导体(上海)有限公司 A kind of LVDS interface circuit
CN109450435B (en) * 2018-11-21 2024-02-13 灿芯半导体(上海)股份有限公司 LVDS interface circuit
US11336313B2 (en) 2019-09-24 2022-05-17 Silicon Works Co., Ltd Data transmission circuit
CN114006605A (en) * 2021-12-31 2022-02-01 峰岹科技(深圳)股份有限公司 Single-edge delay circuit
CN114006605B (en) * 2021-12-31 2022-05-10 峰岹科技(深圳)股份有限公司 Single-edge delay circuit

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