KR101082110B1 - Timing controller, apparatus for data sending and receving using timing controller - Google Patents

Abstract

The apparatus for transmitting and receiving includes a master timing controller connected with a memory, and a plurality of slave timing controllers connected in series with the master timing controller. The master timing controller receives data from the memory and transmits the data to an adjacent slave timing controller of the plurality of slave timing controllers. Each slave timing controller receives data from an adjacent slave timing controller in a first direction among the plurality of slave timing controllers, and transmits data to an adjacent slave timing controller in a second direction different from the first direction of the plurality of slave timing controllers. send.

Timing Controller, Inter-Integrated Circuit (I2C), Memory, Master Mode, Slave Mode

Description

TIMING CONTROLLER, APPARATUS FOR DATA SENDING AND RECEVING USING TIMING CONTROLLER}

The present invention relates to a timing controller, and an apparatus for transmitting and receiving data using the same.

As a display device, such as a liquid crystal display (LCD), has become larger, a system for transmitting and receiving data using an inter-integrated circuit (I2C) interface includes a memory, for example, an eeprom and a timing controller ( More than two Timing Controllers are used, and as a result, it operates as a multi-drop bus structure having two or more identical device addresses. Here, the system for transmitting and receiving data using the interface is a device that operates in a multidrop bus structure based on the I2C bus protocol. In this case, the timing controller may include a source driver for supplying a data signal representing an image to a plurality of data lines formed in the display device.

In this multidrop bus structure, the timing controller initially operates in slave mode. If the I2C start signal is not transmitted from the outside for a predetermined time, the timing controller operates in master mode and communicates with the memory.

Therefore, in the multidrop bus structure, the timing controllers operate in the master mode at the same time, thereby performing I2C communication with the memory. If any one of the plurality of timing controllers successfully communicates with the memory, the timing controller transmits different response signals (ACKs) for whether the data is normally received from the memory to the memory, thereby preventing I2C communication from being performed normally. A problem occurs.

Accordingly, a technique for performing efficient I2C communication in a multi-drop bus structure in which two or more identical device addresses exist is required.

The technical problem to be achieved in the present invention is that a timing controller configured as a master timing controller in a multi-drop bus structure in which two or more identical device addresses exist, receives data by performing I2C communication with a memory first. A timing controller capable of controlling transmission of data to an adjacent slave timing controller, and an apparatus for transmitting and receiving data using the same.

According to an aspect of the present invention, a data transmission and reception apparatus includes a master timing controller connected to a memory, and a plurality of slave timing controllers connected in series to the master timing controller. Receives data from the memory and transmits the data to an adjacent slave timing controller of the plurality of slave timing controllers, wherein each slave timing controller is the data from an adjacent slave timing controller in a first direction of the plurality of slave timing controllers. And transmits the data to an adjacent slave timing controller in a second direction different from the first direction among the plurality of slave timing controllers.

According to another aspect of the present invention, a timing controller for transmitting and receiving data includes a first clock input terminal for receiving a clock signal, a first data input / output terminal for receiving the data in synchronization with the clock signal, and a timing controller connected to an adjacent timing controller. A second clock output terminal, a second data input / output terminal connected to the adjacent timing controller, and the clock signal output to the second clock output terminal, and in synchronization with the clock signal output to the second clock output terminal; And a chip main body configured to output the data to the second data input / output terminal.

As described above, according to the exemplary embodiment of the present invention, only a master timing controller of a plurality of timing controllers communicates one-to-one with a memory in a multi-drop bus structure. I2C communication can be performed more efficiently by avoiding collisions.

In addition, according to an embodiment of the present invention, since the timing controller is divided into a master timing controller and a slave timing controller according to a signal set from the outside for each timing controller without changing the I2C bus structure, a substrate for more efficiently performing I2C communication. Lifting cost can be reduced.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention, and like reference numerals designate like parts throughout the specification.

Throughout the specification, when a part is said to "include" a certain component, it means that it can further include other components, without excluding other components unless specifically stated otherwise.

1 is a diagram illustrating an example of I2C communication in a data transmission / reception apparatus for transmitting and receiving conventional data, and FIG. 2 is a diagram illustrating a signal for explaining an I2C interface in the transmission / reception system shown in FIG. 1.

Referring to FIG. 1, a conventional data transmission / reception apparatus includes a plurality of timing controllers (TCONs) 30-31 having the same device address as the memory 20. In this case, the memory may be, for example, an electrically erasable programmable read-only memory (eeprom). Each timing controller may include a source region for driving some data lines of a plurality of data lines (not shown) formed in the display unit (not shown).

The plurality of timing controllers 30 to 32 initially operate in the slave mode. If the I2C communication start signal is not transmitted from the outside for a predetermined time, the timing controllers 30 to 32 attempt to communicate with the memory 20 by themselves in the master mode. That is, referring to FIG. 2, each of the plurality of timing controllers 30-32 operating in the master mode performs an I2C communication start signal (START) 40 to the memory 20 to communicate with the memory 20. Then, it transmits the address (SLAVE ADDRESS) 41 of the memory 20 to communicate. Each of the plurality of timing controllers 30-32 transmits an R / W signal (READ / WRITE) 42 for selecting read / write, and then receives a response signal (ACK) 43 from the memory 20. When receiving, it transmits or receives data (DATA) 44 to communicate with. When transmission and reception of all data are completed, each of the plurality of timing controllers 30-32 transmits an end signal STOP 45 indicating the end to the memory 20.

After performing the I2C communication, the timing controller 30 among the plurality of timing controllers 30-32 succeeds in communication with the memory 20 and transmits a response signal 43 corresponding to success to the memory 20. Since the timing controller 31-32 also transmits a response signal 43 corresponding to the communication result, an abnormal I2C communication between the plurality of timing controllers 30-32 and the memory 20 occurs.

To solve this problem, a timing controller according to an embodiment of the present invention for normal I2C communication in a multidrop structure having the same address as one memory and a data transmitting / receiving apparatus transmitting and receiving data using the same will be described with reference to FIG. 3. It demonstrates concretely.

3 is a view schematically showing a data transmission and reception apparatus according to an embodiment of the present invention.

3, the data transmission and receiving apparatus according to an embodiment of the present invention includes a plurality of memory timing controller having the same address as _{(100) (200 1 -200 n} ).

Memory 100 performs the timing controller and the only I2C communication set as the master timing controllers of the plurality of the timing controller (200 ₁ -200 _n). In Figure 3 the timing controller (200 ₁₎ of the plurality of the timing controller (200 ₁ -200 _n) it is set as a master timing controller (200 ₁₎ is assumed to perform the I2C communication with the memory 100. The memory 100 includes a first power terminal VDDT, a second power terminal GNDT, a clock terminal SCLT, and a data terminal SDAT. That is, the first power supply terminal VDDT of the memory 100 is connected to the first power supply terminal VDDT of the master timing controller 200 ₁ , and the second power supply terminal GNDT is the master timing controller 200 ₁ . Is connected to the second power supply terminal (GNDT). The clock terminal SCLT of the memory 100 is connected to the first clock input terminal SCL0_IN of the master timing controller 200 ₁ , and the data terminal SDAT is connected to the first data input / output terminal SDA0_INOUT. . The memory 100 supplies power VDD required for driving the master timing controller 200 ₁ through the first power terminal VDDT and synchronizes with the master timing controller 200 ₁ through the clock terminal SCLT. Send the clock signal CLK to match. The memory 100 transmits and receives data SDA in synchronization with the master timing controller 200 ₁ and the clock signal CLK through the data terminal SDAT. Here, the data SDA includes a signal used for controlling the display device, for example, a timing signal and a control signal.

A plurality of the timing controller (200 ₁ -200 _n) includes a first clock input terminal (SCL0_IN), the second clock output terminal (SCL1_OUT), the first data input-output terminal (SDA0_INOUT), a second data input-output terminal (SDA1_INOUT), chip mode And a decision terminal CM ₀ -CM _m and a chip body CBD. Here, the terminals are omitted for supplying power (VDD, GND) between a plurality of the timing controller (200 ₁ -200 _n). A plurality of the timing controller (200 ₁ -200 _n) is set to such a set through the terminal chip mode determination (CM ₀ -CM _m) to the master timing controller chip according to a mode decision signal is applied from the outside, or a slave timing controller. Here, the chip mode determination signal may be a signal that is externally determined in hardware to set the timing controller as the master timing controller or as the slave timing controller. According to an embodiment of the present invention is set to only the timing controller (200 _1), the master timing controller (200 ₁₎ of the plurality of the timing controller (200 ₁ -200 _n), the rest of the timing controller (200 ₂ -200 _n) are slave timing controller It is set to (200 ₂ -200 _n).

The first clock input terminal SCL0_IN of the master timing controller 200 ₁ is connected to the clock terminal SCLT of the memory 100, and the first data input / output terminal SDA0_INOUT is connected to the data terminal of the memory 100. SDAT). A second clock output of the master timing controller (200 ₁₎ terminal (SCL1_OUT) is connected to the first clock input terminal (SCL0_IN) of the slave timing controller (200 _2), a second data input-output terminal (SDA1_INOUT) is a slave timing controller It is connected to the first data input / output terminal SDA0_INOUT of (200 ₂ ). A second clock output of the slave timing controller (200 ₂₎ terminal (SCL1_OUT) is connected to the first clock input terminal (SCL0_IN) of the slave timing controller (200 _3), a second data input-output terminal (SDA1_INOUT) is a slave timing controller It is connected to the first data input / output terminal SDA0_INOUT of (200 ₃ ). Equal to the remaining slave timing controller (200 ₃ -200 _n) is also the first clock input terminal, and (SCL0_IN) is connected to the second clock output terminal (SCL1_OUT) of the slave adjacent the timing controller, the first data input-output terminal (SDA0_INOUT) It is connected to the second data input / output terminal SDA1_INOUT of an adjacent slave timing controller. That is, (200 ₂ -200 _n), a plurality of slave timing controller is connected in series to the master timing controller (200 _1).

It will now be explained in details with respect to the data (SDA) in the transmission and reception of these master timing controller (200 ₁₎ and a plurality of slave timing controller (200 ₂ -200 _{n). (N} 200 ₂ -200) a plurality of slave timing controller according to an embodiment of the present invention after prior to receiving the data (SDA) in the I2C communication process operates in the slave mode, receive data (SDA) is a master mode, The controller transmits the data SDA to an adjacent slave timing controller by operating as. However, the master timing controller 200 ₁ initially operates in the slave mode. If the I2C communication start signal is not transmitted from the outside for a predetermined time, the master timing controller 200 ₁ operates in the master mode by itself and attempts to communicate with the memory 20.

In detail, the master timing controller 200 ₁ receives data SDA by performing I2C communication with the memory 100. In detail, the master timing controller 200 ₁ receives the clock signal CLK for synchronization from the clock terminal SCLT of the memory 100 through the first clock input terminal SCL0_IN. The master timing controller 200 ₁ receives the data SDA from the data terminal SDAT of the memory 100 through the first data input / output terminal SDA0_IN in synchronization with the clock signal CLK. When the reception of the data SDA is completed, the master timing controller 200 ₁ checks a check-sum of the data SDA to check whether the data is in error. When no error occurs, the master timing controller 200 ₁ transmits a transfer completion signal to the memory 100 through the first data input / output terminal SDA0_INOUT. When an error occurs, the master timing controller 200 ₁ receives data SDA again from the data terminal SDAT of the memory 100. In addition, the master timing controller 200 ₁ transmits the received data SDA to the adjacent slave timing controller 200 ₂ .

When the master timing controller 200 ₁ receives data through I2C communication from a device other than the memory 100 (not shown), the master timing controller 200 ₁ operates in slave mode during the I2C communication process. When communication with the network is terminated, the controller enters the master mode and transmits the received data SDA to the adjacent slave timing controller.

The slave timing controller 200 ₂ performs I ₂ C communication with the adjacent master timing controller 200 ₁ to receive the data SDA. In detail, the slave timing controller 200 ₂ receives the clock signal CLK for synchronizing from the second clock output terminal SCL1_OUT of the master timing controller 200 ₁ through the first clock input terminal SCL0_IN. . The slave timing controller 200 ₂ receives the data SDA from the second data input / output terminal SDA1_INOUT of the master timing controller 200 ₁ through the first data input / output terminal SDA0_INOUT in synchronization with the clock signal CLK. do. When the reception of the data SDA is completed, the slave timing controller 200 ₂ checks a check-sum of the data SDA to check whether the data is in error. If no error occurs, the slave timing controller 200 ₂ transmits a transmission completion signal to the master timing controller 200 ₁ through the first data input / output terminal SDA0_INOUT. When an error occurs, the slave timing controller 200 ₂ receives the data SDA again from the second data input / output terminal SDA1_INOUT of the master timing controller 200 ₁ . At this time, when the reception of the data SDA is completed without error, the slave timing controller 200 ₂ operates in the master mode to transmit the data SDA to the adjacent slave timing controller 200 ₃ .

The slave timing controller 200 ₃ receives data SDA from an adjacent slave timing controller 200 ₂ operating in the master mode. In detail, the timing controller 200 ₃ receives a clock signal CLK for synchronizing from the second clock output terminal SCL1_OUT of the slave timing controller 200 ₂ through the first clock input terminal SCL0_IN. The slave timing controller 200 ₃ receives the data SDA from the second data input / output terminal SDA1_INOUT of the slave timing controller 200 ₂ through the first data input / output terminal SDA0_INOUT in synchronization with the clock signal CLK. do. When the reception of the data SDA is completed, the slave timing controller 200 ₃ checks whether the data is in error by checking a check-sum of the data SDA. If no error occurs, the slave timing controller 200 ₃ transmits a transmission completion signal to the slave timing controller 200 ₂ through the first data input / output terminal SDA0_INOUT. When an error occurs, the slave timing controller 200 ₃ re-receives data SDA from the second data input / output terminal SDA1_INOUT of the slave timing controller 200 ₂ .

In the same way, when the rest of the slave timing controller (200 ₄ -200 _n-1) also receives the data (SDA) is completed, the received data to an adjacent slave timing controller operating in the slave mode to operate from the I2C communication process in the master mode, Send (SDA). When the data SDA is transmitted to the last slave timing controller 200 _n , the data SDA transmission in the plurality of timing controllers having the same address is completed.

As such, the master timing controller 200 ₁ of the data transmission and reception apparatus according to the embodiment of the present invention first performs I2C communication with the memory 100 to receive data SDA, and then, to the adjacent slave timing controller 200 ₂ . Send the data SDA. At this time, when the reception of the data SDA is completed, the slave timing controller 200 ₂ operates in the master mode to transmit the data SDA to the next adjacent slave timing controller, and in the same manner, to the last slave timing controller 200 _n . Send the data SDA.

As described above, in the data transmission / reception apparatus based on the multi-drop structure having two or more identical addresses according to an embodiment of the present invention, the timing controller selected as the master timing controller 200 ₁ is first used as the memory 100. and performing an I2C communication by receiving data (SDA), and the slave timing controller (200 ₂₎ adjacent to the master timing controller (200 _1), the rest of the slave timing control other than the (200 ₂ -200 _n), the master timing controller (200 ₁ ) After receiving the data SDA from ₁ ), it operates in the master mode and transmits the data SDA to the next slave timing controller again by the same method, thereby preventing collision between a plurality of timing controllers having the same address. Can perform normal I2C communication. In addition, since the I2C communication is performed by setting the master timing controller or the slave timing controller according to the chip mode decision signal applied from the outside for each timing controller without changing the I2C bus structure, it is possible to reduce the production cost of manufacturing the substrate. .

Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

1 is a diagram illustrating an example of I2C communication in a data transmission / reception apparatus for transmitting and receiving conventional data.

FIG. 2 is a diagram illustrating a signal for explaining an I2C interface in the transmission and reception system shown in FIG. 1.

3 is a view schematically showing a data transmission and reception apparatus according to an embodiment of the present invention.

Claims (13)

A master timing controller connected to the memory, and A plurality of slave timing controllers connected in series with the master timing controller, The master timing controller receives data from the memory, and transmits the data to an adjacent slave timing controller of the plurality of slave timing controllers, Each slave timing controller receives the data from a slave timing controller adjacent in a first direction among the plurality of slave timing controllers and transmits the data to a slave timing controller adjacent in a second direction different from the first direction among the plurality of slave timing controllers. Data transmitting and receiving device for transmitting the data. The method of claim 1, The data transmission and reception device is performed by the inter-integrated circuit (I2C) communication. The method of claim 1, And the master timing controller and the plurality of slave timing controllers have the same address. The method of claim 1, And the master timing controller operates in a master mode to receive the data from the memory. The method of claim 1, Each of the slave timing controllers is operated in a slave mode to receive the data from the master timing controller or a slave timing controller adjacent in the first direction, And transmitting the data to a timing controller adjacent to the second direction in the master mode. The method of claim 5, Each slave timing controller operates in the master mode when the reception of the data is completed. The method of claim 1, The master timing controller and the plurality of slave timing controllers each include a chip mode determination terminal, And the master timing controller and the plurality of slave timing controllers are distinguished by setting the chip mode determination terminal. The method according to any one of claims 1 to 7, And the data includes a signal used to control the display device. In the timing controller for transmitting and receiving data, A first clock input terminal for receiving a clock signal, A first data input / output terminal configured to receive the data in synchronization with the clock signal, A second clock output terminal connected to an adjacent timing controller, A second data input / output terminal connected to the adjacent timing controller, and A chip main body which outputs the clock signal to the second clock output terminal and outputs the data to the second data input / output terminal in synchronization with the clock signal output to the second clock output terminal; Timing controller comprising a. 10. The method of claim 9, Further comprising a chip mode determination terminal, And the timing controller determines, by the setting of the chip mode determination terminal, either the master timing controller directly communicating with the memory storing the data or the slave timing controller receiving the data from an adjacent timing controller. The method of claim 10, When the timing controller is the slave timing controller, And the chip body operates in a master mode when outputting the data to the second data input / output terminal. 10. The method of claim 9, The data controller is a timing controller performed by the inter-integrated circuit (I2C) communication. The method according to any one of claims 9 to 12, And the data includes a signal used to control a display device.

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